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DTSTAMP:20260730T152729Z
LOCATION:Seaside Ballroom B
DTSTART;TZID=America/Los_Angeles:20260728T110000
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UID:dac_DAC 2026_sess272_ENGPRES367@linklings.com
SUMMARY:ANA-MODELGEN: Automating Analog IP Model Generation and Validation
  for Efficient Mixed-Signal Verification
DESCRIPTION:Aadhar Sharma (Texas Instruments (TI)); Parthasarthy Ramesh, R
 inu Mathew, and David Mendoza (Texas Instruments); Sooraj Sekhar (Texas In
 struments (TI)); and Srijan Soni (Texas Instruments)\n\nAnalog IP verifica
 tion remains a bottleneck in modern mixed-signal SoC development  due to l
 engthy SPICE simulation times and integration challenges. This paper intro
 duces  ANA-MODELGEN, a comprehensive hierarchical modeling methodology tha
 t transforms analog IP verification through automated model generation and
  validation. Our approach enables rapid development and validation of beha
 vioral models for any analog IP type, featuring direct integration capabil
 ities with industry-standard verification environments. The methodology in
 cludes automated testbench generation for rigorous model validation and eq
 uivalence checking against SPICE references. Deployment in production SoC 
 verification flows demonstrates substantial gains in functional coverage a
 nd execution speed, enabling earlier bug detection and faster time-to-mark
 et.\n\nTopics: Design, EDA, Systems\n\nSession Chair: Nanditha Rao (IBM)\n
 \n
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