BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260730T152728Z
LOCATION:Seaside Ballroom B
DTSTART;TZID=America/Los_Angeles:20260728T114500
DTEND;TZID=America/Los_Angeles:20260728T120000
UID:dac_DAC 2026_sess272_ENGPRES172@linklings.com
SUMMARY:Custom Implementation of High-Speed Digital Blocks using Virtuoso 
 Studio
DESCRIPTION:Pratik Korde and Sumanth S (Cadence Design Systems, Inc.) and 
 Kishan Chanumolu (Micron)\n\nHigh-speed digital blocks integrated within t
 raditional Place & Route flows pose verification and implementation challe
 nges that analog-centric methodologies cannot fully address. As process te
 chnologies scale and timing margins shrink, these blocks exhibit strong se
 nsitivity to parasitics, layout-dependent effects, and high-frequency inte
 ractions, demanding enhanced automation and predictability. While the Cade
 nce Virtuoso studio provides unmatched control for custom transistor-level
  design and leverages Cadence Innovus for digital automation, it lacks cap
 abilities for automated Structured Data Path (SDP) file and routing constr
 aint creation from source.\n\nThis work introduces a unified implementatio
 n approach that bridges this gap by enabling SDP-based placement for custo
 m standard cells with auto-generating SDP file from schematic or Verilog, 
 and creating routing constraints such as matching and shielding based on n
 et prefixes/suffixes from schematic/Verilog. The methodology improves desi
 gn scalability, reduces manual effort, and strengthens flow automation for
  high-speed digital blocks. By combining Virtuoso studio custom design fle
 xibility with Innovus-driven automation, the proposed solution delivers a 
 robust, layout-aware implementation flow suited for next-generation high-p
 erformance SoC and PHY architectures.\n\nTopics: Design, EDA, Systems\n\nS
 ession Chair: Nanditha Rao (IBM)\n\n
END:VEVENT
END:VCALENDAR