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DTSTAMP:20260730T152726Z
LOCATION:Seaside Ballroom B
DTSTART;TZID=America/Los_Angeles:20260728T113000
DTEND;TZID=America/Los_Angeles:20260728T114500
UID:dac_DAC 2026_sess272_ENGPRES036@linklings.com
SUMMARY:Scalable, Protocol-Agnostic Clockless In-Band Reset Architecture f
 or Serial Link IPs in Multi-Domain SoCs
DESCRIPTION:Aradhana Kumari and Ankur Bal (STMicroelectronics)\n\nModern m
 ulti-domain SoCs almost always integrate serial link IPs, making reliable 
 system reset a critical challenge, especially when clock generation circui
 try is compromised. Conventional out-of-band reset schemes require dedicat
 ed pins, limiting scalability, while existing in-band reset solutions depe
 nd on clock availability, rendering them unreliable in certain failure sce
 narios. This paper introduces a scalable, protocol-agnostic, clockless in-
 band reset architecture that ensures deterministic SoC reset through preci
 se reset pulse width generation without relying on any clock source. The p
 roposed design partitions functionality into PHY and controller blocks, in
 corporating a Reset Pattern Detector (RPD) for robust reset signaling. Dem
 onstrated on an MIPI I3C controller subsystem, the architecture is easily 
 portable to PCIe, eSPI, USB, SATA, DisplayPort, Ethernet, and other protoc
 ols. Key advantages include guaranteed reset duration, independence from S
 oC size or complexity, technology agnosticism, and non-intrusiveness to ex
 isting IP standards. This approach significantly enhances system reliabili
 ty and scalability for heterogeneous SoCs, supporting error recovery, sync
 hronization, and security-critical applications across diverse wired inter
 faces.\n\nTopics: Design, EDA, Systems\n\nSession Chair: Nanditha Rao (IBM
 )\n\n
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