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DTSTAMP:20260730T152652Z
LOCATION:Seaside Ballroom B
DTSTART;TZID=America/Los_Angeles:20260728T103000
DTEND;TZID=America/Los_Angeles:20260728T120000
UID:dac_DAC 2026_sess272@linklings.com
SUMMARY:IP Design for Mixed-signal and High-speed SoCs
DESCRIPTION:This session presents scalable, signoff-driven methodologies f
 or designing and validating IPs in analog computing, mixed-signal verifica
 tion, high-speed serial interfaces, and custom digital blocks. The topics 
  cover programmable and synthesizable analog optimization IP, automated an
 alog model generation,   formal verification for protocol correctness,  po
 wer-integrity analysis for large SerDes designs, and  architectures for mu
 lti-domain SoCs. Together, these works demonstrate how automation, scalabi
 lity, and verification enable reliable IP development from early design th
 rough sign-off.\n\n"\n\nA Programmable, Synthesizable CMOS Analog Optimiza
 tion IP Core for Real-Time Control\n\nThis work presents an automated EDA 
 toolchain for synthesizing programmable and scalable CMOS analog optimizat
 ion IP cores. Addressing the latency wall in real-time control, where conv
 entional digital solvers face polynomial scaling bottlenecks, our methodol
 ogy translates high-level mathematical spe...\n\n\nPriyanshu Sahu, Swapnil
  Sharma, Sachin Khoja, and Palak Jain (Vellex Computing) and Jason Poon (C
 al Poly, San Luis Obispo)\n---------------------\nNo Credit Where Credit I
 s Due: Quiesced Formal Check for PCIe Crediting\n\nPCIe Gen6/7 introduces 
 major architectural enhancements to meet the bandwidth and latency demands
  of AI and datacentre workloads. Bandwidth doubles from 32 GT/s to 64 GT/s
  to 128GT/s through support for PAM4 signalling, flit‑based transfers, and
  multiple virtual channels (VCs). These capabilit...\n\n\nIsha Lale, Pradi
 p Prajapati, and Anshul Jain (Synopsys)\n---------------------\nANA-MODELG
 EN: Automating Analog IP Model Generation and Validation for Efficient Mix
 ed-Signal Verification\n\nAnalog IP verification remains a bottleneck in m
 odern mixed-signal SoC development  due to lengthy SPICE simulation times 
 and integration challenges. This paper introduces  ANA-MODELGEN, a compreh
 ensive hierarchical modeling methodology that transforms analog IP verific
 ation through automated model ...\n\n\nAadhar Sharma (Texas Instruments (T
 I)); Parthasarthy Ramesh, Rinu Mathew, and David Mendoza (Texas Instrument
 s); Sooraj Sekhar (Texas Instruments (TI)); and Srijan Soni (Texas Instrum
 ents)\n---------------------\nA Distributed and Scalable Dynamic Power Int
 egrity Flow from Early Analysis to Sign-off for Large-Scale SerDes Designs
 \n\nFor large-scale SerDes designs, dynamic power integrity sign-off is be
 coming increasingly challenging due to growing design scale and performanc
 e demands. Modern SerDes integrate analog blocks, digital blocks, sensitiv
 e clocks, decaps with complex Power Delivery Network (PDN) design. Such de
 signs ca...\n\n\nXin Shu, Jinrong Yan, Hang Sun, Xuewei Ding, and Xiaofan 
 Lu (Sanechips Technology Co.,Ltd) and Xiaomei You and Jie Cheng (Synopsys)
 \n---------------------\nScalable, Protocol-Agnostic Clockless In-Band Res
 et Architecture for Serial Link IPs in Multi-Domain SoCs\n\nModern multi-d
 omain SoCs almost always integrate serial link IPs, making reliable system
  reset a critical challenge, especially when clock generation circuitry is
  compromised. Conventional out-of-band reset schemes require dedicated pin
 s, limiting scalability, while existing in-band reset solutions ...\n\n\nA
 radhana Kumari and Ankur Bal (STMicroelectronics)\n---------------------\n
 Custom Implementation of High-Speed Digital Blocks using Virtuoso Studio\n
 \nHigh-speed digital blocks integrated within traditional Place & Route fl
 ows pose verification and implementation challenges that analog-centric me
 thodologies cannot fully address. As process technologies scale and timing
  margins shrink, these blocks exhibit strong sensitivity to parasitics, la
 yout-d...\n\n\nPratik Korde and Sumanth S (Cadence Design Systems, Inc.) a
 nd Kishan Chanumolu (Micron)\n\nTopics: Design, EDA, Systems\n\nSession Ch
 air: Nanditha Rao (IBM)
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