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DTSTAMP:20260730T152729Z
LOCATION:Seaside Ballroom A
DTSTART;TZID=America/Los_Angeles:20260729T133000
DTEND;TZID=America/Los_Angeles:20260729T134500
UID:dac_DAC 2026_sess269_ENGPRES153@linklings.com
SUMMARY:Accelerating X-State Aware Power Simulation using Advanced Hardwar
 e Emulation
DESCRIPTION:Jihye Lim, Yungi Um, Sungtae Kang, Jihyun Jang, and Youngsik K
 im (Samsung Electronics)\n\nWith the advent of the A.I era, the amount of 
 handling data of SOC has sky-rocketed and power consumption inevitably inc
 reased. To suppress this phenomenon, various low-power hardware architectu
 res have been added to the SOC and consequently 1) "X" values that cause b
 ugs at silicon level have appeared and 2) verification complexity and TAT 
 have increased to detect "X". Emulator is a general solution for reducing 
 verification time, but it degrades the quality of power verification since
  it can only express two logical states ("0" and "1"). In this study, we p
 ropose a high performance 4-state ("0", "1", "X", and "Z") RTL power-aware
  simulation methodology leveraging an emulator. This methodology focuses o
 n the precise modeling of UPF (Unified Power Format) intents and 4-state l
 ogic, which are vital for capturing realistic power behavior. We demonstra
 te that the seamless verification of UPF-driven power scenarios at hardwar
 e speeds while maintaining the logic granularity of 4-state simulation. Fi
 nally, by applying to the latest SOC project, we confirm that there is a 3
 5 times performance gain compared to conventional simulation.\n\nTopics: E
 DA, Systems\n\nSession Chair: Dave Rich\n\n
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