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DTSTAMP:20260730T152730Z
LOCATION:Seaside Ballroom A
DTSTART;TZID=America/Los_Angeles:20260727T103000
DTEND;TZID=America/Los_Angeles:20260727T104500
UID:dac_DAC 2026_sess265_ENGPRES169@linklings.com
SUMMARY:Progress-Based Timeout Debug for Scalable SoC Verification
DESCRIPTION:Vikash Kumar (ARM) and Yunus Akhtar (-)\n\nTimeout failures ar
 e among the most resource-intensive issues in System-on-Chip (SoC) verific
 ation, frequently manifesting as silent execution hangs with no explicit d
 iagnostic signature. In large-scale regression environments, such failures
  can consume a significant fraction of total simulation resources and acco
 unt for a disproportionate share of debug effort. Conventional mechanisms,
 \nincluding global watchdogs, UVM heartbeats, and waveform-based analysis,
  typically provide only reactive termination without isolating the underly
 ing root cause across RTL, testbench, or firmware layers.\n\nThis paper in
 troduces a deterministic and protocol-aware framework for timeout root-cau
 se isolation in UVM-based verification environments. The framework integra
 tes distributed telemetry agents, localized watchdogs, and transaction-agi
 ng monitors across verification layers to enable real-time\ncorrelation of
  causal dependencies. Timeout events are automatically classified into arc
 hitectural, testbench, and system-level handshake categories using tempora
 l and protocol-aware analysis.\n\nAcross more than 500 large-scale regress
 ion runs, the proposed framework reduced average timeout debug effort by 6
 5–75%, lowered re-run frequency by approximately 40%, and improved overall
  schedule predictability. By transforming non-diagnostic global hangs into
  localized, actionable failure signatures, this approach enables structure
 d timeout debug and proactive failure prevention in modern SoC verificatio
 n flows.\n\nTopics: EDA\n\nSession Chair: Chandrakanth Betageri (Intel)\n\
 n
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