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DTSTAMP:20260730T152651Z
LOCATION:Seaside Ballroom A
DTSTART;TZID=America/Los_Angeles:20260727T103000
DTEND;TZID=America/Los_Angeles:20260727T120000
UID:dac_DAC 2026_sess265@linklings.com
SUMMARY:Precision in Practice: Advanced verification techniques for modern
  silicon
DESCRIPTION:Join us to explore practical, high-impact verification strateg
 ies designed to keep pace with the growing scale and complexity of modern 
 silicon. Verification teams must adopt more precise, scalable, and intelli
 gent methodologies, spanning the journey from architectural intent to sili
 con-ready implementation.\n\nProgress-Based Timeout Debug for Scalable SoC
  Verification\n\nTimeout failures are among the most resource-intensive is
 sues in System-on-Chip (SoC) verification, frequently manifesting as silen
 t execution hangs with no explicit diagnostic signature. In large-scale re
 gression environments, such failures can consume a significant fraction of
  total simulation res...\n\n\nVikash Kumar (ARM) and Yunus Akhtar (-)\n---
 ------------------\nUVM-MS: A Novel Approach to Mixed-Signal IP Verificati
 on\n\nTraditional analog mixed-signal (MS) IP verification relies heavily 
 on analog-centric simulations, such as Monte Carlo simulations, which focu
 s solely on analog behavior . This approach leads to significant drawbacks
 , including the inability to accurately model loading effects, kickbacks, 
 and refere...\n\n\nPritam Panigrahi, Aadhar Sharma, and Kumar Singh (Texas
  Instruments (TI)) and Shivam Gupta and Aadhar Sharma (Texas Instruments)\
 n---------------------\nSTEER: Simulation of Templates Engine for Efficien
 t Resource Usage\n\nCoverage-Directed Generation (CDG) accelerates functio
 nal verification closure by iteratively optimizing constrained-random test
  templates that target under-exercised design functionalities, but it requ
 ires substantial compute for each optimization simulation phase. STEER (Si
 mulation of Templates En...\n\n\nMelchizedek Das, Devleena Ghosh, Ketul Pa
 tel, Arun Joseph, and Arvind Haran (IBM Research)\n---------------------\n
 Building an Ontology-Driven Knowledge Graph for Constraint-Aware Navigatio
 n of Semiconductor Design Documents\n\nSemiconductor design involves exten
 sive documentation, often spanning hundreds of pages in documents with hig
 hly intricate and complex internal relationships, making manual navigation
  and cross-referencing highly inefficient. To overcome this critical bottl
 eneck, we implemented a solution that signi...\n\n\nJongwoo Ryu, JungSub K
 oh, Sungsu Kim, MinYoung Cho, DongKyu Kim, and Youngsik Kim (Samsung Elect
 ronics)\n---------------------\nArchitectural Coverage Analysis and ML-bas
 ed Automated-test generation\n\nVerification coverage analysis evaluates t
 he effectiveness of verification stimulus on design verification. Signific
 ant computational resources are spent toward coverage closure. Robust infr
 astructure and tools are available to analyze large coverage data to effic
 iently allocate resources to the mos...\n\n\nBryan Hickerson, Arvind Haran
 , Tuhin Mahmud, and Manoj Dusanapudi (IBM Research)\n---------------------
 \nDFT Ready Design with SCO Canvas : Shift Left of DFT Designs\n\nAs semic
 onductor designs scale in complexity, Design-for-Test (DFT) has become a c
 ritical bottleneck, often delayed until the post-RTL freeze stages. This p
 aper introduces a novel "DFT-Ready Design" methodology using SOC Canvas to
  bridge the chronic gap between system design and DFT. Unlike conventi...\
 n\n\nHoyeon Jeon (ITDA semiconductor Co.,Ltd.)\n\nTopics: EDA\n\nSession C
 hair: Chandrakanth Betageri (Intel)
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