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DTSTAMP:20260730T152728Z
LOCATION:DAC Pavilion\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260727T170000
DTEND;TZID=America/Los_Angeles:20260727T180000
UID:dac_DAC 2026_sess264_ENGPOST089@linklings.com
SUMMARY:Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets
  Integration: A System-Technology Co-Optimization (STCO) Perspective on Sp
 atial-Temporal Temperature Uniformity
DESCRIPTION:Yuan Chen (WITMEM); Mingyang Liu (Hangzhou Zhicun (Witmem) Tec
 hnology Co., Ltd.); yu tian (Beijing Zhicun (Witmem) Technology Co., Ltd);
  Runjian Wang and Yue Heng (Hangzhou Zhicun (Witmem) Technology Co., Ltd.)
 ; hengzhi hu (Witintech); Yi Chen (Hangzhou Zhicun (Witmem) Technology); M
 in Cai (Witintech); Long Kong (Fudan University); and Ran Zhang and haixun
  lian (Synopsys)\n\nAnalog Compute-In-Memory performance in 3D heterogeneo
 us chiplet integration is highly sensitive to spatial temperature gradient
 s and temporal temperature fluctuations. Conventional thermal sign-off bas
 ed on the maximum junction temperature is insufficient for ensuring the me
 mory algorithmic precision across diverse operational phases. This study p
 roposes a System-Technology Co-Optimization (STCO) framework featuring The
 rmal Avoidance and Thermal Compensation strategies to enhance spatial-temp
 oral temperature uniformity. The approach synergizes hardware-level spatia
 l optimization, such as selective transistor density reduction and control
 lable heating element deployment, with software-level temporal regulation,
  such as load-rate modulation and dummy workflow supplement. The proposed 
 strategies are validated by the thermal simulations of an 8-layer memory s
 tack on a high-power SoC utilizing a granular Chip Thermal Model (CTM). Th
 e results demonstrate that the SoC-adjacent memory die has the highest the
 rmal risk and the strategies can reduce its spatial temperature gradient b
 y up to 25%. This work provides a practical, early-stage STCO solution for
  maintaining memory reliability and functional integrity in advanced 3D in
 tegrated systems.\n\nTopics: AI, Chiplet, Design, EDA, Quantum, Security, 
 Systems\n\n
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