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DTSTAMP:20260730T152729Z
LOCATION:Seaside Ballroom B
DTSTART;TZID=America/Los_Angeles:20260727T104800
DTEND;TZID=America/Los_Angeles:20260727T110600
UID:dac_DAC 2026_sess262_ENGPRES250@linklings.com
SUMMARY:Automated Verification and Performance Analysis for Chiplets
DESCRIPTION:Joshua Lam and Batu Bayram (Cadence Design Systems, Inc.)\n\nC
 hiplets allow flexibility of design, enabling higher yields and faster tur
 naround times compared to monolithic SoCs. As part of creating the Cadence
  chiplet development solution, various areas for automation were identifie
 d to speed up the emulation and performance processes, thereby reducing th
 e time required to bring chiplet designs to market.  \n\nProvision of emul
 ation platforms early in the design cycle allow real hardware to be used b
 y stakeholders such as system architects and software developers, allowing
  them to kick-off their activities significantly earlier, and reducing int
 er-team dependencies by creating a cohesive flow between all departments. 
  \n\nThe verification flow uses outputs from design automation to generate
  the simulation & emulation platforms, the verification environment and te
 sts. Tests are written using the Accellera Portable Test and Stimulus Stan
 dard (PSS) to allow C code to be generated for different target platforms,
  reducing duplication and saving effort and time.  \n\nThe flow further ge
 nerates the performance testing suite allowing metrics to be automatically
  retrieved between any defined source and end point using the Cadence Syst
 em Performance Analyser. Availability of performance metrics early in the 
 design cycle results in earlier design closure, reducing late architectura
 l changes and increasing confidence in functionality and performance.\n\nT
 opics: AI, EDA, Systems\n\nSession Chair: Karunveer Singh (Meta)\n\n
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