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DTSTAMP:20260730T152728Z
LOCATION:Exhibitor Forum\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260729T103000
DTEND;TZID=America/Los_Angeles:20260729T110000
UID:dac_DAC 2026_sess240_EF104@linklings.com
SUMMARY:GOOGLE: From Infrastructure to AI: Taping Out Data Center Silicon 
 on a Workload-Optimized, Agent-Driven EDA Stack
DESCRIPTION:Sathya Narasimhan (Google)\n\nAs semiconductor designs advance
  toward trillion-transistor systems, general-purpose infrastructure can be
 come a bottleneck, slowing down design velocity and impacting your bottom 
 line. In this session, we'll provide a technical deep dive into the worklo
 ad-optimized EDA stack that Google uses to tape out its own data center ch
 ips —including the Ironwood TPU and ARM-based Axion processors—all entirel
 y on Google Cloud.\n\nWe'll explore how to deploy high-performance compute
  and storage foundations to meet the intense demands of modern chip design
 . We'll detail how our H4D and C4A instances, paired with Google Cloud Net
 App Volumes (GCNV), are engineered to handle the rigorous I/O and low-late
 ncy requirements of large-scale verification and physical design. Furtherm
 ore, we'll demonstrate how Alphabet is integrating AI directly into the pr
 oduction flow including using agents to optimize Verilog code and achieve 
 targeted improvements in Power, Performance, and Area (PPA), effectively d
 e-risking complex design cycles through a cloud-native, AI-integrated appr
 oach.\n\n
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