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DTSTAMP:20260730T152728Z
LOCATION:Exhibitor Forum\, Exhibit Floor
DTSTART;TZID=America/Los_Angeles:20260728T134500
DTEND;TZID=America/Los_Angeles:20260728T141500
UID:dac_DAC 2026_sess236_EF103@linklings.com
SUMMARY:CHIPAGENTS AI: AI Agent-Driven Timing Closure
DESCRIPTION:Mehir Arora, William Wang, Nikolas Belle, and Dakota Barnes (C
 hipAgentsAI)\n\nTiming closure remains one of the most iteration-heavy bot
 tlenecks in chip design, spanning multiple teams and abstraction levels fr
 om RTL through signoff. Each iteration requires running tools that take ho
 urs to days, making the feedback loop between identifying a timing violati
 on and validating a fix prohibitively slow. Extracting actionable signal f
 rom massive timing reports, mapping timing violations back to RTL, and cho
 osing among fixes with complex PPA tradeoffs demand deep expertise and rem
 ain largely manual. We explore how AI agents can be applied to this proble
 m: what domain-specific capabilities they need beyond general code generat
 ion and how an agent-driven "shift-left" strategy can reduce iteration cou
 nt and accelerate convergence. We present ChipAgents' approach to timing c
 losure along with the lessons we've learned along the way.\n\n
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