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BEGIN:VEVENT
DTSTAMP:20260730T152729Z
LOCATION:Mtg Room 201B
DTSTART;TZID=America/Los_Angeles:20260727T164200
DTEND;TZID=America/Los_Angeles:20260727T165400
UID:dac_DAC 2026_sess164_RESEARCH3153@linklings.com
SUMMARY:A Boolean Processor-Based Hardware Emulation System with Reconfigu
 rable Interconnects
DESCRIPTION:Ruiyao Pu, Muhan Li, Li Shang, and Fan Yang (Fudan University)
 \n\nExisting Boolean processor-based (BP-based) hardware emulation systems
  typically rely on fixed interconnects, which often suffer from severe ban
 dwidth underutilization under highly imbalanced traffic. We propose a BP-b
 ased hardware emulation system with hierarchical reconfigurable interconne
 cts. At both the inter-chip and intra-chip levels, our system dynamically 
 reallocates idle interconnect lanes from low-traffic pairs to high-demand 
 pairs, alleviating communication bottlenecks and improving interconnect ut
 ilization without modifying the underlying ASIC fabric. The hardware is co
 -designed with the compiler, which profiles communication, generates per-l
 ane configuration tables and scheduling strategies, and programs the inter
 connect via registers. Experimental results on industrial digital designs 
 show up to 64% emulation performance improvement and an average 27% reduct
 ion in compilation time, with only 7.4% area overhead compared to a fixed-
 interconnect baseline system.\n\nTopics: EDA\n\nTrack: EDA2. Design Verifi
 cation and Validation\n\nSession Chairs: Deming Chen (University of Illino
 is at Urbana-Champaign) and Sabya Das (Synopsys)\n\n
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