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Session

Event Type
Research Manuscript
TimeWednesday, July 295:30pm - 6:00pm PDT
Location
Tracks
Systems
Tags
EDA6. Analog CAD
Simulation
Verification and Test; Design
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; AI
AI2-II. AI/ML Algorithms and Models; EDA
EDA7-I. Physical Design and Verification; AI
SEC2. Hardware Security: Primitives
Architecture
SYS5. Embedded Memory and Storage Systems; EDA
AI5-II. AI/ML System and Platform Design; Security
Design & Test
Presentations
5:30pm - 5:30pm PDTBSGCN: Taming Diverse Sparsities in GCNs via Adaptive Band-Segmentation and Tailored Caching
5:30pm - 5:30pm PDTAlphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search
5:30pm - 5:31pm PDTEASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs
5:31pm - 5:31pm PDTAdagscale: Viewpoint-Adaptive Gaussian Scaling in 3D Gaussian Splatting to Reduce Gaussian-Tile Pairs
5:31pm - 5:32pm PDTLATTE: Legality-Assured Differentiable Timing-Driven Detailed Placement
5:32pm - 5:32pm PDTAccelerating GPU Inference of Large Language Models with Moderately Unstructured Sparse Weight Matrices
5:32pm - 5:33pm PDTLeveraging AI-Inspired Hardware Architecture to Enhance LPN Acceleration in Post-Quantum Cryptography
5:33pm - 5:33pm PDTKnowledge-Driven Hybrid SSD Management Enhanced by Fine-Tuned LLMs
5:33pm - 5:33pm PDTSP2RINT: Spatially-Decoupled Physics-Constrained Progressive Inverse Optimization for Diffractive Optical Neural Network Training
5:33pm - 5:34pm PDTPhotomt : Accelerating Zero-Knowledge Proofs with a Photonic-Electronic Merkle Tree Engine
5:34pm - 5:34pm PDTFlowplace: Flow Matching for Chip Placement
5:34pm - 5:35pm PDTCell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm
5:35pm - 5:35pm PDTPillarsparse: Rethinking Unstructured Sparse Formats for Tensor Cores
5:35pm - 5:36pm PDTAthena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage
5:36pm - 5:36pm PDTSpecANNS: Accelerating Graph-Based Approximate Nearest Neighbor Search with Speculative In-Storage Computing
5:36pm - 5:36pm PDTPerifi:physics-Infused RF Inverse Design with Parametric Data-Efficient Feasible-Region Sampling
5:36pm - 5:37pm PDTZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
5:37pm - 5:37pm PDTHow Can Reinforcement Learning Achieve Expert-Level Placement?
5:37pm - 5:38pm PDTLearning-Based Slack-Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
5:38pm - 5:38pm PDTEcprefix: Erasure-Coded Prefix KV Cache for Optimizing Load Balancing in Large Language Model Serving
5:38pm - 5:39pm PDTTowards Practical Live Migration for Heterogeneous Confidential Virtual Machines
5:39pm - 5:39pm PDTVALVE: Accelerating Visible Version Searching in HTAP Systems via In-Storage Computing
5:39pm - 5:40pm PDTPcbgen: Self-Evolving LLM Agent for Specification-to-Schematic PCB Design with Parameter Tuning
5:40pm - 5:40pm PDTISA-PM: A Unified ISA Extension and Microarchitecture Enabling Efficient ECPM in IoT Devices
5:40pm - 5:40pm PDTENACT: Ensemble Neural Fields for Reactive Robot Control
5:40pm - 5:41pm PDTHyPAS: A Hybrid Optimization Framework for Placement and Sizing Co-Optimization
5:41pm - 5:41pm PDTCoX-MoE: Coalesced Expert Execution for High-Throughput MoE Inference with AMX-Enabled CPU-GPU Co-Execution
5:41pm - 5:42pm PDTSparsee: Unlocking Sparsities in Encrypted Sparse Matrix Multiplication via Hardware-Software Co-Design
5:42pm - 5:42pm PDTFlashhd: A Flash-Based In-Storage Hyperdimensional Computing Framework for Hierarchical Sequence Matching
5:42pm - 5:43pm PDTCOmPOSER: Circuit Optimization of mm-Wave/rf Circuits with Performance-Oriented Synthesis for Efficient Realizations
5:43pm - 5:43pm PDTATTINA: Spatial Acceleration of Additive Number Theoretic Transform for Energy-Efficient zkSNARKs at the Edge
5:43pm - 5:43pm PDTExcavating Consistency Across Editing Steps for Effective Multi-Step Image Editing
5:43pm - 5:44pm PDTToward True-3D Timing-Driven Analytical Global Placement for Mixed-Size Face-to-Face 3D ICs
5:44pm - 5:44pm PDTExpertflow: Efficient Mixture-of-Experts Inference via Predictive Expert Caching and Token Scheduling
5:44pm - 5:45pm PDTPIMA-SecDB: Processing-in-Memory Acceleration for Fully Homomorphic Encryption Databases
5:45pm - 5:45pm PDTExpcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models
5:45pm - 5:46pm PDTDiffsp: Differentiable Sequence Pair-Based Analog Placement
5:46pm - 5:46pm PDTCO-MAC: A Center-Out Ordered Stochastic MAC for Low-Latency Inference
5:46pm - 5:46pm PDTGSR-GNN: Training Acceleration and Memory-Saving Framework of Deep GNNs on Circuit Graph
5:46pm - 5:47pm PDTIntegrated Timing-Driven Placement for Hybrid-Bonding-Based Face-to-Face 3D ICs
5:47pm - 5:47pm PDTAdana: Accelerating Large Language Models via Adaptive Nonuniform Asymmetric Quantization
5:47pm - 5:48pm PDTAre They All Safe? Practical Fault Injection Attacks on FPGA Logic Synthesis Tools
5:48pm - 5:48pm PDTEtherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead
5:48pm - 5:49pm PDTStochastic Diffusion Prior: Knowledge Elicitation and Local Adaptation for Transistor Sizing
5:49pm - 5:49pm PDTALOHA: Area-Efficient and Low-Power Stochastic Computing with Hammersley Sequences
5:49pm - 5:50pm PDTPBA-rGAT-Edge: Arc-Level Path-Based Timing Prediction with Scalable Residual Edge-Aware Graph Attention
5:50pm - 5:50pm PDTAnalytically-Derived Hybrid Net–pin Weighting for Timing-Driven Global Placement
5:50pm - 5:50pm PDTHW-Router: Hardware-Aware Routing for Scalable Multi-LLM Serving
5:50pm - 5:51pm PDTRaise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography
5:51pm - 5:51pm PDTNash: A Neighbor-Aware Shared Memory Design on GPU for Accelerating AI Workloads
5:51pm - 5:52pm PDTOpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM
5:52pm - 5:52pm PDTEHPC: Efficient Heterogeneous Probabilistic Computing Architecture for Combinatorial Optimization Acceleration
5:52pm - 5:53pm PDTOperator-Level Acceleration for Sparse 3D Object Detection
5:53pm - 5:53pm PDTATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer
5:53pm - 5:53pm PDTOrchestrating Dual-Boundaries: An Arithmetic Intensity Inspired Acceleration Framework for Diffusion Language Models
5:53pm - 5:54pm PDTReal-Time, Lightweight, High Coverage Error Detection and Correction for CRYSTALS with Small-Modulus Paths
5:54pm - 5:54pm PDTCOM-BNN: A Configurable Low Power MRAM-Based Computing-in-Memory Accelerator for Binary Convolutional Computations
5:54pm - 5:55pm PDTExploiting Function-Family Structure in Analog Circuit Optimization
5:55pm - 5:55pm PDTiADS: In-Situ Adaptive Diffusion Sampling Architecture Based on Voltage-Tunable P-Bits
5:55pm - 5:56pm PDTTRACE: Learning to Compute on Circuit Graphs
5:56pm - 5:56pm PDTAdvancing Macro Placement: Integrating Proven Design Practices with Reinforcement Learning
5:56pm - 5:56pm PDTOptimizing Dynamic-Shape Neural Networks: A Unified Approach to Adaptive Tuning
5:56pm - 5:57pm PDTATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification
5:57pm - 5:57pm PDTOnyx: Efficient Transaction Processing with Real Processing-in-Memory Prototypes
5:57pm - 5:58pm PDTATLAS: Asynchronous Topological Learning for Accurate FIT Prediction via Decoupled Graph Neural Networks
5:58pm - 5:58pm PDTDRIFT: Harnessing Inherent Fault Tolerance for Efficient and Reliable Diffusion Model Inference
5:58pm - 5:59pm PDTFlashfps: Efficient Farthest Point Sampling for Large-Scale Point Clouds via Pruning and Caching
5:59pm - 5:59pm PDTIR-Drop Aware Global Placement with PDN Optimization and GPU-Accelerated Analysis for Mitigating Global and Local IR-Drop
5:59pm - 6:00pm PDTSTELLAR: Structure-Guided LLM Assertion Retrieval and Generation for Formal Verification