Close

Session

Event Type
Research Manuscript
TimeWednesday, July 2912:30pm - 1:00pm PDT
Location
Topics
AI
Tracks
AI5-I. AI/ML System and Platform Design
Tags
AI4-II. AI/ML Architecture Design; AI
AI4-I. AI/ML Architecture Design; Design
DES2B-II. In-memory and Near-memory Computing Architectures
Applications and Systems; EDA
EDA2. Design Verification and Validation; Systems
SYS3. Embedded Software; Systems
SYS6. Time-Critical and Fault-Tolerant System Design; AI
Presentations
12:30pm - 12:30pm PDTPiHG: A Redundancy-Free Heterogeneous Graph Neural Network Accelerator via a Pivot-Centric Approach
12:30pm - 12:30pm PDTPFGEMM: Fully Exploiting the Parallelism of SpGEMM With Element-Wise Out-of-Order Execution Flow and Prefix Decomposition of Indices
12:30pm - 12:31pm PDTA Fully Analog Continuous-Time CIM Neural ODE Solver for Flow-Matching-Based Fluid Dynamics Generation
12:31pm - 12:31pm PDTPRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
12:31pm - 12:32pm PDTDySL-VLA: Efficient Vision-Language-Action Model Inference via Dynamic-Static Layer-Skipping for Robot Manipulation
12:32pm - 12:32pm PDTStrix: Re-Thinking NPU Reliability from a System Perspective
12:32pm - 12:33pm PDTCODA: A Computation-Data Decoupled Dataflow Paradigm for DNN Computing on NPUs
12:33pm - 12:33pm PDTVoyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators
12:33pm - 12:34pm PDTMBA: Mega-Buffer Architecture Based on 1T1C IGZO eDRAM for Efficient LLM Inference
12:34pm - 12:34pm PDTFoundry-SRAM-Compatible Compute-Near-Memory Macro for Microscaled Block-FP in 12-nm CMOS
12:34pm - 12:35pm PDTPRS: An Efficient Parallel SAT Framework
12:35pm - 12:35pm PDTMATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs
12:35pm - 12:36pm PDTSTAC: Spatial-Temporal Activation Contextualization for Resilient LLM Inference
12:36pm - 12:36pm PDTBringing Graphs Closer to Memory: Compiler-Driven Data Transfer Reduction in the PIM Accelerator
12:36pm - 12:37pm PDTPipegs: Unlocking 3DGS Pipeline Parallelism via Hierarchical Reuse and Dynamic Partitioning
12:37pm - 12:37pm PDTUniNL: Unifying Fragmented Non-Linear Operators for Efficient Edge LLM Inference
12:37pm - 12:38pm PDTThermal Stability Strategy for a 12nm/28nm Hybrid-Bonding Wafer-on-Wafer 3D-Integrated Eflash In-Memory Computing SoC
12:38pm - 12:38pm PDTDropping Multiple Literals per SAT Call in IC3 Model Checking
12:38pm - 12:39pm PDTHestia: Hyperthread-Level Scheduling for Cloud Microservices with Interference-Aware Attention
12:39pm - 12:39pm PDTDuet: Exploiting High-Order Lossless Sparsity for Bit-Serial Transformer Acceleration via Distribution-Aware Pruning
12:39pm - 12:40pm PDTSpRDA: An Efficient Sparse Accelerator for Robotics Diffusion Model
12:40pm - 12:40pm PDTUNICON: A Unified Reconfigurable Nonlinear Architecture for Efficient Neural Network Inference
12:40pm - 12:41pm PDTPiMM-NoC: Process-in-Memristor-Memory NoC with RL Mapping Framework for Versatile AI Models
12:41pm - 12:41pm PDTLegend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
12:41pm - 12:42pm PDTSafe-IoT : A Memory-Efficient HW/SW Co-Designed ML-DSA Accelerator for IoT Edge Devices
12:42pm - 12:42pm PDTPer Flow Asynchronous Traffic Shaping in Time Sensitive Networking
12:42pm - 12:43pm PDTChiSER: Surrogate-Enhanced Resource-Aware Exploration of Chiplet-Based Deep Neural Network Accelerators
12:43pm - 12:43pm PDTORBIS: Output-Guided Token Reduction with Distribution-Aware Matching for Video Diffusion Acceleration
12:43pm - 12:44pm PDTAHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices
12:44pm - 12:44pm PDTDypamear: Efficient and Scalable Dynamic Graph Pattern Mining on Practical Processing-in-Memory Architecture
12:44pm - 12:45pm PDTMiter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
12:45pm - 12:45pm PDTZ-Paraswap: Co-Optimizing ZNS Parallelism and Swapping for Heterogeneous Graph Neural Network
12:45pm - 12:45pm PDTScheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
12:45pm - 12:46pm PDTAdahuff-GNN: A Convergency-Aware Adaptive Huffman Compression for Communication Reduction in Distributed GNN Training
12:46pm - 12:46pm PDTRelay-GS: Reusing Temporal Sort Information for 4D Gaussian Splatting Acceleration
12:46pm - 12:47pm PDTOvermind NSA: A Unified Neuro-Symbolic Computing Architecture with Approximate Nonlinear Activations and Preemptive Memory Bypass
12:47pm - 12:47pm PDTEnabling Robust On-Device Personalization via Pulse-Based Mapping and Noise Suppression for Non-Ideal CIM Architecture
12:47pm - 12:48pm PDTParallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
12:48pm - 12:48pm PDTPRICE: An Operator Recomputation and Fission Framework for Computation Graphs via Attainable Arithmetic Intensity
12:48pm - 12:49pm PDTCOLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation
12:49pm - 12:49pm PDTROSA: Robust and Energy-Efficient Microring-Based Optical Neural Networks via Optical Shift–and-Add and Layer-Wise Hybrid Mapping
12:49pm - 12:50pm PDTCODA: Cooperative Register Distribution and Arbitration Among Partitioned GPU Sub-Cores
12:50pm - 12:50pm PDTUCME: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead
12:50pm - 12:51pm PDTUBFP-IMC: Ultralarge Bit-Width Digital Floating-Point In-Memory Computing Accelerator for Scientific Computing
12:51pm - 12:51pm PDTParallel Combinational Equivalence Checking Through Factored Form Sharing
12:51pm - 12:52pm PDTExploiting Dependency and Parallelism: Real-Time Scheduling and Analysis for GPU Tasks
12:52pm - 12:52pm PDTBeyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence
12:52pm - 12:53pm PDTPREBA: A Hardware/software Co-Design for Multi-Instance GPU Based AI Inference Servers
12:53pm - 12:53pm PDTTRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
12:53pm - 12:54pm PDTDUET: Disaggregated Hybrid Mamba-Transformer LLMs with Prefill and Decode-Specific Packages
12:54pm - 12:54pm PDTM²CAM: A Multi-Level Memristor-Based Self-Adaptive CAM Architecture for Genome Processing Acceleration
12:54pm - 12:55pm PDTParallelizing Complementary Approximate Reachability
12:55pm - 12:55pm PDTFinding Behavior Bugs in IoT Messaging Protocols with Automated Oracle Generation and Monitoring
12:55pm - 12:56pm PDTSCOUT: Thermal-Aware SRAM Allocation for Real-Time DNN Tasks on Edge TPU
12:56pm - 12:56pm PDTAn Efficient Heterogeneous Co-Design for Fine-Tuning on a Single GPU
12:56pm - 12:57pm PDTMXP: A Posit-Inspired Microscaling Format for Vision-Language Tasks
12:57pm - 12:57pm PDTIs 2D Gaussian Enough? A Sort-Free 3D Gaussian Splatting Inference Architecture with Geometry Guidance
12:57pm - 12:58pm PDTLeveraging Invariants for Scalable Verification of RISC-V Cryptography Extensions
12:58pm - 12:58pm PDTAkirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch
12:58pm - 12:59pm PDTXRel-Graph: Graph Learning-Driven Cross-Layer Reliability Management in Embedded Mixed-Criticality Systems
12:59pm - 12:59pm PDTTowards Fast and Robust Split Federated Learning over Satellite-Based Computing Networks
12:59pm - 1:00pm PDTVten: Tensor-Centric Verification Framework for Domain-Specific Accelerators