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Research Manuscript

TimeTuesday, July 285:30pm - 6:00pm PDT

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Presentations

5:30pm - 5:30pm PDT	Phantom Walk: Reducing the Post-Migration Translation Path via Proactive Translation Dissemination in Multi-GPU Systems Authors Jihun Choi Jaesang Moh Tae Hee Han
5:30pm - 5:30pm PDT	Pegasus: Personalized and Communication-Efficient Mixture-of-Experts System for Distributed Edge LLM Inference Authors Zhixuan Liao Kongyange Zhao Tao Ouyang Liekang Zeng Siqi Luo Xu Chen
5:30pm - 5:31pm PDT	SAAP: An Efficient Spatial-Aware Analytic Partitioning Algorithm of VLSI Netlists for Parallel Routing Authors CHEN LIU Hongxin Kong Lang Feng Wenchao Qian Wuxi Li
5:31pm - 5:31pm PDT	An Adaptive Prediction of Tokens Fluctuation for Decoupled Prefetching to Accelerate Long-Context LLM Decoding Authors Yuanhua Xiao Jihe Wang Zhiyu Sun Linying Wu Danghui Wang
5:31pm - 5:32pm PDT	Mappingevolve: LLM-Driven Code Evolution for Technology Mapping Authors Rongliang Fu Yi Liu Qiang Xu Tsung-Yi Ho
5:32pm - 5:32pm PDT	A Remote Side-Channel Attack on Post-Quantum Key Encapsulation Mechanisms: A Case Study of ML-KEM on Intel x86 Authors Mona Hashemi Qianmei Wu Fan Zhang Shivam Bhasin Trevor E. Carlson
5:32pm - 5:33pm PDT	Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells Authors Hao Wu Keyu Peng Fuxing Huang Qiyuan Chen Zhengzhe Zheng Jianli Chen Ziran Zhu
5:33pm - 5:33pm PDT	Memflow: Characterizing Memory Traffic Contention in Disaggregated Architectures Authors Fujun He Tuo Fang Huaxiang Cai Baolong Cui Zhihe Zhang Yishan Yao Xiabing Li Linyi Du Chuyue Ye Pingyi Huo Bin Gao Yiming Zhang Pengfei Zheng Yunfei Du
5:33pm - 5:33pm PDT	On-Demand Multi-Task Sparsity for Efficient Large-Model Deployment on Edge Devices Authors Lianming Huang Haibo Hu Qiao Li Nan Guan Chun Jason Xue
5:33pm - 5:34pm PDT	G-Matcher: GPU-Accelerated Multi-Level, Multi-Stage Framework for Large-Scale Layout Pattern Matching Authors Nan Wang Hanbin Dong Chengxuan Lv Jiaqi Liu Tao Wu Jingyi Yu Hao Geng
5:34pm - 5:34pm PDT	Sandwich: Joint Configuration Search and Hot-Switching for Efficient CPU LLM Serving Authors JUNTAO ZHAO Jiuru Li Chuan Wu
5:34pm - 5:35pm PDT	Gearls: Generalizable Reinforcement Learning Framework for Logic Optimization via Policy Similarity Metric Authors Yusen Qin Jiaqi Lyu Zhi Li Peng Cao
5:35pm - 5:35pm PDT	Tdsnap: Enabling Secure Function-as-a-Service with Trusted Domain Snapshots Authors Seong-Joong Kim Seungwon Shin Myoungsung You
5:35pm - 5:36pm PDT	Hyperefs: Adaptive Clique Sampling for Scalable Effective Resistance Estimation in Large Hypergraphs Authors Hamed Sajadinia Yihang Yuan Zhuo Feng
5:36pm - 5:36pm PDT	FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration Authors Xingzhen Chen Jinming Zhuang Zhuoping Yang Shixin Ji Sarah Schultz Zheng Dong Weisong Shi Peipei Zhou
5:36pm - 5:36pm PDT	Sharedkd: Gradient-Guided Dynamic Student Discovery Inside a Single 3D Object Detector Authors Hyunjoon Cho Sangho An HYUNSUNG PARK Jangho Kim
5:36pm - 5:37pm PDT	AMS Layout Automation Using Circuit-Level Analog Standard Cells and Self-Biasing Techniques in Digital PnR Tools. Authors Wonsik Oh Luke Theogarajan
5:37pm - 5:37pm PDT	Smartswap: Swap-Based Memory Optimization for LLM Training Under Varying Operator Sequences Authors Zibo Wang Yuhang Zhou Zhibin Wang Shipeng Li Xinjing Huang Chendong Cai Bingxu Mu Yuqing Sun Zhiheng Hu Bin She Shu You Guanghuan Fang Rong Gu Wanchun Dou Guihai Chen Chen Tian
5:37pm - 5:38pm PDT	RL4HDL: Code Diversity Guided FPGA Logic Synthesis Compiler Testing Via Reinforcement Learning Authors Zhihao Xu Hui Zeng Hui Li Qian Ma Furui Zhan Shikai Guo
5:38pm - 5:38pm PDT	Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE Authors Tenghui Hua Huawei Li Jianan Mu Jing Ye Liang Kong Mingzhe Zhang
5:38pm - 5:39pm PDT	Compart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning Authors Yugao Zhu Zhicheng Guo Yuchao Wu Mengming Li Jing Wang Zhiyao Xie
5:39pm - 5:39pm PDT	PD-Swap: Prefill–decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration Authors Yifan Zhang Zhiheng Chen Ye Qiao Zhenyu Tang Sitao Huang
5:39pm - 5:40pm PDT	Pefoo-L: A General Framework for Preconditioned Forward-Only Optimizer Enabling LLM Fine-Tuning on the Edge Authors Yuanfang Wang Yu Li Zhinan Qin
5:40pm - 5:40pm PDT	Unified Rail-Signal Co-Design for Multilayer PCBs: Resource Allocation, IR-Drop, and Routability Authors Wei-Kai Huang Jhih-Jie Lee Yao-Wen Chang Yang Lu Jerry Bai Bin-Chyi Tseng
5:40pm - 5:40pm PDT	Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services Authors Haoyu Chen Xue Li Kun Qian Yu Guan Jin Zhao Xin Wang
5:40pm - 5:41pm PDT	Delay-Constrained Area Optimisation Using SAT-Based Local Improvement Authors Franz-Xaver Reichl Christoph Scholl
5:41pm - 5:41pm PDT	TAMI-MPC: Trusted Acceleration of Minimal-Interaction MPC for Efficient Nonlinear Inference Authors Zhuoran Li Hanieh TotonchiAsl Yifei Cai Ebrahim Nouri Danella Zhao
5:41pm - 5:42pm PDT	Rectilinear Soft Module Floorplanning via Differentiable Polygon Shaping Model and Flow-Based Legalization Authors Fuxing Huang Qiyuan Chen Hao Wu Hao Gu Wenxing Zhu xinning liu Ziran Zhu
5:42pm - 5:42pm PDT	PEACE: Algorithm–hardware Co-Design for PE-Granular Energy-Aware Compressed GEMM Acceleration Authors yueting Li Terry Ye He Xiao Zheng Liu Ngai Wong Weisheng Zhao
5:42pm - 5:43pm PDT	Scoutattention: Efficient KV Cache Offloading via Layer-Ahead CPU Pre-Computation for LLM Inference Authors Qiuyang Zhang Kai Zhou Ding Tang Kai Lu Cheng Li Zhenyu Yang Peng Xu Jiguang Wan
5:43pm - 5:43pm PDT	DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic Graphical Model Authors han zhang Junming Jiao Zhi Li Qixun Tian Peng Cao
5:43pm - 5:43pm PDT	MoE-Balance: Unleashing the Full Potential of CPU-GPU Heterogeneity for Efficient MoE Inference Authors Tiantian Lin Xiaohang Wang Yingtao Jiang Amit Kumar Singh Kui Ren
5:43pm - 5:44pm PDT	Transsyn: Scalable, Area-Oriented Transistor Network Synthesis via Cut-Based Mapper with SAT-Based Refinement Authors Jiun-Cheng Tsai Wei-Min Hsu Hsuan-Ming Huang Jen-Hang Yang Heng-Liang Huang Yen-Ju Su Hung-Pin (Charles) Wen
5:44pm - 5:44pm PDT	Seeing the Unseen: Reverse Engineering Hidden PMU Events by Differential Analysis and Simulation Validation Authors Yihao Yang Pengfei Qiu Xiaojie Zhang Yihao Deng Chunlu Wang Gang Qu Dongsheng Wang
5:44pm - 5:45pm PDT	Moduplace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation Authors Yaohui Han Beichen Li Mingyang Zhao Rongliang Fu Qunsong Ye Tinghuan Chen Bei Yu Tsung-Yi Ho
5:45pm - 5:45pm PDT	SALUT: Efficient Sparse LU Factorization via Asynchronous Task Triggering on HBM FPGAs Authors Xin Xu Zhenhua Wu Dan Niu Zhou Jin Cheng Zhuo
5:45pm - 5:46pm PDT	Ultrasketchllm: Sub-1-Bit LLM Compression via Sketch and Hardware-Friendly Operators Authors Sunan Zou Xueting Sun Ziyun Zhang Guojie Luo
5:46pm - 5:46pm PDT	Mixed-Structure Double-Sided Redistribution Layer Routing for Glass Interposer-Based 5.5D ICs Authors Haoyang Xu Zhen Zhuang Leilei Jin Zheng Yang Chen Wu Lei He Sung Lim Tsung-Yi Ho
5:46pm - 5:46pm PDT	eLLM: Elastic Memory Management Framework for Efficient LLM Serving Authors Yi Xiong Jiale Xu Rui Zhang Cong Guo Zihan Liu Yangjie Zhou Weiming Hu Hao Wu Boyu Li Junping Zhao Minyi Guo Jingwen Leng zongwei zhu Xuehai Zhou
5:46pm - 5:47pm PDT	Shared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis Authors Alessandro Tempia Calvino Anubhaw Xess Anika Prasad Jacob Minz Eleonora Testa Walter Lau Neto Alan Mishchenko Giovanni De Micheli Patrick Vuillod Luca Amaru
5:47pm - 5:47pm PDT	CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator Authors Li Ni Jinwei Pu Xijun Huang Wenhong Ma Zhenyu Wang Lei Liao Wanli Chang You Meng
5:47pm - 5:48pm PDT	GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine Authors Tongkai Wu Beichen Li Yapeng Li Zuxun Duan Yanshi Liang Yihe Wang Baohui Xie Qunsong Ye Tinghuan Chen
5:48pm - 5:48pm PDT	Tsetlinwisard: On-Chip Training of Weightless Neural Networks Using Tsetlin Automata on FPGAs Authors Shengyu Duan Marcos Sartori Rishad Shafik Alex Yakovlev
5:48pm - 5:49pm PDT	Think Before You Prune: Self-Reflective Structured Pruning for Reasoning Language Models Authors Ziyan Wang Enmao Diao Qi Le Pu Wang Guanchu Wang Minwoo Lee Shu-ping Yeh Li Yang
5:49pm - 5:49pm PDT	DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation Authors Shunjie Chang Yuxuan Dong Haodong Lu Youran Wu Jianli Chen Jun Yu Kun Wang
5:49pm - 5:50pm PDT	Zipfloat: An Ultra-Fast and Lossless Floating-Point Compressor for LLM Inference Systems Authors Shihao Wang Xiangyu Zou Wen Xia Hao Hu
5:50pm - 5:50pm PDT	Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs Authors Xianfeng Cao Jiangnan Li Lingli Wang
5:50pm - 5:50pm PDT	PMU-Faker: The Apparently Harmless Performance Monitoring Unit Events Are Actually Harmful Authors Zeru Lan Pengfei Qiu Yaxuan Zhao Ziyan Huang Zhihao Zhang Jiayi Guo Chunlu Wang Dongsheng Wang Gang Qu
5:50pm - 5:51pm PDT	Module-Level Placement Using Force-Based Deformation for Efficient Early Design Estimation Authors Mengen Chen Xu He Tong Shen Yao Wang
5:51pm - 5:51pm PDT	Celestialeye: A Synergistic CPU-FPGA Engine for Accurate Frequency Measurement in High-Speed Data Streams Authors Zhongxian Liang Ying Li Zimo Dong Han Wang Wenjun Li Qun Huang Zhuo Li Weizhe Zhang
5:51pm - 5:52pm PDT	ACE-NAS: A Zero-Cost NAS Framework for Co-Design of Architecture and Encoding in Spiking Neural Networks Authors Mingyu Qin Liangming Fang Wei Liu Jinghai Wang shanlin xiao
5:52pm - 5:52pm PDT	LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment Authors Pengcheng Huang Zepeng Li Zhenkun Lin Guangyong Chen Genggeng Liu Wen-Hao Liu Xing Huang
5:52pm - 5:53pm PDT	Asymcheck: Asymmetric Partitioned Checkpointing for Efficient Large Language Model Training Authors Zhangqiang Ming Yuchong Hu Zhiyuan Luo Patrick P. C. Lee Yuanhao Shu Xinjue Zheng Wenxiang Zhou Dan Feng
5:53pm - 5:53pm PDT	Bident: Optical Logic Synthesis via Optimal Configuration of Binary-Combiner Trees Authors Jun-Wei Liang Iris Hui-Ru Jiang Kai-Hsiang Chiu
5:53pm - 5:53pm PDT	Attackonctf: Defending Hardware Security Competition Benchmarks in the Age of LLMs Authors Mohamadreza Rostami Nikhilesh Singh Stephen Muttathil Lichao Wu Chen Chen Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi
5:53pm - 5:54pm PDT	Ihyperg: Incremental Hypergraph Partitioning on GPU Authors Wan Luan Lee Aditya Das Sarma Che Chang Chih-Chun Chang Tsung-Wei Huang
5:54pm - 5:54pm PDT	Escaping Flatland: A Placement Flow for Enabling 3D FPGAs Authors Cong "Callie" Hao Andrew Kahng Bodhisatta Pramanik Ismael Youssef
5:54pm - 5:55pm PDT	Hardware-Aware Neural Architecture Search for Real-Time BEV-Based 3D Object Detection Authors Jisup Lee Soonhoi Ha Jeongwon Her
5:55pm - 5:55pm PDT	DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm Authors Jinwei Liu Xingyu Cui Liang Xiao Bangqi Fu Evangeline Young
5:55pm - 5:56pm PDT	Throughput-Oriented Speculative Decoding via Intra-Device Parallelism Authors Zehua Li Zijian Zhu Zhanhong Tan Fei Ren Kaisheng Ma
5:56pm - 5:56pm PDT	Duplication-Aware Retiming and Cell Interface Redesign for Superconductor Circuit Minimization Authors Panagiotis Papanikolaou Alex Vanasse Haoran Jin Georgios Tzimpragos Jennifer Volk
5:56pm - 5:56pm PDT	Drop-In Masked Modular Reduction for ML-DSA: Cutting Side-Channel Cost in the Root-of-Trust Authors Merve Karabulut Reza Azarderakhsh
5:56pm - 5:57pm PDT	Impart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning Authors Yugao Zhu Zhicheng Guo Shang Liu Mengming Li Jing Wang Zhiyao Xie
5:57pm - 5:57pm PDT	A Differentiable Approach to Task Graph Partitioning: A Case Study in RTL Simulation Authors Aditya Das Sarma Wan Luan Lee Shui Jiang Boyang Zhang Tsung-Wei Huang
5:57pm - 5:58pm PDT	TACo: Training-Free, Hardware-Aware ViT Architecture Search with a Hypervolume-Based Unified Zero-Cost Score Author Eunji Kwon
5:58pm - 5:58pm PDT	Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing Authors Sojung Park Junghyun Yoon Jooyeon Jeong Heechun Park
5:58pm - 5:59pm PDT	C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems Authors Jiayi Li Di Wu Qingxu Li Hongxiao Zhao Jiaqi Yang Anjunyi Fan Wenbin Zhang Boqiang Wu Shuting Liu Shifeng Fang Jianbo Dong Dimin Niu Bonan Yan
5:59pm - 5:59pm PDT	Unveiling the Security Risks Driven by the Hardware Interrupts Authors Zhihao Zhang Pengfei Qiu Zhouyang Li Yaxuan Zhao Zeru Lan Jiliang Zhang Chunlu Wang Gang Qu Dongsheng Wang
5:59pm - 6:00pm PDT	Hyspecpro: Scalable Hypergraph Partitioning via Spectral Projection Optimization Authors Rongjian Liang Zhuo Feng Haoxing Ren

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