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Session

Event Type
Research Manuscript
TimeMonday, July 275:30pm - 6:00pm PDT
Location
Tracks
AI2-I. AI/ML Algorithms and Models
Design
Tags
DES4. Digital and Analog Circuits; Design
DES1-I. SoC
Heterogeneous
and Reconfigurable Architectures; EDA
EDA4. Power Analysis and Optimization; EDA
EDA2. Design Verification and Validation; Security
SEC4. Embedded and Cross-Layer Security; AI
AI1. AI/ML Frontiers for Hardware Design; AI
Presentations
5:30pm - 5:30pm PDTAdaptive Multiply-Accumulate Unit with Scalable Critical Path for Aggressive Voltage Underscaling DNN Accelerators
5:30pm - 5:30pm PDTSpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
5:30pm - 5:31pm PDTGEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid
5:31pm - 5:31pm PDTLyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
5:31pm - 5:32pm PDTWhen Cloud TEEs Encounter Availability: A Lightweight Framework for Verifiable CPU Availability
5:32pm - 5:32pm PDTChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
5:32pm - 5:32pm PDTExquant: Global Expert Ranking–guided Mixed-Precision Quantization for Efficient MoE Inference
5:32pm - 5:33pm PDTDAP: A Software/hardware Co-Design for Accelerating Multi-Chip-Based Distributed Sparse-Dense Matrix Multiplication
5:33pm - 5:33pm PDTTRIDENT: An End-to-End Streaming Accelerator for TriSpGEMM
5:33pm - 5:34pm PDTBLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
5:34pm - 5:34pm PDTBeyond Fuzzer Islands: CPU Fuzzing via Smart Coordination
5:34pm - 5:35pm PDTThrend: Mitigating Counting Thread-Based Fine-Grained Timing on Arm and Apple CPUs
5:35pm - 5:35pm PDTLLM4SDC: Leveraging Multi-Agent System for Automated SDC Generation and Benchmarking
5:35pm - 5:35pm PDTSpecmoe: A Fast and Efficient Mixture-of-Experts Inference via Self-Assisted Speculative Decoding
5:35pm - 5:36pm PDTFactored Floating-Point MAC: Eliminating Redundant Normalization for Energy-Efficient Systolic Arrays
5:36pm - 5:36pm PDTProcyon: Promoting Fine-Grained Multi-Tenancy to Optimize Sparse Streaming Accelerators
5:36pm - 5:37pm PDTLEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power
5:37pm - 5:37pm PDTARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing
5:37pm - 5:38pm PDTSpike-PTSD: A Bio-Plausible Adversarial Example Attack on Spiking Neural Networks via PTSD-Inspired Spike Scaling
5:38pm - 5:38pm PDTSvacoder: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
5:38pm - 5:38pm PDTKL-MoE: A Hierarchical MoE Pruning Framework Exploiting KL Divergence
5:38pm - 5:39pm PDTPMTPA: An Ising Model-Based Parallel-Momentum Tempering Processing Architecture for Combinatorial Optimization
5:39pm - 5:39pm PDTTRINE: A Token-Aware, Runtime-Adaptive FPGA Inference Engine for Multimodal AI
5:39pm - 5:40pm PDTPIANO: Physics-Informed Admittance Neural Operator for Fast Power Integrity Analysis
5:40pm - 5:40pm PDTUvmarvel: an Automated LLM-Aided UVM Machine for Subsystem-Level RTL Verification
5:40pm - 5:41pm PDTCARAMEL: Boosting Device Utilization in Control Flow Auditing
5:41pm - 5:41pm PDTDebug Like a Human: Scaling LLM-Based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing
5:41pm - 5:41pm PDTPRISM: Priority Aware Shared Scale Microscaling Format for 4-Bit Quantization
5:41pm - 5:42pm PDTRFIPSA: A Reconfigurable FIP-Based Systolic Array for Various Matrix-Intensive Workloads
5:42pm - 5:42pm PDTPHAROS: Pipelined Heterogeneous Accelerators for Real-Time Safety-Critical Systems With Deadline Compliance
5:42pm - 5:43pm PDTEarly Design Stage Thermal Prediction and Optimization: Machine-Learning Driven Approach
5:43pm - 5:43pm PDTStitch: Assertion-Guided Patching of On-Chip Protocol Implementations Using LLMs
5:43pm - 5:44pm PDTSemi-Virtual Addressing to Enhance Memory Safety on Microcontrollers
5:44pm - 5:44pm PDTEARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation
5:44pm - 5:44pm PDTLiveVLM: Efficient Online Video Understanding via Streaming-Oriented KV Cache and Retrieval
5:44pm - 5:45pm PDTARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy
5:45pm - 5:45pm PDTCan Asymmetric Tile Buffering Be Beneficial?
5:45pm - 5:46pm PDTEastPCG: An Efficient and Self-Tuning Graph Sparsification Based PCG Solver for Circuit Simulation
5:46pm - 5:46pm PDTTOB-Sched: Topological Order Balancing-Driven Static Scheduling for Processor-Based Emulation
5:46pm - 5:47pm PDTGraph-Based Attack-Chain Traceback Across Multiple In-Vehicle Network Domains
5:47pm - 5:47pm PDTStepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
5:47pm - 5:47pm PDTMarlin: I/O-Efficient Prefix KV Cache Retrieval for Long-Prefix LLM Serving
5:47pm - 5:48pm PDTCLUE-ECC: Low-Cost LPDDR6 Reliability Enhancement by Integrating System ECC with On-Die ECC
5:48pm - 5:48pm PDTCachence: Fine-Grained Cache Partitioning in Both Time and Space
5:48pm - 5:49pm PDTCOOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging
5:49pm - 5:49pm PDTA Boolean Processor-Based Hardware Emulation System with Reconfigurable Interconnects
5:49pm - 5:50pm PDTInstruction-Level Side-Channel Disassembly on Modern Complex CPUs via Voltage Waveform Analysis
5:50pm - 5:50pm PDTReflectbench: An Agentic Framework for Generating System-Level Design Testbench via Consensus and Reflection
5:50pm - 5:50pm PDTTopGQ: Fast GNN Post-Training Quantization Leveraging Topology Information
5:50pm - 5:51pm PDTTrain Once, Calibrate Always: Machine-Learning-Assisted Blind Calibration for Analog-to-Digital Converters
5:51pm - 5:51pm PDTToki: Profiling HBM Performance on FPGA Systems with RISC-V Soft Cores and PCIe Host DMA Traffic
5:51pm - 5:52pm PDTCompilation Tells Energy: Rethinking Power Modeling for DNN Accelerator Agile Design
5:52pm - 5:52pm PDTDart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution
5:52pm - 5:53pm PDTZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
5:53pm - 5:53pm PDTNotsotiny: A Large, Living Benchmark for RTL Code Generation
5:53pm - 5:53pm PDTSemcom: Semantic-Enhanced On-Board Satellite Image Compression at Ultra-Low Bitrates
5:53pm - 5:54pm PDTDeltasight: Architecting Efficient Video AIoT Systems via Cross-Stage Consistent Redundancy Elimination
5:54pm - 5:54pm PDTCredix: A Credit-Driven Distributed Buffer Management for Large-Scale Switching Chips
5:54pm - 5:55pm PDTLegotherm: Modular and Reusable Thermal Model for Chiplet-Based Heterogeneous Integration
5:55pm - 5:55pm PDTActivity-Aware Partitioning for Effective Multi-Threaded Event-Driven RTL Simulation
5:55pm - 5:56pm PDTEnabling AI ASICs for Zero Knowledge Proof
5:56pm - 5:56pm PDTDrcagent: A Design Rule Aware LLM Agent for DRC Auto-Fix with Adversarial Reinforcement Learning
5:56pm - 5:56pm PDTCrystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
5:56pm - 5:57pm PDTPEL: A 4K@120FPS Palette-Based Enhancement Layer Validated with JPEG XS Achieving 18.13% Bdrate Reduction
5:57pm - 5:57pm PDTOpenSUN: An Open Platform for Exploring Scale-Up Network Systems
5:57pm - 5:58pm PDTFLASH3D: A Fast Layered Analytical Solver for High-Accuracy Steady-State Thermal Simulation of 3D ICs
5:58pm - 5:58pm PDTAccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
5:58pm - 5:59pm PDTHades: Harnessing Architecture Design Automation for Application-Specific FHE Accelerators
5:59pm - 5:59pm PDTChipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
5:59pm - 5:59pm PDTSPADE: An Input-Adaptive Sparse Attention Engine for Fast Video Diffusion Models Inference