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Session

Event Type
Research Manuscript
TimeMonday, July 273:00pm - 3:30pm PDT
Location
Topics
Chiplet
Tracks
SYS4. Embedded System Design Tools and Methodologies
EDA
Tags
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package; Design
DES3. Emerging Models of Computation; AI
AI3-I. AI/ML Application and Infrastructure; EDA
EDA6. Analog CAD
Simulation
Verification and Test; Design
DES2B-I. In-memory and Near-memory Computing Architectures
Applications and Systems; AI
AI2-I. AI/ML Algorithms and Models; Systems
Presentations
3:00pm - 3:00pm PDTFlexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
3:00pm - 3:01pm PDTBrain-Like Hyper-Dimensional Graph Learning System with Hardware-Efficient Adaptive Sparsity
3:01pm - 3:01pm PDTGreenllm: SLO-Aware Dynamic Frequency Scaling for Energy-Efficient LLM Serving
3:01pm - 3:02pm PDTIGNITE: An Inquisitive and Graph-Aware Neural Circuit Simulator with Two-Stage Enhanced In-Context Learning
3:02pm - 3:03pm PDTCQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval
3:03pm - 3:03pm PDTPCBgen3D: A Self-Correcting Graph-Based MLLM Framework for Automated PCB 3D Models Generation
3:03pm - 3:04pm PDTHierarchical Pareto-Prompted Optimization for Probabilistic DAG Scheduling on Real-Time Systems
3:04pm - 3:04pm PDTWhitespace-Free Rectilinear 3D Floorplanning with Pressure-Driven Orthogonal Laguerre-Voronoi Tessellation (POLT)
3:04pm - 3:05pm PDTADAPT: An Algorithm-Hardware Co-Design for Spiking Transformer with Training-Free Adaptive Token Pruning and Hierarchical Sparsity
3:05pm - 3:06pm PDTTernainfer: Pushing the Compression Boundary of Ternary LLMs Towards 1.58-Bit GPU Inference
3:06pm - 3:06pm PDTUGLMS-uSMILE: Live Measurement Sequencing for Segmented Linearity Identification in ADCs
3:06pm - 3:07pm PDTCANNON: A CXL-Based Near-Memory Processing Architecture for Approximate Nearest Neighbor Search on Real Hardware
3:07pm - 3:07pm PDTCupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution
3:07pm - 3:08pm PDTMALIWAN: Performance and Energy Efficiency Co-Optimization of GEMM on Versal ACAP Architectures
3:08pm - 3:09pm PDTSeeing Through Silicon: Multimodal Thermal Reconstruction via Physics-Informed Diffusion
3:09pm - 3:09pm PDTHDDB: Efficient In-Storage SQL Database Search Using Hyperdimensional Computing on Ferroelectric NAND Flash
3:09pm - 3:10pm PDTInferweave: Efficient LLM Inference on the MT-3000 Processor
3:10pm - 3:11pm PDTGTX: Graph Transformer for Parasitic Extraction on Analog Circuits
3:11pm - 3:11pm PDTRAGNMP: Leveraging Elimination Tree to Accelerate RAG with Near-Memory Processing
3:11pm - 3:12pm PDTParetopilot: Global Optimization Reasoning on HLS Design Space Exploration with LLMs
3:12pm - 3:12pm PDTPrelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging
3:12pm - 3:13pm PDTBSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
3:13pm - 3:14pm PDTBiBNN: 88.6% Computation Reduction in Bayesian Neural Networks via Post-Training Bernoullization
3:14pm - 3:14pm PDTSparsity- and Tolerance-Aware Temporally Redundant Neural Networks
3:14pm - 3:15pm PDTUNCHARTED: A Universal Circuit Design Hierarchical Model Based on Auto-Regressive Spatio-Temporal Graph Neural Network with Exogenous Driving Inputs
3:15pm - 3:15pm PDTLOHA: A Latency-Optimized CPU-Storage Hybrid Architecture for Billion-Scale Graph-Based Vector Similarity Search
3:15pm - 3:16pm PDTAutonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
3:16pm - 3:17pm PDTEXRA: Efficient Execution of Data-Dominated Applications via ISA Extensions for Expandable Register Files
3:17pm - 3:17pm PDTIdealsim: Efficient Ideal Scenario Modeling for Processor Upper-Bound Performance Analysis
3:17pm - 3:18pm PDTSkiST: Memory-Efficient Fine-Tuning of Spiking Neural Networks via Spatio-Temporal Adaptation
3:18pm - 3:18pm PDTSmoe: Elastic MoE-Based Inference with Serverless Computing via Fine-Grained Expert Scaling
3:18pm - 3:19pm PDTFloquet-Based Subspace Projection Method for Time-Domain PPV Computation
3:19pm - 3:20pm PDTPS-CAM: An Efficient Content-Addressable Memory Based Accelerator for Point Search in Point Clouds
3:20pm - 3:20pm PDTRTL-Benchmt: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
3:20pm - 3:21pm PDTSTCG: Sparse Tensor Code Generation via Adaptive Tile Scheduling on GPUs with Tensor Cores
3:21pm - 3:22pm PDTDataflowgen: An MLIR-Based Compiler for Efficient Dataflow Accelerator Generation
3:22pm - 3:22pm PDTAdaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks
3:22pm - 3:23pm PDTFaster-MoA: Low-Latency Tree-Structured MoA Serving with Early Exit and Agent-Aware Prefill-Decode Overlap
3:23pm - 3:23pm PDTA Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation
3:23pm - 3:24pm PDTPrism: Reducing Arithmetic for High-Recall Approximate Nearest Neighbor Search on Processing-in-Memory
3:24pm - 3:25pm PDTThe Phantom of PCIe: Constraining Generative Artificial Intelligences for Practical Peripherals Trace Synthesizing
3:25pm - 3:25pm PDTStateful Embedded Fuzzing Using Peripheral-Accurate Systemc Virtual Prototypes
3:25pm - 3:26pm PDTChiplanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems
3:26pm - 3:26pm PDTSDM: A Variation-Tolerant Soft Decision Machine with In-Memory Sigmoid Computation
3:26pm - 3:27pm PDTGalaxydit: Efficient Video Generation with Guidance Alignment and Adaptive Proxy in Diffusion Transformers
3:27pm - 3:28pm PDTFUSE-TCAD: A Diffusion-Based Multi-Field Surrogate for High-Fidelity TCAD Device Simulation
3:28pm - 3:28pm PDTPIMGRAG: A Heterogeneous PIM Architecture for Graph-Based Retrieval-Augmented Generation
3:28pm - 3:29pm PDTSchemacoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
3:29pm - 3:29pm PDTG-Power: Architecture-Level GPU Power Modeling with Aggregated Knowledge Foundations from Known GPUs