Session

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Research Manuscript

TimeMonday, July 2712:30pm - 1:00pm PDT

LocationMtg Room 102

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Presentations

12:30pm - 12:30pm PDT	Fusedot: A Multiplication-Fused Dot Product Accelerator for Efficient LLM Inference Authors Wenju Zhao Jianhui Yue Pengcheng Yao Yujia Cui Qinggang Wang Yufei Sun Jiaqi Zhai Hai Jin Xiaofei Liao
12:30pm - 12:30pm PDT	CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators Authors Shi Chao teng wang Zhu Qinggang Qianyu Cheng Jing Wu Wenqi Lou Lei Gong Zhou Xuehai
12:30pm - 12:31pm PDT	Securerouter: Encrypted Routing for Efficient Secure Inference Authors Yukuan Zhang Mengxin Zheng Qian Lou
12:31pm - 12:31pm PDT	Shortcircuit: Alphazero-Driven Generative Circuit Design Authors Dimitrios Tsaras Antoine Grosnit Lei Chen Zhiyao Xie Haitham Bou Ammar Mingxuan Yuan
12:31pm - 12:32pm PDT	S2CIM: A Secure-Computation and Secure-Storage Compute-in-Memory Architecture with Circuit-Algorithm Co-Design for Efficient and Trustworthy Edge Inference Authors Hanyong Shao Zhiyuan Ning Wenshuai Yao Runteng Zhu Wenpu Luo Xiaolei Wang Xunzhao Yin Meng Li Kechao Tang Ru Huang
12:32pm - 12:32pm PDT	Path-Based Timing Analysis Acceleration via Segment-Level Timing Arc Reuse Authors Yuyang Ye Xiangfei Hu Leyun Tian Chang Meng Qing He Longxing Shi
12:32pm - 12:33pm PDT	METRIC: An MDS-Analog ECC with Minimum Two-Column Redundancy for Fault-Tolerant, Layer-Aware IMC Architecture Authors Jiajun Gao Chengping He Haozheng Wan Zhanzhi Liu Mingrui Jiang Can Li
12:33pm - 12:33pm PDT	TDH-GNN: An Efficient Topology-Driven Accelerator for Dynamic Heterogeneous GNN Authors Hui Yu Wei Zhang Ligang He Jin Zhao Yu Zhang Zixiao Wang
12:33pm - 12:34pm PDT	Integrating LLMs into a Two-Tier Traditional Methodology for Automated Verilog Code Generation Authors Alex Lu Bilal El Jamal Alex Doboli
12:34pm - 12:34pm PDT	TT-SEAL: TTD-Aware Selective Encryption for Adversarially-Robust and Low-Latency Edge AI Authors Kyeongpil Min Sangmin Jeon Jae-Jin Lee Woojoo Lee
12:34pm - 12:35pm PDT	Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits Authors Jingyi Zhou Zhengyuan Shi Jiaying Zhu Ziyang Zheng Qiang Xu
12:35pm - 12:35pm PDT	HYPER-CIM: Hierarchical Predictive Exploration and Realizable Design Flow for High-Efficient Digital CIM Authors An Guo Yuhui Shi Yuhuai Zhang Tianhui Jiao Xiaoxue Zhong Defa Wu Arindam Basu Xin Si Jun Yang
12:35pm - 12:36pm PDT	Disentangled Differentiable Timing-Power Co-Optimization with Quad-Gradient Gate Sizing Authors Zixuan Pan Zizheng Guo Yufan Du Runsheng Wang Yibo Lin
12:36pm - 12:36pm PDT	STEM-CAM: Segmented Thermometer-Encoded Multibit CAM with Wildcard Matching for Efficient Arbitrary-Order Minkowski Distance Metrics Authors Zeyu Zhang Weikai Xu Changyue Hao Qianqian Huang Ru Huang
12:36pm - 12:37pm PDT	MASQ: Accelerating Masked Diffusion via Stage-Wise Multi-Precision Quantization Authors Seeyeon Kim Jaehun Lee Sungyeob Yoo Joo-Young Kim
12:37pm - 12:37pm PDT	LLM-Based Automatic Architecture Optimization for AI Model HLS Implementation on FPGA Authors Zhe Xiao Mingyu Liu Xu He Haoying Wu Jie Zhao Yao Wang Libo Huang
12:37pm - 12:38pm PDT	FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity Authors Guiming Shi Yuchen Wei Zhanhong Tan Muyang Li Dapeng Cao Jingwei Cai Shuwen Deng Kaisheng Ma
12:38pm - 12:38pm PDT	Capbench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction Authors Hector Rodriguez Jiechen Huang Wenjian Yu
12:38pm - 12:39pm PDT	Noisexplore: A Device-Aware Hierarchical Noise Modeling and DTCO Framework for Analog In-Pixel Computing Architectures Authors Jinghan Xu Zheng Zhou Yi Xiao Nan Tang Shuhan Wang Ligong Zhang Xiaoyan Liu
12:39pm - 12:39pm PDT	RTL-3D: Timing-Aware Tier Partitioning for 3D ICs Using Pre-Synthesis Timing Analysis Authors Haoyang Xu Zheng Yang Zhen Zhuang Leilei Jin Bei Yu Sung Lim Tsung-Yi Ho
12:39pm - 12:40pm PDT	Jsplace: A Shape-Controllable and Length-Matching Placement for Rapid Single-Flux-Quantum Circuits Authors Rongliang Fu Minglei Zhou Huilong Jiang Da Wang Fei Wang Huawei Cao Junying Huang
12:40pm - 12:40pm PDT	TAG: A Topology-Aware Architecture for Configurable and Memory-Efficient GNN Acceleration Authors Ruoheng Yao Yichen Ouyang Wenneng Jiang Tianji Wang Yangyi Zhang Zhiyue Gao Zhiyong Lai Lei Chen Fengwei An
12:40pm - 12:40pm PDT	Insights from Verification: Training a Verilog Generation LLM Using Reinforcement Learning with Testbench Feedback Authors Ning Wang Bingkun Yao Jie Zhou Yuchen Hu Xi Wang Zhe Jiang Nan Guan
12:40pm - 12:41pm PDT	Runtime-ADAR: Runtime Anomaly Detection and Attack Recovery in Encrypted DNNs Authors Jie Xiao jiajun guo yuhao huang hao ying zhanhui shi Jianping Mei Fan Zhang
12:41pm - 12:41pm PDT	TOPCELL: Topology Optimization of Standard Cell via LLMs Authors Zhan Song Yu-Tung Liu Chen Chen Guoheng Sun Jiaqi Yin Chia-tung Ho Ang Li Haoxing Ren Cunxi Yu
12:41pm - 12:42pm PDT	DIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing Authors Zhaoyang Zhang Tianhao Zhao Defa Wu yingxuan zhou Xiaodong Li Yan Yan Yang Jun Xin Si
12:42pm - 12:42pm PDT	Powerpath: Internal-Probe-Free Search Interval Reduction for Efficient Statistical Sequential Constraint Characterization Authors Junzhuo Zhou Li Huang Wei Xing Ting-Jung Lin Lei He
12:42pm - 12:43pm PDT	Gwrite: Offloading Replication in Disaggregated Memory Systems Authors Jianglang Zhu Mingxing ZHANG Yingdi Shan Yongwei Wu
12:43pm - 12:43pm PDT	Florella: Accelerating Graph Neural Networks by Sliding Reduction Convention and Flexible Architecture Authors Xiaobo Lu Jianbin Fang Lin Peng Yang Liu Yixiang Di Chun Huang
12:43pm - 12:44pm PDT	Unlocking Automated Datapath Gating via Machine Learning Power Prediction Authors Felipe Marranghello Giulia Meuli Barkha Gupta Alessandro Tempia Calvino Eleonora Testa Walter Lau Neto Patrick Vuillod Luca Amaru
12:44pm - 12:44pm PDT	Holocode: Hybrid Optical-Electronic Edge Encoding for Privacy-Preserving Cloud Training Authors Ruofan Xing Arman Akbari Weikai Lin Adith Boloor Alexander McNeil Michael Moebius Yongmin Liu Yuhao Zhu Xuan Zhang
12:44pm - 12:45pm PDT	Neural Domain Decomposition for Scalable Multi-Physics: Chip-Scale Thermal-Stress Analysis Authors Min-Chul Park Ji-Hye Lee Sungyeop Lee Giyong Hong Seokki Lee In Huh Hong-hyun Park Hyunjae Jang Changwook Jeong Young-Gu Kim Dae Sin Kim
12:45pm - 12:45pm PDT	NASiC: 3D NAND-Based CAM-Selected Multibit CIM Architecture for Efficient On-Device Mixture-of-Experts LLM Inference Authors Weikai Xu Meng Li Shuzhang Zhong Tianyang Luo Dongxue Zhao LING LIANG Zongwei Wang Qianqian Huang Yimao Cai Ru Huang
12:45pm - 12:46pm PDT	RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-Based Paradigm Authors Ziyan Guo Wenji Fang Wenkai LI Yuchao Wu Shang Liu Zhiyao Xie
12:46pm - 12:46pm PDT	Rememtier: Rethinking Memory Tiering for CXL-Based SSD via Large Granularity Memory Access Authors Yi-Sia Gao Wen Sheng Lim Tei-Wei Kuo Yuan-Hao Chang
12:46pm - 12:47pm PDT	AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability Authors Yubin Qin Yang Wang Zhiwei Lin Yushu Zhao Xiaolong Yang Zhiheng Yue Huiming Han Yang Hu Shouyi YIN
12:47pm - 12:47pm PDT	Soberdse: Sample-Efficient Design Space Exploration via Learning-Based Algorithm Selection Authors Lei Xu Shanshan Wang Chenglong Xiao
12:47pm - 12:48pm PDT	PLONK-Hammer:breaking Input Privacy of PLONK Proving Systems via Rowhammer Authors Zhiwen Zhang Junkai Liang Xin Zhang Qingni Shen Cong Li Yuejian Fang
12:48pm - 12:48pm PDT	Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion Authors Ning Wang Zichong Deng Bingkun Yao Jie Zhou Yuchen Hu Xi Wang Zhe Jiang Nan Guan
12:48pm - 12:49pm PDT	KCD-CAM: A K-Nearest-Neighbor Accelerator Based on Charge-Domain Content-Addressable-Memory for Point Cloud Processing Authors Tong Hu Jiancong Li Yingjie Yu Zhiwei Zhou Jia Chen Yi Li Xiangshui Miao
12:49pm - 12:49pm PDT	iPCL-M: Pre-Training of Chip Layout for Metrics Evaluation and Optimization Authors Xinhua Lai He Liu Weiguo Li Yihang Qiu Miao Liu Simin Tao Xingquan Li Jungang Xu
12:49pm - 12:50pm PDT	TierANNS: Scalable Graph-Based ANNS with CXL-Enabled Tiered Data Placement Authors Ying Zhang Chao Li Xiaowei Chen Tianyu Wang Chenlin Ma Zhaoyan Shen Jiaxian Chen Kecheng Huang
12:50pm - 12:50pm PDT	DSPE: An Energy-Efficient Edge Processor for Deepseek Inference with Merkletree-Based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing Authors Yuhan Zhang Zhou Wang Zhou Shu Jiuren Zhou Yanqing Xu Xiaonan Tang shushan qiao Tianchun Ye Yang Liu Anil Bharath Emm Drakakis
12:50pm - 12:50pm PDT	Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks Authors Haoran Xue teng wang Qianyu Cheng Zhendong Zheng Wenqi Lou Lei Gong Xi Li Xuehai Zhou
12:50pm - 12:51pm PDT	MACH: Memory-Aware Configuration Generation for Homomorphically Encrypted Neural Networks Authors Honghui You Linjie Xiao Yuhang Fan Wenzhe Wang Tianxiang Sui Zhuoran Ji Lei Ju
12:51pm - 12:51pm PDT	Xsearch: Exploring Microarchitecture Design Space Through Bayesian Optimization and Cross Evaluation on Multi-Fidelity Simulators Authors Honghua Zhu Chunjie Luo Xinke Zhao Jianfeng Zhan
12:51pm - 12:52pm PDT	Probabilistic Memory Design for Efficient Trustworthy Edge Intelligence Authors Likai Pei Jiahao Zheng Xueji Zhao Emilie Ye Jianbo Liu Hanqing Tao Ming-Yen Lee Ruiyang Qin Yiyu Shi Shimeng Yu X. Sharon Hu Ningyuan Cao
12:52pm - 12:52pm PDT	Warp-STAR: High-Performance, Differentiable GPU-Accelerated Static Timing Analysis Through Warp-Oriented Parallel Orchestration Authors En-Ming Huang Shih-Hao Hung
12:52pm - 12:53pm PDT	Design Technology Co-Optimization for Network on Chip in High Performance CPUs at 3nm Node Using Monolithic 3D and Backside Interconnect Technologies Authors Tianchi Liu Hu Zhou Zexu Leng Zhiyong Zhang Lianmao Peng Rongmei Chen
12:53pm - 12:53pm PDT	FSGen: Agile Fused and Sparse Accelerator Generator with Accurate Power Model for LLM Applications Authors Jay Zhe-An Mok Qijun Zhang Zhiyao Xie
12:53pm - 12:54pm PDT	B-Flex: Exploration of Broader Flip-Flop Design Space Based on FSM Exhaustive Search Authors Hyunsung Jeong Kyounghun Kang Wanyeong Jung Jongeun Lee
12:54pm - 12:54pm PDT	Icarus's Wings: Disabling MoE Offloading Acceleration via a Universal Hidden Prefix Attack Authors Qichao Ma Zecheng Hao Zihao Zheng LING LIANG Xing Hu Zhaofei Yu Tiejun Huang
12:54pm - 12:55pm PDT	Weak-Form Physics-Informed Neural Network for Self-Supervised Learning in Semiconductor Device Simulation Authors Hanshi Yang Tianrun Yang Quan Zhao Yadong Wei Ying Ma
12:55pm - 12:55pm PDT	REPAIR: Reliability Enhancement of NVM FPGAs Through Lifetime-Aware Differential Partial Reconfiguration Authors Miran Tobar Hassan Nassar Joerg Henkel
12:55pm - 12:56pm PDT	PG-GNN: Physics-Guided Graph Neural Network for Cell Timing Library Characterization Authors Jason Cheng Jeffery Chen Aaron Liang Hung-Pin (Charles) Wen
12:56pm - 12:56pm PDT	Lightningfno: Ultra-Fast Modeling and Inverse Design for Photonic Matrix-Vector Multiplication Computing Units Authors Mingyuan Li Qisheng Yang Yichi Zhang xiaoxuan Wu Guochang Lin Tian-ling Ren
12:56pm - 12:57pm PDT	DM-MARK: Software and Hardware Co-Design of Watermarking Accelerator for Authorized Diffusion Model Usage on Edge Devices Authors Shiyu Guo Jie Gu
12:57pm - 12:57pm PDT	Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping Authors Kuo-Wei Ho Jie-Hong Roland Jiang Alan Mishchenko Sean Weaver Yu-Wei Fan
12:57pm - 12:58pm PDT	Multi‑GPU Tensor‑Level Fusion and Adaptive Memory Management for Private Inference Authors Homer Gamil Michail Maniatakos
12:58pm - 12:58pm PDT	From Fluid Dynamics to Chip Design: PDE Foundation Model Address Data Bottleneck in 3D-ICs Thermal Simulation Authors Zhen Huang Xin HaiYang Dongming Jiang yangbo wei Hong Wang yang wenkai yu zhang Wei Xing Ting-Jung Lin lei he
12:58pm - 12:59pm PDT	DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access Authors Yuxuan Qin Chuxiong Lin Shuo Yan Guoming Rao Weiguang Sheng Weifeng He
12:59pm - 12:59pm PDT	Crosstalk Timing Prediction via Graph Prompt Learning in Aggressor-Victim RC Networks Authors Yuren Zhou Fan Yang Zihao Zeng Yifan Wang Yuyang Ye Qing He
12:59pm - 1:00pm PDT	Hyperwafer: Communication-Aware Sparse Matrix Multiplication on Wafer-Scale Chips Authors Zhongcheng Du Yu Huang Yi Zhang Qihang Qiu Chencheng Ye Huanyu Wu Qie Wang Xueqi Li Long Zheng Xiaofei Liao Hai Jin

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