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Work in Progress
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Work in Progress (WIP) Poster Session
Event Type
Work in Progress
TimeMonday, July 275:00pm - 7:00pm PDT
LocationExhibit Hall
Presentations
5:05pm - 5:06pm PDTDefending Side-Channel Attacks in Client-Side Deduplication with Hardware/software Codesign
5:06pm - 5:07pm PDTLate Breaking Results: Guiding Compiler Optimizations for Neutral Atom Quantum Computers Through Visualizations
5:07pm - 5:08pm PDTAn Autonomous Design Agent of Parallel Feedforward Equalizer for Advanced Wireline Receivers
5:11pm - 5:12pm PDTLate Breaking Results: Influential Data Selection for LLM-Based RTL Generation
5:13pm - 5:14pm PDTAgentic AI for Chip Design and Verification: Results and Limitations from CVDP
5:14pm - 5:15pm PDTLinearly Scalable Algorithms for DFT Static Verification, Coverage Analysis, and Debug at RTL
5:15pm - 5:15pm PDTML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π Networks
5:18pm - 5:18pm PDTLate Breaking Results: FeMFET Multi-Level Cell Capacity Limits for SNN-Based Compute-in-Memory Inference
5:21pm - 5:21pm PDTAccelerated Dynamic Voltage Drop Prediction Using a Lightweight Machine Learning Model
5:21pm - 5:22pm PDTLate Breaking Results: Encoding-in-Memory via Generating True Random One-Time Password
5:23pm - 5:24pm PDTWill AI Mess my RTL? A Snapshot-Based Approach to Verifying AI-Written RTL
5:26pm - 5:27pm PDTLate Breaking Results: Energy-Aware Scheduling of Open-Vocabulary Detection on Low-Power Mobile Robots
5:27pm - 5:27pm PDTLate Breaking Results: A Neuromorphic Accelerator for Efficient Multi-Head Attention Processing in Spiking Vision Transformers
5:27pm - 5:28pm PDTA Novel Way to Handle Non-Convergence of Properties in Formal Verification of Digital Systems
5:31pm - 5:32pm PDTLate Breaking Results: Micro-Dense Tensor-Core-Aligned N:M Sparse Kernel for Efficient Inference Acceleration
5:33pm - 5:33pm PDTR5-Link : Enhancing RISC-V Multi-Core Efficiency with Hardware Message Passing Channels in a 2D Mesh Network
5:34pm - 5:35pm PDTLate Breaking Results: Analog Circuit Sizing Optimization Using Procrustes-Guided Machine Learning Heuristics
5:35pm - 5:36pm PDTHierarchical Learning–based Digital Circuit Design Tuning Framework for Power-Delay Optimization
5:37pm - 5:38pm PDTLate Breaking Results: Fast Energy-Aware Neural Network Modeling for Efficient FPGA-Based Inference
5:39pm - 5:40pm PDTLate Breaking Results: Die Area and Temperature Co-Optimization for Thermal Throttling Mitigation in Mobile Application Processors
5:42pm - 5:43pm PDTLate Breaking Results: A Scalable and Efficient Multi-Layer 3D-Printed Microfluidic Design Synthesis
5:49pm - 5:50pm PDTPASCAL: ML-Based Predictive Skew Compensation for Asymmetric Clock Tree Aging
5:52pm - 5:53pm PDTSplit–and–sync Bayesian Learning–driven SRAM Compiler: Automatic Design Tuning with Optimal Banking
5:54pm - 5:55pm PDTLate Breaking Results: Quantum-Aware Model Compression Techniques for Scalable Quantum Machine Learning
6:05pm - 6:06pm PDTLate Breaking Results: High-Fidelity Simulation and Real-Time Forecasting of Fluid-Solute-Coupled Microfluidics
6:09pm - 6:10pm PDTLate Breaking Results: Tiny Brain, Big World: Autonomous MCU-Friendly Navigation for Mapless Dynamic Environments
6:10pm - 6:10pm PDTLate Breaking Results: A Resource-Constrained Co-Design Framework for Enabling Heterogeneous Quantum Chiplet Ensembles via Circuit Cutting
6:10pm - 6:11pm PDTLate-Breaking Results: QML for Quantum Sensing Under Measurement-Induced Information Loss
6:13pm - 6:13pm PDTLate Breaking Results: Synthesizable 8-Bit Digital Memristor Emulator with Programmable State Retention for Accelerated Edge Computing
6:14pm - 6:15pm PDTNPU-Based Energy-Efficient LLM Inference for Semiconductor Equipment Control Code Generation
6:15pm - 6:16pm PDTLate Breaking Results: Hardware-Efficient PQ Search Framework for Sparse Coding-Based KV Cache Compression
6:20pm - 6:21pm PDTLate Breaking Results: Analog Circuit Sizing via LLM-Guided Heuristic Search with Metric Difficulty Awareness
6:26pm - 6:27pm PDTLate Breaking Results: Hightide: an Open-Source Hardware Benchmark Suite
6:27pm - 6:28pm PDTLate Breaking Results: Q-STEP: A Cross-Layer Design and Validation Framework for Advancing Quantum Sensing
6:29pm - 6:30pm PDTLockroute: A Spatial Locking Framework for Parallel Global Routing
6:30pm - 6:31pm PDTAccelerating Functional Fault Grading for Flash and DRAM Designs
6:31pm - 6:32pm PDTChiplite: High-Level Performance Modeling Methodology for Automotive Chiplet Systems
6:32pm - 6:32pm PDTEdgeQ‑GEMM: INT4/INT8 Mixed‑Precision GEMM Accelerator with On‑the‑Fly Quantization for Accuracy–Energy Tunability in Edge AI Processors
6:32pm - 6:33pm PDTSwift-Healer: Firmware-Reconfigurable Self-Healing for Remote Glitch-Injection on Autonomous Driving Systems
6:33pm - 6:34pm PDTThe Last Line of Defense in DNN Inference: Argmax Security Under Combined Power Side-Channel and Fault Injection Attack
6:34pm - 6:35pm PDTCompact ML-Based Glitch Propagation Modeling of Standard Cells
6:35pm - 6:35pm PDTRELMAS-HRT: Online Inference Scheduling in Mixed-Criticality Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning
6:36pm - 6:37pm PDTNucleus: A Reconfigurable Long-Context LLM Accelerator Using Adaptive Outlier-Aware KV Cache Quantization
6:37pm - 6:38pm PDTPHAP: A Pre-Analyzed Head-Wise Attention Pattern for Efficient Sparse Attention in LLM Inference
6:38pm - 6:38pm PDTNeuromorphic Ising Solver with Signed Spiking Neuron and Interleaving Simulated Annealing for Large-Scale Traveling Salesman Problem
6:38pm - 6:39pm PDTTechnology-Oriented DTCO Framework Using Neural Compact Modeling and Polar Level-Set Clustering
6:39pm - 6:40pm PDTAn Energy-Efficient Automated Hardware Generator for Edge BCI Systems
6:40pm - 6:41pm PDTSpec2Plan: A Robust LLM-Powered Framework for Verification Plan Generation and Evaluation
6:41pm - 6:41pm PDTSpiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks
6:41pm - 6:42pm PDTSTA Accuracy Validation: A Machine Learning Approach
6:42pm - 6:43pm PDTPRAC-Auto: A Flexible and Efficient Framework for PRAC-Based Rowhammer Mitigation
6:43pm - 6:44pm PDTGzswap: Mitigating GPU I/O Bottlenecks in Heterogeneous Memory Systems Through On-Device Zswap
6:44pm - 6:44pm PDTBeyond Static Policies: Dynamic-PRAC for Balanced and Efficient Rowhammer Mitigation
6:44pm - 6:45pm PDTSNN Accelerator Testing via Sparse Test Matrices
6:45pm - 6:46pm PDTSPEEDY: Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization
6:46pm - 6:47pm PDTHigh Fan-in Dynamic Leakage Suppression Standard Cells for Improved Power, Performance, and Area in Ultra-Low Power Circuits Authors: Suprio Bhattacharya and Benton Highsmith Calhoun
6:47pm - 6:47pm PDTSPICEMixer - Netlist-Level Circuit Evolution
6:47pm - 6:48pm PDTLighthouse RL: Sample-Efficient Circuit Optimization via Strategic Reset Points
6:48pm - 6:49pm PDTEtch-Vigen: A Video Generation Model for Etching Simulation
6:49pm - 6:50pm PDTReConCHF: ReRAM-Based Reconfigurable Architecture for Cryptographic Hash Functions with Software/hardware Integration
6:50pm - 6:50pm PDTTIDE: A Triangular Interaction-Symmetric Dual-Systolic Engine for Efficient Acceleration of Physics-Inspired Optimization
6:50pm - 6:51pm PDTTrace and Chase: Empowering LLMs to Identify the Root Cause of Test Failures in RISC-V SoCs via Textualized Waveform
6:51pm - 6:52pm PDTCMP-Aware Dummy-Fill Optimization via Generative Modeling and Measurement-Calibrated Prediction
6:52pm - 6:53pm PDTA Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis
6:53pm - 6:53pm PDTAtto-Spinformer: An Energy-Efficient Magneto Electric Spin Orbit Logic-Based Compute-in-Memory Transformer Architecture
6:53pm - 6:54pm PDTFast and Accurate RRAM Write-and-Verify via Hadamard-Encoded Read and ADC-Energy-Reduced HARP
6:54pm - 6:55pm PDTLeak-CIM: A PVT-Robust and Energy-Efficient SRAM-CIM Macro Exploiting Transistor Leakage
6:55pm - 6:56pm PDTGeneralized Structural Bias Analysis for Corrupt-and-Correct Logic Locking
6:56pm - 6:56pm PDTTactician: A Formal Workflow for Discovering Unintended Interactions Among Microarchitectural Defenses
6:56pm - 6:57pm PDTLSTM-Based Performance Modeling for Enhanced Peak Memory Prediction in Layout Versus Schematic Verification Tools
6:57pm - 6:58pm PDTA 1.31 TOPS/W CGRA Hardware with SIMD and Programmable Memory Address Generation Unit for Edge AI
6:58pm - 6:59pm PDTO-RRP: Optical Proximity Correction Runtime and Resource Prediction Using Machine Learning
6:59pm - 7:00pm PDTTerastal: Layer-Variant-Based Scheduling for Real-Time Multi-DNN Workloads on Heterogeneous Accelerators