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Late Breaking Results

Student

Work in Progress

: Late Breaking Results, Work-in-Progress Poster Session

Event Type

Late Breaking Results

Student

Work in Progress

TimeTuesday, July 285:00pm - 6:00pm PDT

LocationExhibit Hall

Tracks

Similar Sessions

Work in Progress (WIP) Poster Session

Late Breaking Results (LBR) Poster Session

RM Poster Session One

Presentations

5:00pm - 5:00pm PDT	An Autonomous Design Agent of Parallel Feedforward Equalizer for Advanced Wireline Receivers Authors You-Cheng Tu Rui-Yong Kuo Wei-Zen Chen
5:00pm - 5:00pm PDT	Agentic AI for Chip Design and Verification: Results and Limitations from CVDP Authors Jan Ole Ernst Rajath Salegame Igor Markov
5:01pm - 5:01pm PDT	Late Breaking Results: High-Fidelity Simulation and Real-Time Forecasting of Fluid-Solute-Coupled Microfluidics Authors Siyuan Liang Chenghan Wang Yushen Zhang Zhiqiang Jia Mengchu Li Tsun-Ming Tseng Ulf Schlichtmann Tsung-Yi Ho
5:01pm - 5:02pm PDT	Late Breaking Results: Micro-Dense Tensor-Core-Aligned N:M Sparse Kernel for Efficient Inference Acceleration Authors Liu Yiming Wenqi Lou Ke Zhiwei Fengrui Zuo Chao Wang Xuehai Zhou
5:03pm - 5:03pm PDT	NPU-Based Energy-Efficient LLM Inference for Semiconductor Equipment Control Code Generation Authors Sanghyeok Park Seunghoo Hong Simon Woo
5:03pm - 5:04pm PDT	Late Breaking Results: A Scalable and Efficient Multi-Layer 3D-Printed Microfluidic Design Synthesis Authors Jiashuo Chen Yushen Zhang Tsun-Ming Tseng Ulf Schlichtmann
5:04pm - 5:04pm PDT	R5-Link : Enhancing RISC-V Multi-Core Efficiency with Hardware Message Passing Channels in a 2D Mesh Network Authors Yosef Ida Nachman Abargil Sarit Shvimer Alex Grinshpun Freddy Gabbay
5:05pm - 5:06pm PDT	Split–and–sync Bayesian Learning–driven SRAM Compiler: Automatic Design Tuning with Optimal Banking Authors Jaeseung Baik Ijun Jang Gwanwoo Park Sejun Park Mingeun Song Dahun Ko Doohyun Yu Hanwool Jeong
5:06pm - 5:06pm PDT	ML-Net: Enhanced Interconnect Modeling Through Machine Learning–based Framework and Novel Double-π Networks Authors Parsa Mirfasihi Jatan Mandaliya Omar Yamak Ahmed Shebaita Hamid Mahmoodi
5:06pm - 5:07pm PDT	Will AI Mess my RTL? A Snapshot-Based Approach to Verifying AI-Written RTL Authors Bernat Homs Oscar Palomar Miquel Moreto Marcelo Orenes-Vera
5:08pm - 5:08pm PDT	Late-Breaking Results: QML for Quantum Sensing Under Measurement-Induced Information Loss Authors Sounak Bhowmik Himanshu Thapliyal
5:08pm - 5:09pm PDT	Linearly Scalable Algorithms for DFT Static Verification, Coverage Analysis, and Debug at RTL Authors Kanad Chakraborty Vinod Viswanath
5:11pm - 5:11pm PDT	Late Breaking Results: Die Area and Temperature Co-Optimization for Thermal Throttling Mitigation in Mobile Application Processors Authors Jisoo Hwang SoYoung Kim
5:12pm - 5:12pm PDT	Accelerated Dynamic Voltage Drop Prediction Using a Lightweight Machine Learning Model Authors Itay Yonatanov Ido Parchomovsky Mohamad Omari Freddy Gabbay
5:13pm - 5:13pm PDT	Late Breaking Results: Influential Data Selection for LLM-Based RTL Generation Authors Zhan Song Cunxi Yu
5:14pm - 5:14pm PDT	Late Breaking Results: Quantum-Aware Model Compression Techniques for Scalable Quantum Machine Learning Authors Nouhaila Innan Muhammad Shafique
5:16pm - 5:17pm PDT	PASCAL: ML-Based Predictive Skew Compensation for Asymmetric Clock Tree Aging Author Freddy Gabbay
5:18pm - 5:19pm PDT	Defending Side-Channel Attacks in Client-Side Deduplication with Hardware/software Codesign Authors Yinjin Fu Qingli Zeng Jian Wu Nong Xiao
5:19pm - 5:19pm PDT	Late Breaking Results: Guiding Compiler Optimizations for Neutral Atom Quantum Computers Through Visualizations Authors Yannick Stade Robert Wille
5:20pm - 5:20pm PDT	Late Breaking Results: A Neuromorphic Accelerator for Efficient Multi-Head Attention Processing in Spiking Vision Transformers Authors Rachmad Vidya Wicaksana Putra Amirhesam Jafari Rad Muhammad Shafique
5:20pm - 5:20pm PDT	Late Breaking Results: Q-STEP: A Cross-Layer Design and Validation Framework for Advancing Quantum Sensing Authors Gabrielle MacNeil Hari Paudel Qiaoyan Yu
5:20pm - 5:21pm PDT	Late Breaking Results: Hightide: an Open-Source Hardware Benchmark Suite Authors Benjamin Goldblatt Paolo Pedroso Farhad Modaresi Matthew Guthaus
5:23pm - 5:23pm PDT	A Novel Way to Handle Non-Convergence of Properties in Formal Verification of Digital Systems Authors surinder sood kishan mushar Nirmal Jose
5:23pm - 5:24pm PDT	Late Breaking Results: Energy-Aware Scheduling of Open-Vocabulary Detection on Low-Power Mobile Robots Authors Abdul Basit Nurik Serikbayev Muhammad Shafique
5:24pm - 5:24pm PDT	Late Breaking Results: A Resource-Constrained Co-Design Framework for Enabling Heterogeneous Quantum Chiplet Ensembles via Circuit Cutting Authors Alberto Marchisio Muhammad Kashif Nouhaila Innan Walid El Maouaki Muhammad Shafique
5:25pm - 5:26pm PDT	Late Breaking Results: Analog Circuit Sizing via LLM-Guided Heuristic Search with Metric Difficulty Awareness Authors Xinyue Wu Fan Hu Jani Shaik Zixuan Li Mohamed El-Hadedy Xinfei Guo
5:26pm - 5:26pm PDT	Late Breaking Results: Encoding-in-Memory via Generating True Random One-Time Password Authors Ranyang Zhou Gamana Aragonda Abeer Almalky Filip Roth Tronnes-Christensen Adnan Siraj Rakin Shaahin Angizi
5:27pm - 5:27pm PDT	Hierarchical Learning–based Digital Circuit Design Tuning Framework for Power-Delay Optimization Authors Ijun Jang Jaeseung Baik Gwanwoo Park Sejun Park Mingeun Song Dahun Ko Doohyun Yu Hanwool Jeong
5:27pm - 5:28pm PDT	Late Breaking Results: Analog Circuit Sizing Optimization Using Procrustes-Guided Machine Learning Heuristics Authors Brandon Hippe David Burnett Lydia Lee
5:28pm - 5:28pm PDT	Late Breaking Results: Fast Energy-Aware Neural Network Modeling for Efficient FPGA-Based Inference Authors Rishi Agrawal Andrea Guerrieri
5:28pm - 5:28pm PDT	Late Breaking Results: FeMFET Multi-Level Cell Capacity Limits for SNN-Based Compute-in-Memory Inference Authors Osama Abdelaal Alptekin Vardar Nandakishor Yadav Thomas Kämpfe
5:28pm - 5:29pm PDT	Late Breaking Results: Hardware-Efficient PQ Search Framework for Sparse Coding-Based KV Cache Compression Authors Sohyeon Kim Doohyun Cho Myounghoon Cho Donghoon Han SeungJae Lee Ji-Hoon Kim
5:29pm - 5:30pm PDT	Late Breaking Results: Synthesizable 8-Bit Digital Memristor Emulator with Programmable State Retention for Accelerated Edge Computing Authors Shekhar Suman Borah Philip Waldecker Henry Torbert Prabha Sundaravadivel
5:34pm - 5:34pm PDT	Lockroute: A Spatial Locking Framework for Parallel Global Routing Authors Amber Thrall Vidya Chhabria S. M. Ferdous Mahantesh Halappanavar Bala Krishnamoorthy
5:35pm - 5:35pm PDT	Late Breaking Results: Tiny Brain, Big World: Autonomous MCU-Friendly Navigation for Mapless Dynamic Environments Authors Omer Kurkutlu Arman Roohi
5:36pm - 5:36pm PDT	Late Breaking Results: Unified PCB Routing Considering Pair-Spacing and Width-Range Constraints Authors Wei-Chen Hung Jhih-Jie Lee Sheng-Hua Wang Yao-Wen Chang
5:36pm - 5:37pm PDT	Late Breaking Results: A Fully Differentiable Rectilinear Minimum Spanning Tree Wirelength Model for Global Placement Authors Fuxing Huang Hao Wu Junhong Li Qiyuan Chen Wenxing Zhu xinning liu Ziran Zhu
5:37pm - 5:37pm PDT	Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router Authors Zheqi He Zhendong Zheng teng wang Nanhao Zhou Lei Gong Wenqi Lou Chao Wang Xuehai Zhou
5:37pm - 5:37pm PDT	Late Breaking Results: Physics-Aware Diffusion Framework for Transistor-Level Placement Beyond Standard-Cell Boundary Authors Keyu Peng Junhong Li Hao Wu Chao Wang Jun Yang Ziran Zhu
5:37pm - 5:38pm PDT	Late Breaking Results: LLM-Driven Constraint Generation and Deferred Shape Exploration for Analog IC Floorplanning Authors Yu Chen Fuxing Huang Chengjie Liu Xi Wang Ziran Zhu
5:38pm - 5:38pm PDT	Late Breaking Results: Power Mesh Construction for 3D-IC with Backside Power Delivery Authors Chien-Pang Lu Chun-Hao Lai Iris Hui-Ru Jiang Chih-Hsiang Yang Chung-Ching Peng
5:38pm - 5:38pm PDT	DScNMP: A Dataflow Scheduling for the Precision-Scalable Near-Memory Processing Microarchitecture Author yueting Li
5:38pm - 5:39pm PDT	Late Breaking Results: Astfusion -- Two-Stage Structural Enhancement Learning for Robust HLS Code Generation Authors Ke Zhiwei Wenqi Lou Liu Yiming Fengrui Zuo Chao Wang Xuehai Zhou
5:39pm - 5:39pm PDT	Late Breaking Results: Toward a Foundation Model for 3DIC Thermal Analysis and Beyond Authors Akhilesh Kumar Zelin Lu Norman Chang Igor Markov Lang Lin Jessica Yen Haoliang Jiang Wenbo Xia Yujing Luo Gang Qu
5:39pm - 5:39pm PDT	Automated Design of Device Fingerprinting Circuits for FPGAs Authors James Moore Maire O'Neill CHONGYAN GU
5:39pm - 5:40pm PDT	Late Breaking Results: Recoverability-Guided Layer-Wise N:M Sparsity Under Latency Constraints Authors Liu Yiming Wenqi Lou Ke Zhiwei Fengrui Zuo Chao Wang Xuehai Zhou
5:40pm - 5:40pm PDT	Neural Subgraph Matching for Hardware Decompilation in Gate-Level Netlists Authors Yunzhen Liu Yingjie Li Nan Wu
5:40pm - 5:40pm PDT	Late Breaking Results: 3D Analytical Placement with Smoothed Multi-Die Wirelength Model Authors Xingyu Tong Chih-Jung Hsu Guohao Chen Yin-Hsuan Hung Jianli Chen Yao-Wen Chang
5:40pm - 5:40pm PDT	Late Breaking Results: "describing" Your Way to a Functional Microfluidic Chip Authors Yushen Zhang Louis Dickgießer Siyuan Liang Tsun-Ming Tseng Shigeru Yamashita Tsung-Yi Ho Ulf Schlichtmann
5:40pm - 5:41pm PDT	Late Breaking Results: Scalable OARSMT Generation via Predictive Topological Reduction in VLSI Routing Authors Xiqiong Bai Daiwei Zhang Xiutao Yan zhifeng lin Kun Wang Ziran Zhu Jianli Chen Zhikuang Cai
5:41pm - 5:41pm PDT	Late Breaking Results: QUBO Approaches to Logic Equivalence Checking and Testing Authors Tao-Chun Huang Hao-Yu Tsai You-Cheng Lin Yi-Ting Li Wuqian Tang Yung-Chih Chen Jian-Meng Yang Chun-Yao Wang
5:41pm - 5:41pm PDT	Polaris: Enabling PIM-Optimized Low-Energy SpGEMM Using a Remote-Access-Aware Mapping Solution Authors Helya Hosseini Christina Giannoula Bahar Asgari
5:41pm - 5:42pm PDT	Late Breaking Results: Novel Qubit Mapping for Two-Dimensional Trapped-Ion Quantum Computing Systems Authors Wei-Hsiang Tseng Yao-Wen Chang Jie-Hong Roland Jiang
5:42pm - 5:42pm PDT	Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis Authors Haoyuan Ren Yinkang Gao Yixuan Zhu Bo Zhang teng wang Wenqi Lou Xi Li
5:42pm - 5:42pm PDT	Late Breaking Results: Hardware-Aware Compilation Reshapes Trainability in Variational Quantum Circuits Authors Muhammad Kashif Muhammad Shafique
5:42pm - 5:43pm PDT	Hierarchical ML-Framework for Rapid RDL and Bump Optimisation in GPIO-Encroached Flip-Chip SoCs Authors PRATEEK PENDYALA Vishant Gotra
5:43pm - 5:43pm PDT	Late Breaking Results: Structured Expert Routing for Efficient MoE Inference Under GPU–CPU Orchestration Authors Yixiao Chen Arman Akbari Arash Akbari Zhendong Mi Enfu Nan Xiaowei Lin Weiwei Chen Shaoyi Huang Hao Wang Pu Zhao Yanzhi Wang
5:43pm - 5:43pm PDT	Late Breaking Results: EIV-Aware Backside PDN Synthesis Under Strict nTSV Spacing Constraints Authors Yin-Qi Xu Shao-Yun Fang
5:43pm - 5:44pm PDT	Late Breaking Results: A High-Performance TFHE Bootstrapping Accelerator with Heterogeneous Processing Engines Authors Haopeng Zhang Yukui Luo Jiafeng Xie Wenfeng Zhao
5:44pm - 5:44pm PDT	Late Breaking Results: A Coarse-to-Fine PCB Placement Framework via LLM-Guided Component Grouping and Group-Aware Placement Authors Junhong Li Keyu Peng Fuxing Huang Hao Wu Ziran Zhu
5:44pm - 5:44pm PDT	SAT-Helper: A Multi-Agent System for Adaptive Optimizing Large-Scale Conjunctive Normal Form Authors Zhiyuan HE Rongliang Fu Pin-Yu Chen Tsung-Yi Ho
5:44pm - 5:44pm PDT	Late Breaking Results: A Unified Analytical Framework for MBFF Clustering and Placement for Timing, Power, and Area Co-Optimization Authors Chuan-Chi Su Yu-Sheng Yang Cheng-Yen Li Shao-Hsiang Chen Yao-Wen Chang
5:44pm - 5:45pm PDT	Late Breaking Results: Nano-TSV Assignment for Backside Power Delivery Network Designs Considering Stress and IR-Drop Effects Authors Maoze Liu Yao-Wen Chang Kai-Yuan Chao
5:45pm - 5:45pm PDT	Late Breaking Results: ROAST: Reverse-Training Offset Attack on Spatial Sampling Topologies Authors Shayan Gerami Sepehr Tabrizchi Shaahin Angizi Arman Roohi
5:45pm - 5:45pm PDT	Late Breaking Results: Training-Free CCS Library Generation via Voltage Domain Transformation and PCHIP Interpolation Authors Meng-Hsuan Ho Hung-Ming Chen Hsuan-Ming Huang Jiun-Cheng Tsai
5:45pm - 5:46pm PDT	Late-Breaking Results: Ultra Energy Efficient Personalized Glucose Prediction with RLS Implementation on a Tiny FPGA Authors Georgios Mentzos Theodora Podimata Georgios Zervakis Emmanouil Psarakis Joerg Henkel
5:46pm - 5:46pm PDT	Late Breaking Results: Hybrid-Bonding Architecture with Stage-Aware Mapping for Masked Autoregressive Model Inference Authors Wenxi Gao Zhenhua Zhu Hongyi Wang Yuan Xie Yu Wang
5:46pm - 5:46pm PDT	Late Breaking Results: Hardware-Efficient Quantum Reservoir Computing via Quantized Readout Authors Param Pathak Mansi Od Nouhaila Innan Muhammad Shafique
5:46pm - 5:47pm PDT	Late Breaking Results: Audio-Language-Action Models with Direct Speech Conditioning for Robotic Manipulation Authors Enfu Nan Pu Zhao Yixiao Chen Lin Zhao Juyi Lin Chen Wang Weiwei Chen Yanzhi Wang
5:47pm - 5:47pm PDT	Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis Authors Hao Wu Fuxing Huang Qiyuan Chen Junhong Li Keyu Peng Ziran Zhu
5:47pm - 5:47pm PDT	Late Breaking Results: Fisher-Guided Selective Error Reconstruction for Quantized LLMs Authors Seonha Ryu Il Hong Suh Yeseong Kim
5:47pm - 5:48pm PDT	Late Breaking Results: Towards Low-Latency TinyML via Regularized Activation Packing Authors Georgios Mentzos Konstantinos Balaskas Georgios Zervakis Joerg Henkel
5:48pm - 5:48pm PDT	Accelerating Functional Fault Grading for Flash and DRAM Designs Authors Euisang Yoon Arun Gogineni Saurabh Srivastava Eunjong Oh Seongwook Lee Sungyun Yoo Geonbeom Kwon Yoseop Lee Hyojin Choi
5:48pm - 5:48pm PDT	Chiplite: High-Level Performance Modeling Methodology for Automotive Chiplet Systems Authors Diksha Moolchandani Vinay Kumar
5:48pm - 5:48pm PDT	EdgeQ‑GEMM: INT4/INT8 Mixed‑Precision GEMM Accelerator with On‑the‑Fly Quantization for Accuracy–Energy Tunability in Edge AI Processors Authors Chaebin Jung Kyeongwon Lee Hyunseok Kwak Jongin Choi Sechan Park Sangmin Jeon Hyeonguk Jang Jae-Jin Lee Woojoo Lee
5:48pm - 5:49pm PDT	Swift-Healer: Firmware-Reconfigurable Self-Healing for Remote Glitch-Injection on Autonomous Driving Systems Authors Ali Suvizi Joshua Iwu Kostas Amberiadis Guru Venkataramani
5:49pm - 5:49pm PDT	The Last Line of Defense in DNN Inference: Argmax Security Under Combined Power Side-Channel and Fault Injection Attack Authors Le Wu Liji Wu Yuyang Pan Xiangmin Zhang
5:49pm - 5:49pm PDT	Compact ML-Based Glitch Propagation Modeling of Standard Cells Authors Anastasis Vagenas Dimitrios Garyfallou George Stamoulis
5:49pm - 5:50pm PDT	RELMAS-HRT: Online Inference Scheduling in Mixed-Criticality Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning Authors Francesco Blanco Enrico Russo Giuseppe Ascia Maurizio Palesi
5:50pm - 5:50pm PDT	Nucleus: A Reconfigurable Long-Context LLM Accelerator Using Adaptive Outlier-Aware KV Cache Quantization Authors Youngmin Cho Yoontae Lee Lojin Park Sunjae Lee Jimin Lee Jeongwoo Park Young Oh
5:50pm - 5:51pm PDT	Neuromorphic Ising Solver with Signed Spiking Neuron and Interleaving Simulated Annealing for Large-Scale Traveling Salesman Problem Authors Seongsik Park Jongkil Park
5:51pm - 5:51pm PDT	PHAP: A Pre-Analyzed Head-Wise Attention Pattern for Efficient Sparse Attention in LLM Inference Authors Seonghan Kwon Daeyoung Kim Hyunjae Jang Jaewook Kim YeonJoo Jeong Inho Kim Jong-Kook Kim Seongsik Park Jongkil Park
5:51pm - 5:51pm PDT	Technology-Oriented DTCO Framework Using Neural Compact Modeling and Polar Level-Set Clustering Authors Yongjeong Lee Jeonghwan Kim Jinyoung Lee Youngbin Lee JeongYeol Kim Jung Yun Choi
5:51pm - 5:52pm PDT	An Energy-Efficient Automated Hardware Generator for Edge BCI Systems Authors Chih-Chyau Yang Hao-Ruei Jiang Chien-Ming Wu Chun-Ming Huang
5:52pm - 5:52pm PDT	Spec2Plan: A Robust LLM-Powered Framework for Verification Plan Generation and Evaluation Authors Ting-Wei Chen Tzu-Wei Tseng Pei-Yun Yen Xin-Hong Ou Yun-Ru Li Hong-Siang Wu Jheng-Han Lai Yi-Xin Yang Yi-Hang Chen Gung-Yu Pan Ming-Hui Hsieh Chung-Yang (Ric) Huang
5:52pm - 5:52pm PDT	STA Accuracy Validation: A Machine Learning Approach Authors Rujie Yin Rui Liu Bogdan Tutuianu Florentin Dartu
5:52pm - 5:52pm PDT	Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks Authors Alessio Caviglia Filippo Marostica Alessandro Savino Stefano Di Carlo
5:52pm - 5:53pm PDT	Beyond Static Policies: Dynamic-PRAC for Balanced and Efficient Rowhammer Mitigation Authors Jeonghyun Lee Minwoo Ahn Jisung Park Jinkyu Jeong
5:53pm - 5:53pm PDT	Gzswap: Mitigating GPU I/O Bottlenecks in Heterogeneous Memory Systems Through On-Device Zswap Authors Boyeol Choi Sanghyun Park Sanyhyun Hong Jungrae Kim
5:53pm - 5:53pm PDT	PRAC-Auto: A Flexible and Efficient Framework for PRAC-Based Rowhammer Mitigation Authors Seomgim Jeong Sunggi Ahn Saeid Gorgin Jungrae Kim
5:53pm - 5:54pm PDT	SNN Accelerator Testing via Sparse Test Matrices Authors Osita Ukwuaba Cory Merkel
5:54pm - 5:54pm PDT	SPEEDY: Single-Step Reinforcement Learning Framework for Efficient Analog Circuit Sizing Optimization Authors Chun-Yen Yao Chun-Yen Wu Matteo Guarrera Alberto Sangiovanni-Vincentelli Pierluigi Nuzzo Rikky Muller
5:54pm - 5:54pm PDT	High Fan-in Dynamic Leakage Suppression Standard Cells for Improved Power, Performance, and Area in Ultra-Low Power Circuits Authors: Suprio Bhattacharya and Benton Highsmith Calhoun Authors Suprio Bhattacharya Benton Calhoun
5:54pm - 5:55pm PDT	Lighthouse RL: Sample-Efficient Circuit Optimization via Strategic Reset Points Authors Mustafa Gürsoy Stefan Uhlich Ryoga Matsuo Yağız Gençer Arun Venkitaraman Chia-Yu Hsieh Andrea Bonetti Lorenzo Servadei
5:55pm - 5:55pm PDT	SPICEMixer - Netlist-Level Circuit Evolution Authors Stefan Uhlich Andrea Bonetti Arun Venkitaraman Chia-Yu Hsieh Yagiz Gencer Mustafa Emre Gursoy Ryoga Matsuo Lorenzo Servadei
5:55pm - 5:55pm PDT	Etch-Vigen: A Video Generation Model for Etching Simulation Authors Li Ding Zhenjie Yao Lingfei Wang Rui Chen Zhiqiang Li ling li
5:55pm - 5:56pm PDT	ReConCHF: ReRAM-Based Reconfigurable Architecture for Cryptographic Hash Functions with Software/hardware Integration Authors Ching-En Kao Chin-Fu Nien
5:56pm - 5:56pm PDT	TIDE: A Triangular Interaction-Symmetric Dual-Systolic Engine for Efficient Acceleration of Physics-Inspired Optimization Authors Chia-Hua Yen Chin-Fu Nien Ren-Guey Lee Yuan-Ho Chen
5:56pm - 5:56pm PDT	Trace and Chase: Empowering LLMs to Identify the Root Cause of Test Failures in RISC-V SoCs via Textualized Waveform Authors Yicheng Zhong Jingzheng Wu Xiang Ling Hao Lyu Zhiqing Rui Tianyue Luo Chen Zhao
5:56pm - 5:56pm PDT	CMP-Aware Dummy-Fill Optimization via Generative Modeling and Measurement-Calibrated Prediction Authors Ji-Hye Lee Min-Chul Park Yeji Kim Usuk Chae Byungchul Shin Hyunjae Jang JAE HYUN KANG SeongRyeol Kim Young-Gu Kim Dae Sin Kim
5:56pm - 5:57pm PDT	A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis Authors Muhammad Hadir Khan Matthew Guthaus
5:57pm - 5:57pm PDT	Atto-Spinformer: An Energy-Efficient Magneto Electric Spin Orbit Logic-Based Compute-in-Memory Transformer Architecture Authors Hasita Veluri Dilip Vasudevan
5:57pm - 5:57pm PDT	Fast and Accurate RRAM Write-and-Verify via Hadamard-Encoded Read and ADC-Energy-Reduced HARP Authors Ilhuan Choi Jiwon Yoo Yoona Lee Yewon Jeong Jason Lee Woo-Seok Choi
5:57pm - 5:58pm PDT	Leak-CIM: A PVT-Robust and Energy-Efficient SRAM-CIM Macro Exploiting Transistor Leakage Authors Hiroto Tagata Hiromitsu Awano Takashi Sato
5:58pm - 5:58pm PDT	Generalized Structural Bias Analysis for Corrupt-and-Correct Logic Locking Authors Joseph Madera Kyle Juretus
5:58pm - 5:58pm PDT	Tactician: A Formal Workflow for Discovering Unintended Interactions Among Microarchitectural Defenses Authors Kartik Ramkrishnan Stephen McCamant Pen Yew Antonia Zhai
5:58pm - 5:59pm PDT	A 1.31 TOPS/W CGRA Hardware with SIMD and Programmable Memory Address Generation Unit for Edge AI Authors Rakshith Harish Vishnu Nambiar Yuntian Liu Yi Sheng Chong Wang Ling Goh Rahul Dutta Anh Tuan Do
5:59pm - 5:59pm PDT	Terastal: Layer-Variant-Based Scheduling for Real-Time Multi-DNN Workloads on Heterogeneous Accelerators Authors Sing-Yao Wu Fengshuo Song Eli Bozorgzadeh
5:59pm - 5:59pm PDT	O-RRP: Optical Proximity Correction Runtime and Resource Prediction Using Machine Learning Authors Neha Sharma Wyatt Clarke Dallas Lea Lei Zhuang Jeonghee Kim Harsha Krishnareddy Edward Seabolt Vandana Mukherjee Gi-Joon Nam
5:59pm - 6:00pm PDT	LSTM-Based Performance Modeling for Enhanced Peak Memory Prediction in Layout Versus Schematic Verification Tools Authors Norhan Abdelhafez Ahmed Hosny Mohamed Abouelyazid Samar Abd El-Hady Wael ElManhawy Samy Nada

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