Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Poster: Engineering Poster Session ThreeEvent TypeEngineering PosterTimeWednesday, July 293:00pm - 4:00pm PDTLocationDAC Pavilion, Exhibit FloorTopicsAIChipletDesignEDAQuantumSecuritySystemsSimilar SessionsStatic Verification: The Sentinel Guarding RTL IntegrityWork in Progress (WIP) Poster SessionLate Breaking Results, Work-in-Progress Poster SessionPresentationsTiming Aware Power Integrity Enhancement in Performance Core Architectures Through Advanced Custom Global PG-Fill TechniquesAuthorsJoel JoySudhakar MaruthiJoshy MathewMadhur JagotaAnand RajagopalanDynamic CDC Verification Using SVA for Waiver ReviewAuthorsMegha HansaliyaSushovan KuntiA Scalable Timing Analysis and Closure Methodology for Ultra-Large DesignsAuthorsAvinash SekarABUBAKAR SIDDIK KANCHARAArvind NVDaksh BakshiHarivenkadesh MohanrajHimanshu TanwarChaya NHarish GMixed Transistor Design ClosureAuthorsAjoy MandalMuthu A LRavinder KumarAlok VermaAmit DhuriaTrack Analyzer + VisualizerAuthorYamini RavishankarFrom Bottleneck to Breakthrough! Accelerating Circuit Verification Beyond ExpectationsAuthorsKesmat ShahinMonil PatelAmal RajGaurav DeshpandeSLC-Based Real-Time Traffic Buffering with DRAM Row-Aware Write BackAuthorSoojin ParkCrosstalk Hotspot Map Creation at Placement Stage Using CNN UNET Prediction ModelAuthorLoknath MoogiA Real-Time Metric‑Driven Scorecard for Quantifying and Benchmarking Physical‑Design Quality and Deployment ProgressAuthorsMurtaza TankiwalaAshishkumar PalKavithaa RajagopalanAnanya GuptaReal-Time Local Layout Effects Analysis for Advanced Design OptimizationAuthorsAhmed SalehWoonggyu LeeTaehyung LeeJongku KangJooyoung SongMohamed AlimamDevelopment of Machine Learning Framework for Split-Parameter Optimization of LDMOS DevicesAuthorAriel YehAchieving High-Integrity Safety for 360-Degree Automotive Display Soc's RETIME-IP: A Static Analysis Approach to ASIL-D ComplianceAuthorsJerry (Chaojie) ChenNiko (Bicheng) GuoSesha Sai Kumar C VJamil R MazzawiRevisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery FlowAuthorsInsub ShinJoonyoung ShinMyeonggyun JeongSangdo ParkJun SeomunHyung-Ock KimAccelerating Full Flat EMIR Sign-Off in Multi-Billion InstanceAuthorsSatyaki MandalRamaChandra RajaMekala RishikanthArpan BhowmikHierarchical IP Block Resizing on the FlyAuthorsWilliam DoughertyEduard HerkelAlexander LaichingerTimothy SchellJulian StefanacAlexander SuessGoogle's Faster and Earlier Chip Finishing with Seamless Power Grid Enhancement IntegrationAuthorsRakesh ReddySmitha Shivaji KamathiAnish PadhiEsraa SwillamSunil babu PArtur BabayanAnahit UnanyanFPGA-to-ASIC Conversion via Hierarchical WrappingAuthorsAli El-ZeinKenneth PoorBrian VanderpoolMaya SafieddineZero‑Glitch Confidence: An End‑to‑End Static, Formal & Simulation MethodologyAuthorsAnshul BansalGunjan MamaniaSrinidhi ParshiSuresh Babu BarlaSWETHA KARUSALAsuresh barlaEnhancing UVM RAL for Secure and Privileged Flash Memory Interface Verification Using Cadence AMBA VIPAuthorsVikas SauravJagriti KhuranaShaifali BansalArchana AryaOptimizing GPU Clock Power: Exploring Register Array Folding and Its Trade-OffsAuthorDeepayan DasguptaAccelerating Memory Cache Verification with AI-Powered Batch Flow MethodologyAuthorsAnik SrivastavaSai Surya KannanJayne AlexanderFair Play in the Multiplex: Formal Verification of Complex Arbmux DesignsAuthorsSukanya MoreKaran RawatAnshul JainNew Thermal Analysis Workflow for 3DIC DesignsAuthorsSubramanian LalgudiSadha ParasuramanNitish KumarNicholas NealSatish SuranaMike WalshCDG-DNN: Scalable Test Template Generation Using Adaptive Neural Architecture for Industry Class CDG Hardware VerificationAuthorsSneha VargheseDevleena GhoshAkshay KumarMelchizedek DasRuchi MisraSuraj MukadeSajay MathewArun JosephAchieving "zero Defect" Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & VerificationAuthorsKrishanu DeyGanesha Moorthy KrishnasamyAjaj AnsariJayne AlexanderECO Strategy for BIG DIE SOC ConvergenceAuthorsSabya Sachi SahuAniket AgrawalPushpendra YadavRaghu M SChetan B SCapacitance Modeling for Meander Co-Planar Waveguide Devices Used in Quantum ComputersAuthorsNing LuRichard WachnikLeveraging Liberty Modeling to Enable Validation of Critical Inter-Lane Skew and Sync Symbol Specifications for Multi-Lane High-Speed PHY TransmitterAuthorsAru SharmaManish BansalKirtiman RathoreAnil DwivediIsolated Lightning Rod Diode Structure for Process-Induced Discharge (PID) Dissipation to Reduce Leakage on Integrated Passive Device (IPD)AuthorsRamy Nashed Bassely SaidJagat ShakyaJames WaldemerJianyong XieShamika DolasKaladhar RadhakrishnanENHANCED AUTOMATION FOR GENERATING LOGIC-OPTIMIZATION ECOs (EAGLE) IN SIGNOFFAuthorsBhukya SardarKetavanya DubakulaSatish SethuramanAnantakrishnan NSNaveen BishnoiSELECT: Sensitivity Based Exploration and Localisation of Event-Wise Correlated Tokens for Test GenerationAuthorsDevleena GhoshMelchizedek DasKetul PatelKatie SeggermanArun JosephThe Power Grid Reuse ProcessAuthorJustin ConklinRapid Design and Deployment of High-Radix Switch Fabric for Scale-up and Scale-out AI SystemsAuthorSaurabh GayenBridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP VerificationAuthorsAnil RajashekaraShameer YerragudiSivasankar NagineniNeel NatekarSiddharth SinghBridging the Modeling Gap: State-Aware Liberty Enhancements for Multimode IP DesignsAuthorSAURABH SRIVASTAVAMethodology to Optimize the Length of Software Test Library (STL) to Reduce Execution-Time to Meet Both System and ISO-26262 ASIL-B RequirementsAuthorsJamil MazzawiSesha Sai Kumar C VAyman MouallemYazid MuaketThe Pursuit of Golden Specification: Leveraging Architecture FormalAuthorsRamya HariharanPratik MahajanTAWT: Towards Autonomous Wrapper TuningAuthorsPardhu PavanAyan DattaVikash K TKavana VKundan JhaComprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification MethodologyAuthorsShibin VelluvaNeel NatekarActivity Reloaded: Joules Flash Replay - A Methodology for Accurate, Delay-Based Activity Generation for Driving Optimization and Power Sign-offAuthorNimish AgashiwalaEarly DEF-Based Hierarchical Power Grid Shorts AnalysisAuthorsSanghmitra JhaGreg FordINTENT-AWARE RDC ANALYSIS USING MINIMALLY BOOLEAN REASONINGAuthorsMegha HansaliyaSushovan KuntiVarun SharmaVikas SachdevaAlok MehrotraRaghavendra NadigerFlexible NoC IP: Software Based Configuration and Fast Performance ValidationAuthorKent OrthnerMaximize RoI Through Glitch Power Optimization at Early Design StageAuthorsAbbin Perunnilathil JoyAwashesh KumarChristina FarranFormal Verification Engineering for Integer Vector Neural Network InstructionsAuthorsJaideep RamachandranRoope KaivolaReduced Order Modelling (ROM) Based Full Chip EMIR SignoffAuthorsPradhosh Lakshmi NarasimhanAkshay KhareVinuja SridharPRATHWIKA KANNAGOLA PRAKASHStatic Timing Analysis (STA) Platform: An AI-Augmented Web System for Scalable Static Timing Analysis and OptimizationAuthorsSubhash UppalaManjunath NayakAnoop SinghAyan DattaTusharkant MishraBeyond Hierarchical Static Verification: Smart Stubbing for Next-Gen AI AcceleratorsAuthorsAnshul BansalSWETHA KARUSALAHarish Aepalasuresh barlaTackling Local Noise Coverage Limitations in Transient EMIR Analysis for Robust SoC-Level PDN ClosureAuthorsAkhilesh MishraAbhinav GaurMANOJ CHAHANDEAmit JangraShreyashi .Shatakshi SrivastavaScalable EMIR Signoff for Very Large SoCs Using Reduced Order ModellingAuthorsPriyanshu MHemanth KarnatiBhupesh BakshiMohammed Yousuff ShariffVmin Reliability Through Critical Path-Aware PDN AnalysisAuthorsMohit JainRoshan RoyAthanasios GkarasAI-Accelerated Signoff Verification and Glitch Analysis for Single and Multibit Level ShiftersAuthorsRaghu BMHareharan NagarajanAjaj AnsariJayne AlexanderAccurate Characterization Methodology for Combo-IO Design with Concurrent Switching Outputs for Precise Power Analysis at SoCAuthorsPawan VermaSAURABH SRIVASTAVAMatthieu FillaudRay ValenciaHierarchical Cost-Efficient IR Methodology for AI SoCsAuthorsPrashanth MuthuswamyAnuj TrivediHariram RavindranKartik IyerAutomated Workload Analysis for Dynamic Voltage Drop Optimization and Faster Power Integrity Signoff in Complex SoC DesignsAuthorsPriyanshu MHemanth KarnatiBhupesh BakshiMohammed Yousuff ShariffMachine Learning Optimizer-Driven Automatic Full Compact Model Extraction Flow DevelopmentAuthorFahad UsmaniML Based Design Space Prediction for Power Grid OptimizationAuthorsAbhinav GaurAkhilesh MishraMANJEET KUMARAmit JangraAI‑Assisted Formal Verification: Improving Practical Adoption and ScalabilityAuthorsVivek RahejaHarsh GuptaMuhammed Luqman JukakuAutomatic SDC Creation for Static Timing AnalysisAuthorsEric ForemanNate BuckJack DiLulloHemlata GuptaDoug LambGreg SchaefferFree Hand Routing- Sketch to LayoutAuthorsDiwesh PandeyJayant SinghSurya SirikiAlaparthi SaiKiruthika BalachandranBoosting IP Quality and Productivity Through Ipdelta Profile-Driven Change DetectionAuthorsAnil Kumar DwivediJean-Arnaud FrancoisManda Padma SindhujaTanvi AhujaSiddharth RavikumarAI-Accelerated Optimization Flow for Robust Analog and Mixed-Signal Circuit Design Against Process VariationAuthorsIrving HsuLih-Jen HouLocal Layout Effect Coverage Check Using Artificial Neural Network-Based Surrogate ModelsAuthorsKwonwoo KangAbdelrahman DarwishSung-Sik ParkJungseok LimYeongcheol JeongPast Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)AuthorsJebin MohandasRakesh KandulaSachin JainMax KorbelPing LimStaged Snapshots for Firmware-Hardware Collaborative DebugAuthorsPretty JacobCarsten OtteJoachim ParetArun JosephAttacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage AssessmentAuthorsHarikrishnan BalagopalEmrah KaragozShailandar SachdevaKaran HiranandaniKarthik GedelaFerhat YamanGeethu Sathees BabuLang LinAmitabh DasSourabh GoyalNo More Blind Spots: RTL Modeling of Metastability for CDC VerificationAuthorsArchana AryaAnkur BalAnusha ThikkalaFrom Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto CoreAuthorsPrashee AroraHarikrishnan BalagopalMitra MirhassaniLang LinNorman ChangCPPR-Aware Tap-Point Reassignment in Flex-H and Multi-Point CTS for Timing Closure in High-Performance CoresAuthorOmang MahureAccelerating X-State Aware Power Simulation Using Advanced Hardware EmulationAuthorsJihye LimYungi UmSungtae KangJihyun JangYoungsik KimScreening Analog Anomality for Security Vulnerability in Digitally Verified Crypto CoresAuthorsSatoshi KubotaKazuki MontaLih-Jen HouYuLing LinMakoto NagataAutomated System for FPGA-Based SoC PrototypingAuthorsStefano CumiaAndrea ConcilEfficient Routing and Connectivity Repair for Large-Scale Hierarchical Metal NetworksAuthorsAmogh GuptaDiwesh PandeyScalable, Emulation-Friendly,co-Simulation Testbench for Exhaustive RISC-V Cluster Configuration VerificationAuthorsBheema ThangaveluKen GildersleeveE J HannahPravin TavagadStructure Aware Clock Tree Synthesis Using Width-Driven CTS Cell ConstraintsAuthorsAyush KhareMohit GuptaSrikanth VentrapragadaLoknath MoogiA Rule-Aware Layout Conversion Framework for Back-End Physical DesignAuthorsJaeeun KimJuhyun KangHyunchul HwangGwanghoon YunWoongSik JungAdvanced Automation Framework for Clock and Reset Management in SoC Designs – Bridging Design Intent, Verification, Test and ImplementationAuthorsMurtaza TankiwalaKirti PalaiShreya GuptaSuganthi VadivelMuruganParnab GhoshSujaan DubeyMilan VargheseShruti GuptaAnkita MohantyDesmond FernandesKavithaa RajagopalanSai Ram JayanthiTony JoseDesigning Power- and Area-Efficient Custom NPUs for Edge AIAuthorsGert GoossensViswateja NemaniErik BrockmeyerHunting RTL Glitches Before They Burn Power: A Practical RTL Success StoryAuthorsXiaobing TangZhongming HouLing SunShixuan QueFengyu XiaoWanyan JiIn-Situ Architecture for Detecting and Mitigating Off-Chip Interface AttacksAuthorsAnkur BalArchana AryaIntelligent Clock Domain Crossing: Activity-Aware Synchronization for Low-Power SoCsAuthorAradhana KumariLint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint CorrectionAuthorsNirmit JallawarMark MendozaSamantak GangopadhyayShubham KumarSiddharth BhargavYiran LiSriram MuthukumarKaushal GandhiOlivia WuUsing ML-Assisted Side-Channel Analysis in Simulation: A Case Study on AES-GCMAuthorsEmrah KaragozKarthik GedelaFerhat YamanAmitabh DasSourabh GoyalCrosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow FrameworkAuthorsLoknath MoogiMohit GuptaSwathi GangesettiAyush KhareMorph-Inspect: Structural Assurance for Inserted LogicAuthorsMaya SafieddineAli El-ZeinKenneth PoorFaith CurtisViresh ParuthiArvind Haran
