Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowEngineering Poster: Engineering Poster Session TwoEvent TypeEngineering PosterTimeTuesday, July 285:00pm - 6:00pm PDTLocationDAC Pavilion, Exhibit FloorTopicsAIChipletDesignEDAQuantumSecuritySystemsSimilar SessionsIP Design for Mixed-Signal and High-Speed SoCsLate Breaking Results, Work-in-Progress Poster SessionWork in Progress (WIP) Poster SessionPresentationsDesign Verification Automation (DVA) for PCB Signal and Power IntegrityAuthorsSherif AmerAdam El-MansouriColton LoveGarrett StaufferTracey WindleySlack-Exploiting Load Splitting for IR-Drop MitigationAuthorsChou HsiangYu-Wen LinWesley HsiehFlorin DartuCharles KuoNate TaiPhysics-Aware CNN-Based IR Drop Risk Prediction for Fast and Reliable SRAM Placement OptimizationAuthorsSeihyung JangHyoungRae Nohyun rasangkyoo jeongkaram ahnminjae chungRDC Methodology: Noise Reduction and Improving AccuracyAuthorsSushovan KuntiMegha HansaliyaUser Definable Custom Primitives in 3DIC AI-Driven STCO: Case Study on Power Grid Optimization for IR EnhancementAuthorsYi-Wei ChenChung-Ching PengVivek RajanXukang WuXiaohu XuSonia BeghumKeshava ManimundaWeifeng GuHanqi YangPinhong ChenEarly, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICsAuthorsKopal KulshreshthaEmmanuele MazzaráResistive Model-Based via OptimizatiionAuthorHeng Lan LauVeriscore: Measuring LLM Verification Quality with Mutation- and Soundness-Based MetricsAuthorsRohil KhareTamzid RazzaqueEarly Antenna Analysis for IC Design: A Shift-Left Approach to Improve Productivity and Signoff QualityAuthorsNagaMalleswari MetlaPraneeth NarsingojuKalyanaKumar AmruthuluriBasma SerryNermeen HossamMingyong YuDifferential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage IntegrityAuthorsPRATEEK PENDYALAMathew KaipanatuSai AtluriRenjith RA Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar SystemsAuthorsAnkur BalPrince BansalJeet TiwariHarvinder SinghA Simple and Predictable Solution for Early Full-Chip LVS ConvergenceAuthorsRavidas DamodaranTayib SamuKumaresan VallinayagamVishnu ChandrakarBreaking the Simulation Wall – Practical Acceleration for Pre-Silicon ValidationAuthorsSundarraj DurairajVaibhav KumarTauqueer AlamRagavendar SwamisaiDavid ChaoManik ChughAccelerating CPU Design in Advanced Nodes with AI-Powered Floor Planning and VT OptimizationAuthorsLakshmidas KGowry ShanmugamMeeting EDA Workload Capacity Needs with AWS for Siemens' Solido Custom IC TechnologiesAuthorsAzim SiddiqueSaurabh KulkarniRoutability Optimizing Methodology Using Flexible PinAuthorsJinman KangChaewon SongHeeyoung MoonSangdo ParkJun SeomunHyung-Ock KimXchip: A Guardrailed Agentic Gen-AI Front-End Flow from Intent to GDSIIAuthorsKaiyuan YangTiantai DengCharith AbhayaratneJohn GoodenoughAn Adaptive Dynamic Power Reduction Technique for Digital FiltersAuthorsAnkur BalPrince BansalHarvinder SinghBreaking the O(N^2) Barrier: AI-Assisted Linear-Time Formal Verification of Deep Pipeline BuffersAuthorNitin AhujaAgentic AI Partition And Floorplan Assistance For PCIe/CXL Subsystem Physical DesignAuthoryuwenyuan gaoNovel Methodology to Replace Openaccess Inputs for Hierarchical Chip ConstructionAuthorsEduard HerkelJesse SurpriseJoel EarlGregory SchaefferNovel Methodology for in Context Blockage Modification for High-Speed Global Clock RoutingAuthorsJonas OberröhrmannJan HimanekEduard HerkelPeter NasveschukPlug-and-Verify Using Real USB Devices for Front-End Host DUT RTL ValidationAuthorSuchir GuptaA Hybrid Simulation and Formal Verification Approach for Exhaustive Interrupt and Status Flag VerificationAuthorsGiovanni AuditoreJagriti KhuranaShaifali BansalVikas SauravArchana AryaCognitively Guided EM-Aware Routing Approach for Efficient Layout ImplementationAuthorsAkshita BansalSachin BhasinRajeev SinghNisha RanaAutomotive Logic Test Power ManagementAuthorsChen Yuan KaoMing Hsien HsiaoSin Huei LiChen Tsai WeiFully Automated On‑Chip Inductor Synthesis for High‑Frequency VCO with ML Based Optimization FlowAuthorsSahil JhaKapil TyagiNitin JainAtul BhargavaPrayes JainVishesh KumarLibrary PPA DTCO with Library ProfilerAuthorsJaehwan JeonInguk MinIlsu SonByungsu KimAhyoung KwakConnor SchentagEfficient Power Management in USB4 RoutersAuthorsScott GuoJunjun LiangJack DengHongwei MaFei RenMorten ChristiansenLow Power Optimization Through Fast and Accurate Time-Based Power AnalysisAuthorsSORA PARKMYUNGJIN CHOIHEONSEOK HONGJONGPIL LEEKIJOON HONGNAYEON PARKKUNSANG PARKHYESUN KIMJONGWON YIMulti-Cycle Dynamic Vectorless Analysis for Improved PDN SignoffAuthorsMahesh YatagiriChen LiNikhil JatanaMahesh SubramanianPalkesh JainAnukul RangarajanNM-IF: A Deployable Near-Memory Interface for Incremental System-to-Memory OffloadAuthorsyueting LiTeng TengTao WuEnhancing the Robustness of Impinj RAIN RFID Design Through the Application of AI-Powered Process FlowAuthorsMan Chun LiuAgustinus SutandiEric WongHoward TangDevdatt HaldipurLih-Jen HouA Chip-Level DTCO Framework for Yield-Aware Back-End Design: Layout-Aware Misalignment Correction in DRAMAuthorsHyeJin KimSoYoung KimAccelerating IR and Timing Convergence with Revolutionary IR-ECOAuthorsPing DingTuo WangGuohua ZhouLi ZouChang ZhaoA Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive ApplicationsAuthorsTakuya SuzukiLih-Jen HouYuLing LinBeyond Scripting: API Based HDL GenerationAuthorJack GreenbaumIdentifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced NodesAuthorssanthosh kamatamPramod GayakwadAjay KumarRay ValenciaGabriel RojasPerformance Boosting DTCO Methodology for 1-to-1 Metal-Gate Pitch RatioAuthorTaeyong BaeToward an Open Chiplet Ecosystem: Arm® Foundation Chiplet System ArchitectureAuthorsShivangi AgrawalRohit GuptaAccelerating DFT Verification and Enhancing Debuggability Using Veloce-Based Full Chip Gate-Level EmulationAuthorsJaesung ParkJeongjun LeeHyundon KimKyoungmin ParkYoungsik KimDohyeon LeeYounghyun ChoChangkyu LeeByungjik KimInhwan KimJustin LeeChanjin KimARTEMIS: Agentic AI for EDAAuthorsFelix DavidDhara VaishnavNupur BhongeSameer FarooqNovel Approach to Signoff Large MRAM Memory IP Using Hierarchical FlowAuthorsDinesh ChandraSushma SambturDeepak Kumar SahooKumari Saumya DiwediNaveen BShreya SashiAI-Driven Co-Optimization of Power Delivery Network for High-Power Cores in 2.5D Advanced PackagingAuthorsShineng MaLi ZouBin YuChannel Width Optimization for IR Drop Reduction in Advanced SoCsAuthorsShashank NAGovind PalShreyasi DastidarPrateek GuptaAmit JangraAwantika SinghKrish AggarwalFrom Concept to PPA Confidence - Methodology for Rapid RTL Evaluation and Signoff with Joules RTL Design Studio.AuthorNimish AgashiwalaAn Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA SystemsAuthorsShubhi AgrawalRamteja KothamasuPrajjwal SoniNeel NatekarHarshit AroraIntegrated Design Approach for Robust and Area-Efficient IO Ring in Advanced Process NodesAuthorsSukhmani VirkNinad KhireKavithaa RajagoplanSneha ShettySiddharth GuptaAI-Enabled Flow for Silicon Area Reduction and Design ClosureAuthorssaurabh gautamanil yadavFrom Broken Regression to Root-Cause Commit in One Click A Two-Stage Regression-Aware Git-Bisect Framework for Large-Scale Hardware VerificationAuthorSai Sri Ram Goud ChamakuriA Novel Methodology for Automated LVS Rule Deck Verification: Truth Table and Device Extraction QualificationAuthorsAhmed SalehJaeyoung SoMinho JungHeejae LimJimin YeoYunseong LeeJiyoung ShinMohamed AlimamAi&cell Based Analog Circuit Topology Generator(ctgen)AuthorsAkira KURUSUKouji HIRAIShigeya YAMAGUCHIJin WATANABETakuto OGURAChao GENGMasanori KUSANORyou HAMADAKazuhiro KUDONobuto onoTsuyoshi MASUBUCHINobukazu TAKAIShigetoshi NAKATAKETetsuya IIZUKAAutomating DFT Intelligence: Addressing TCPF Hotspots at Source Through Design Aware Test Points in Systemrdl-to-RTL GeneratorsAuthorsVeerabhadrarao VasaRajesh GottumukkalaVikash GuptaFreddy NunezAn Adjustable Length Compression Method for MBIST Repair InformationAuthorsOuyang KeqingQi ChengMinqiang PengGuohua ZhouSri GantaScalable, Protocol-Agnostic Clockless In-Band Reset Architecture for Serial Link IPs in Multi-Domain SoCsAuthorsAradhana KumariAnkur BalNo Credit Where Credit Is Due: Quiesced Formal Check for PCIe CreditingAuthorsIsha LalePradip PrajapatiAnshul JainModeling and Optimization of Power MOSFET Device Layouts with Optislang ToolAuthorsMandar DeshpandeClaudia DumitrescuKhawja SikanderMulti-Cycle Interconnect Synthesis in Small to Large Cutting MethodologyAuthorsJesse Surprisenancy ZhouChandler BrownJosiah HamiltonDeep Reinforcement Learning Paradigm for Analog Design AutomationAuthorsSharath C RSenthil Kumar SundaramoorthyKrishna TejaChanakya K VSujith M ASuberus HeartrishaAI-Assisted EDA Tools DevelopmentAuthorsMaya SafieddineArvind HaranRichard CarboneKenneth PoorFaith CurtisAli El-ZeinViresh ParuthiCustom Implementation of High-Speed Digital Blocks Using Virtuoso StudioAuthorsPratik KordeSumanth SKishan ChanumoluBIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Reasoning for RTL Synthesis and SummarizationAuthorsPrashanth VijayaraghavanLuyao ShiApoorva NitsureDavid BeymerEhsan DeganVandana MukherjeeCorrect-by-Construction Framework for Robustness Against Divergent Voltage Drops and High Clock DivergenceAuthorsPRATEEK PENDYALAMathew KaipanatuAccelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper GenerationAuthorsBindumadhava SinganamalliPandithurai SangaiyahSean SafarpourSayandeep Sayandeep SanyalSandeep JanaRaja MahadevanMulti-Level Intelligent Waveform Orchestration: Specification-Aware Framework for Eliminating Storage-Debug TradeoffsAuthorVinoth SelvanEnabling AI Agent Flows for Verification Triage & DebugAuthorsArvind HaranBryan HickersonDivya JoshiYugal KithanyKenny PoorMaya SafieddineAli El-ZeinViresh ParuthiDaniel CoopsGraph Isomorphism for Explainable Transistor-Level Circuit ComparisonAuthorsAshutosh JadhavXin ZhaoEhsan DeganVandana MukherjeeTaming the Beast: A Formal Verification Approach to Solve Design Complexity- GPU Compression Block Case StudyAuthorsUsha Rani BagadiRahul DaburNamita RawatBathri Narayanan SubramanianArchitectural Formal Verification of Configurable Address Translation Logic for Early Bug ExposersAuthorsMohit ChoradiaSuraj KambleWinnie YeungMulti-Agent Generative AI Pipeline for Assisting in Design VerificationAuthorsPratham GowthamTejas BhatChethan BomannaAnil DeshpandeAuto-Chk: Closing the Last-Mile Interpretation Gap in Digital Sign-off via a Neuro-Symbolic Compiler FrameworkAuthorWentao DaiA Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time ControlAuthorsPriyanshu SahuSwapnil SharmaSachin KhojaPalak JainJason PoonANA-MODELGEN: Automating Analog IP Model Generation and Validation for Efficient Mixed-Signal VerificationAuthorsAadhar SharmaParthasarthy RameshRinu MathewDavid MendozaSooraj SekharSrijan SoniEfficient Power Modeling of Multi-Domain Clock Gating CircuitsAuthorsSpandana RNagu DhanwadaWesley DunganA Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes DesignsAuthorsXin ShuJinrong YanHang SunXuewei DingXiaofan LuXiaomei YouJie ChengAccurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same ChipAuthorsShih-Jie ChangYen-Pin ChenTzu-Hen LinFlorin DartuHardening Security of HW IPs by Verifying Their Negative Space FormallyAuthorsSayak RayJason FungBo-Yuan HuangArun KanuparthiMohammad BidmeshkiMehdi MohtashemiRamya HariharanVivek TiwariWeeding Out Timing Gaps and Improving Performance of DDR Controllers Using Formal VerificationAuthorsRaushan KumarAnshul JainFormally Validating Industry Standard BCH‑ECC/CRC Codes – A Step by Step RecipeAuthorsDisha PuriAatreyi BalBreaking Sequential Depth Barriers: An FSM-Driven Bridge for the Formal Verification of Virtually Address-Mapped Hardware RegistersAuthorsSarvesh TIWARIAyush .Ashwin SinghalTom WeissErik SeligmanHierarchical Functional Fault Grading with Auto-Identification of Observation Points for Faster Fault Coverage Closer in Complex SoCsAuthorsVeerabhadrarao VasaRajesh GottumukkalaKasi ChunduriKarthikeyan SubramanianArun GogineniGaurav GoelAccurate Full-Custom Thermal and EM Analysis for Advanced NodesAuthorDavid NewmarkFlexible & Scalable Network Modeling for AI/HPC Network VerificationAuthorsSanghyeon HwangMinho ChuA Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCsAuthorsPrasad DandraThejeswara ReddyTushar VrindSomraj ManiVenkata Raju IndukuriKrishnakant PatilAmol Kumar JagtapOutsmarting State Space Complexity Through Proven Reset Abstraction StratergiesAuthorsS R PavitraSharika ShajuAnshul JainCost-Based Partial Subgraph Matching for Circuit Pattern RecognitionAuthorsAshutosh JadhavXin ZhaoEhsan DeganVandana MukherjeeAn AI-Enhanced Web-Based Real-Time Analytics & Prediction Platform for ASIC Physical Design (PD) FlowsAuthorsSubhash UppalaAnoop SinghAyan DattaManjunath NayakSigma Profiling: Profiling Solution for Power Integrity SignoffAuthorsGirish DeshpandeAnusha VemuriVishal MalikEmmanuel ChaoSantosh SantoshChidambaram RakkappanAyush SoodTapas GovindrajuA Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance NodesAuthorsPramod Gayakwadsanthosh kamatamKhushboo RathoreRajesh KothaAgile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO TapeoutsAuthorsRuosi FengAadvivian SinghJonathan ElmhurstRishi AnandLLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral CircuitsAuthorsSoyoon ChoiChansol HongJinyoung LeeHyojin ChoiOvercoming Accuracy and Scalability Limits in Multi-Port On-Chip Electromagnetic Simulation Using a Hybrid Partial Elements Equivalent Circuit SolverAuthorsAbishek ManianSonam SadhukhanGarth SundbergKelly Damalou
