Session

DescriptionThis session presents shift‑left hardware security techniques for exposing vulnerabilities before tapeout, with a focus on side-channel leakage in cryptographic IPs and edge systems. The topics cover simulation-based and ML‑assisted analysis to detect power, timing, and analog anomalies in designs. They also present lightweight architectural defenses for securing off-chip interfaces. Together, these works show how integrating security analysis early in the design flow reduces risk in silicon design oriented towards edge AI and embedded hardware.