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Engineering Presentation
: IP Design for Mixed-signal and High-speed SoCs
Session Chair
Nanditha Rao
IBM
DescriptionThis session presents scalable, signoff-driven methodologies for designing and validating IPs in analog computing, mixed-signal verification, high-speed serial interfaces, and custom digital blocks. The topics cover programmable and synthesizable analog optimization IP, automated analog model generation, formal verification for protocol correctness, power-integrity analysis for large SerDes designs, and architectures for multi-domain SoCs. Together, these works demonstrate how automation, scalability, and verification enable reliable IP development from early design through sign-off.

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Event Type
Engineering Presentation
TimeTuesday, July 2810:30am - 12:00pm PDT
LocationSeaside Ballroom B
Topics
Design
EDA
Systems
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