Session
AI-Accelerated IP Libraries: From Optimization to Signoff
Session Chair
DescriptionThis session presents an end-to-end view of how AI/ML techniques are influencing standard-cell and memory IP development. The topics cover AI-driven circuit optimization, from transistor-level cell sizing and memory tuning, to adaptive, high-sigma verification methodologies, characterization flows and automate frameworks that ensure signoff-quality. These works demonstrate how AI enables gains in power, performance, area and model reliability while reducing turnaround time in modern SoC design flows.
Event Type
Engineering Presentation
TimeMonday, July 271:30pm - 3:00pm PDT
LocationSeaside Ballroom B
AI
Design
EDA
Presentations
| 1:30pm - 1:45pm PDT | Optimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level Sizing | |
| 1:45pm - 2:00pm PDT | Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification | |
| 2:00pm - 2:15pm PDT | Leveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.ai | |
| 2:15pm - 2:30pm PDT | Advanced Hard IP Integration Requirement Extraction and Checker | |
| 2:30pm - 2:45pm PDT | A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck | |
| 2:45pm - 3:00pm PDT | Automated Validation of Liberty Models |