Session
Beyond the Block: Verifying complex systems in context
Session Chair
DescriptionAs modern chips evolve into highly integrated systems combining hardware, software, security, and heterogeneous compute clusters, verification must expand beyond block-level correctness. Robust validation now demands coordinated simulation, emulation, prototyping, and HW/SW co-verification strategies to ensure full-system integrity under diverse workloads. Join us in learning about some of the latest techniques to address this, and discover how to confidently verify the integrated systems of the future.
Event Type
Engineering Presentation
TimeWednesday, July 291:30pm - 3:00pm PDT
LocationSeaside Ballroom A
EDA
Systems
Presentations
| 1:30pm - 1:45pm PDT | Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation | |
| 1:45pm - 2:00pm PDT | Staged Snapshots for Firmware-Hardware Collaborative Debug | |
| 2:00pm - 2:15pm PDT | Morph-Inspect: Structural Assurance for Inserted Logic | |
| 2:15pm - 2:30pm PDT | Automated System for FPGA-Based SoC Prototyping | |
| 2:30pm - 2:45pm PDT | Scalable, Emulation-Friendly,co-Simulation Testbench for Exhaustive RISC-V Cluster Configuration Verification | |
| 2:45pm - 3:00pm PDT | Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks |