Session
Precision in Practice: Advanced verification techniques for modern silicon
Session Chair
DescriptionJoin us to explore practical, high-impact verification strategies designed to keep pace with the growing scale and complexity of modern silicon. Verification teams must adopt more precise, scalable, and intelligent methodologies, spanning the journey from architectural intent to silicon-ready implementation.
Event Type
Engineering Presentation
TimeMonday, July 2710:30am - 12:00pm PDT
LocationSeaside Ballroom A
EDA
Presentations
| 10:30am - 10:45am PDT | Progress-Based Timeout Debug for Scalable SoC Verification | |
| 10:45am - 11:00am PDT | UVM-MS: A Novel Approach to Mixed-Signal IP Verification | |
| 11:00am - 11:15am PDT | STEER: Simulation of Templates Engine for Efficient Resource Usage | |
| 11:15am - 11:30am PDT | Building an Ontology-Driven Knowledge Graph for Constraint-Aware Navigation of Semiconductor Design Documents | |
| 11:30am - 11:45am PDT | Architectural Coverage Analysis and ML-Based Automated-Test Generation | |
| 11:45am - 12:00pm PDT | DFT Ready Design with SCO Canvas : Shift Left of DFT Designs |