Session <Full Program · Contributors · Organizations · Search Program · Flagged · My Recommendations · Happening NowMore…Search ProgramFlaggedMy RecommendationsHappening NowEngineering Poster: Engineering Poster Session OneEvent TypeEngineering PosterTimeMonday, July 275:00pm - 6:00pm PDTLocationDAC Pavilion, Exhibit FloorTopicsAIChipletDesignEDAQuantumSecuritySystemsSimilar SessionsSystem & Software DesignAI-Accelerated IP Libraries: From Optimization to SignoffRM Poster Session ThreePresentationsPss–enabled Design Space Exploration for Energy Management SystemsAuthorsAlicia StrangZiqiang WangRisk Analysis for Chiplets, and Security ArchitectureAuthorsSylvain GuilleyKazuki MontaAdvanced Automation for DC Die Generation and VerificationAuthorsBen ThomasTim DavisEnabling Time-Aware Systems Across Silicon-System BoundaryAuthorsXiangye WeiLiming XiuNext-Generation 3DIC STCO: AI-Enabled PPA and Cost Optimization Through IEEE P3537 3DbloxAuthorsYi-Wei ChenChung-Ching PengVivek RajanXukang WuXiaohu XuSonia BeghumKeshava ManimundaImproving Software Libraries Used as Safety Diagnostics for DSPs with DCLS, in Next-Gen Battery Management Systems, to Achieve ASIL-DAuthorsJon GoldfinchAnders ConveryMadhu BabuRoss BallanySesha Sai Kumar C VJamil R MazzawiTransforming Linux Drivers for Pre-Silicon Verification and Emulation Using Systemverilog DPI-CAuthorSuchir GuptaPre-Silicon Real Workloads Validation: Integration of Wireless Network Testers and Hardware Emulation via VirtualizationAuthorsKyuho SHIMKwangseok SeoWooyoung NohHyundon KimYOUNGSIK KIMImplementing Secure Boot, Attestation and Secure Storage in Systems in PackageAuthorsJunie UmSylvain GuilleyResearch on Warpage Simulation Fitting, Stress Simulation Method and Glass Substrate Application of Advanced Package for AI ChipsAuthorsChaoyu JingYu ZouZhimin XuZhenze HanSilicon Correlation of Voltage Droop Mitigation SchemeAuthorsBasavaraj KanthiSharayu KulkarniSanjeev JahagirdarGurupada MandalDesign Rule Checking for Rigid-Flex PCBAuthorsKirti SikriK ManimaranB G R RaoJames DonleyEnhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature UniformityAuthorsYuan ChenMingyang Liuyu tianRunjian WangYue Henghengzhi huYi ChenMin CaiLong KongRan Zhanghaixun lianAutomated 3Dblox File Generation: Enabling Extremely Rapid Solution Exploration by Streamlining Thermal and IR Analysis of 3D SOICsAuthorsKazin BlacklowNitin NavaleSamer AkikiZach BaldwinAgentic Time-Travel Debugging for HLS CodeAuthorsChris Croft-WhiteGreg LawJonathan Bonsor-MatthewsPipeline-Based Denial of Service Attacks on Embedded RISC-V Core-Based SystemsAuthorsA Poorna ChandraAarya PAditya NAshutosh SakrahalliSurinder SoodViraj RawalA Security-Centric Virtual Platform for Accelerating Shift-Left Security Firmware DevelopmentAuthorsJong Seong ParkKyungSoo KangAn Engineering Case Study of Autonomous AI PCB Layout Under Real Manufacturing and System Integration ConstraintsAuthorsBen JordanAmit BahlDarin ten BruggencateUnifying Pre- and Post-Silicon Software Validation Through ModelingAuthorsHojin JoSanghyeon ShinHyunjae WooYoungsik KimSLURM Deployment for IC Design Startups. How to Make the Most of Slurm, and Avoid Common IssuesAuthorsRiad KacedMugurel StancuJason RedgraveSolving Memory Subsystem Verification Challenges for Multi-Instance DesignsAuthorsManish ChandShyam SharmaAdvancing CDC Formal Verification in Low-Power SoCs Using Power Intent and Smart Waiver TechniquesAuthorsDavid VincenzoniErik SeligmanGreg MilanoRan ZhaoMulti-Tiered Physical-Aware Formal: Ensuring Latency-Robustness in Power Management Architecture and DesignAuthorsShashwat SinghSireesha TulluriBharath GottumukkalaSini BalakrishnanPandithurai SangaiyahDesign-for-FV Approach on a RISC-V Memory Page WalkerAuthorsHao XueGavriel GavrielovThe New Era of Digital Verification: a Revolution Driven by Agentic AI AccelerationAuthorsEdoardo BolleaDavide SanalitroWilliam WangTorin SchlunkLiberty-Based Profiling for IP BenchmarkingAuthorssanthosh kamatamKhushboo RathorePramod GayakwadAjay KumarRay ValenciaOoB Generator: A Novel Method to Improve the Productivity of RTL-to-Layout Using PythonAuthorsLuca PulvirentiLuca Francesco PerroniMario BlangifortiMichele BattistaSHELL: AI-Driven UVM FrameworkAuthorsJaehyeok LeeWonyeong SoSungmin HongAdvanced Hard IP Integration Requirement Extraction and CheckerAuthorsMili K JohnsonBen ThomasKavithaa RajagopalanPankaj TalwarInnovative Multiplatform Framework Boosting 10BaseT Ethernet Verification for Next-Gen Automotive SoCsAuthorsbipul halderAsjad FahmiSAHANA SKrunal PatelArchana AryaCentral DMA IP Verification Using Layered UVM ScoreboardAuthorJagadish RongaliUCIe-A 64GT/s High Speed Integrated Design and SI/PI Comparison of CoWoS-S/L/RAuthorsSheng-Fan YangLiang-Kai ChenWei-Cheng LinChih-Chiang HungMing-Chih LinHandling Timing Loops Across Non-Resettable Flops in a Synchronous Resets Design: An Innovative TechniqueAuthorRohit Kumar SinhaMatching Constraint Driven Synchronous Array Implementation for High-Performance ADCsAuthorsAkshita BansalNisha RanaRajeev SinghAkanksha JainInvariant-Driven Contract-Based Formal Verification for Scalable Compositional ProofsAuthorsurinder soodMulti-Agent Automated Formal Verification for Automative ApplicationsAuthorsVaibhav KumarEkansh BhatnagarA Novel Automated Methodology Python Driven for Test Coverage Improvement via Fault Injection and SimulationAuthorsMario BlangifortiLuca Francesco PerroniLuca PulvirentiAI-Enabled High-Fidelity Power Amplifier Behavioral Modeling with Commercial EDA ToolsAuthorsLei LiYanhua CuiTong LiZiquan BaiFei CaoBridging Hardware-Software Abstraction In UVM VerificationAuthorsBhaskar VedulaChandrakanth BetageriAdaptive Multi-Agent Framework for Automated Constraint GenerationAuthorsShez MalikPadma Priya SankarSrikar TallapragadaUsing Arm Native Acceleration with VLAB Virtual PlatformsAuthorsAtanas ParashkevovJeremy WaznyComprehensive Physical Verification Approach for Heterogeneous 2.5/3D IntegrationAuthorsNagaMalleswari MetlaRavali PagidoojuKalyanaKumar AmruthuluriArman DavtyanSara KhalafBaher El SayedA Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-Die InterconnectAuthorsDr. Tim Wang LeeHeeSoo LeeOrlando BellScalable Hierarchical EMIR Analysis Using Multi Layered Abstraction for Reticle-Scale Data Centre SOCsAuthorsudayakumar yedakuppamKarthik MTharun kumar KakarlaSrinivasa BillaAdvancing Silicon Lifecycle Management with Embedded TraceAuthorsVivek ChickermaneMarcel ZakMat O'DonnellAdaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-NetworksAuthorsHyungtae ParkRira OhSanggu KimHyunjae WooYoungsik KimEnabling PSS-Driven Early SoC Verification By Enriching IP-XACT InformationAuthorsKangho LeeYejin LeeMoonki JangYonghyun YangYoungchan LeeWoojoo KimSun-il RoeYoungsik KimAI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA OptimizationAuthorsYi-Wei ChenChung-Ching PengVivek RajanChia-Yi LiouChih-Hsiang YangKurt ChuKuan-Ting KuoXukang WuXiaohu XuSonia BeghumKeshava ManimundaA Unified QA Framework for Intel Library Validation Using Siemens Solido CrosscheckAuthorsSiddhant Paresh JapeKohinoor BasuGuang YongSIDDHARTH RAVIKUMARAutomated Verification and Performance Analysis for ChipletsAuthorsJoshua LamBatu BayramLeveraging AI/ML Techniques for Memory Circuit Performance Optimization: Insights from ASO.aiAuthorsAshish KumarShashank GuptaRakesh ShenoyAtul BhargavaA Soft-Microcode Engine to Power the Next Wave of Edge IntelligenceAuthorStefan BlixtEnabling Automated Software Testing in Emulation Environments via Fastboot Virtualization and On-Premises LLM-Based Failure AnalysisAuthorsHaemin ParkHwansung ParkKyoungmin ParkHyundon KimYoungsik KimOptimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level SizingAuthorsPhilippe HuratArthur BecerrilParis DouadyAlexandre BlampeyA Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die ArchitecturesAuthorsSumanth SuraneniNikhil JayakumarSujyesh Aanandh ManjunthanEnabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power ModelingAuthorsAakrati JainSujyesh Aanandh ManjunthanCheng ChiDFT Ready Design with SCO Canvas : Shift Left of DFT DesignsAuthorHoyeon JeonSTEER: Simulation of Templates Engine for Efficient Resource UsageAuthorsMelchizedek DasDevleena GhoshKetul PatelArun JosephArvind HaranAutomated Validation of Liberty ModelsAuthorsPramod Gayakwadsanthosh kamatamKhushboo RathoreRoopa MalakannavarTarakeshwar Goud DMerin MeynGaurav DhawanA Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI ApplicationsAuthorsZakir HussainMahesh DhanekulaAhmed AbdellatifAnushruti JaiswalShreya SashiYuming TaoSathish RNaveen BScalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP FlowAuthorsNagaraj ShiraliNitin NakirekantiJohn SweeneyMark WestvoldUVM-MS: A Novel Approach to Mixed-Signal IP VerificationAuthorsPritam PanigrahiAadhar SharmaKumar SinghShivam GuptaAadhar SharmaShifting System-Level Verification Left with Firmware-Driven ExecutionAuthorsYoona LhimYungi UmSungtae KangJihyun JangYoungsik KimOptimizing Reliability EM Sign-Off for 2nm Mobile SoCsAuthorsSmaritha KasukurthiSandhya ChandrashekharMathew KaipanatuSimon KuAmit MaratheEarly Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical DesignAuthorsJason CropSujyesh Aanandh ManjunthanAnalysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous IntegrationAuthorsJiwoo HongYumi LeeYelim LeeSeongjin MunAaeseul SeoYounghoe CheonJinwon KimJungyun ChoiSubrata NandyAdvanced Hard IP Integration Requirement Extraction and CheckerAuthorsMili JohnsonBen ThomasKavithaa RajagopalanPankaj TalwarAccelerating RTL and Verification Development via Automated Visual-to-Executable Specification GenerationAuthorsTejas DalalJeevan NatarajuGiridhar SGarima SrivastavaA Service-Aware Energy-Efficient DVFS Framework for System-on-Chip ArchitecturesAuthorsPriyal ThakkarShrinithi TensinghPrasad DandraThejeswara ReddyTushar VrindProgress-Based Timeout Debug for Scalable SoC VerificationAuthorsVikash KumarYunus AkhtarEfficient IR-Aware Powergrid OptimizationAuthorsPriyanka GawandeRishabh SinghSubhadeep GhoshRuchin GuptaHarshit PratikSharath C RRohit SomwanshiAdaptive AI and Additive AI Techniques for High-Sigma Standard Cell VerificationAuthorsInhyeok HwangInguk MinByungsu KimSungyoun LeeMohamed AtouaDesign Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCsAuthorsManmeet SinghSachin KalraAteet MishraKanhaiya MishraShubham AgarwalTanisha SinghBuilding an Ontology-Driven Knowledge Graph for Constraint-Aware Navigation of Semiconductor Design DocumentsAuthorsJongwoo RyuJungSub KohSungsu KimMinYoung ChoDongKyu KimYoungsik KimArchitectural Coverage Analysis and ML-Based Automated-Test GenerationAuthorsBryan HickersonArvind HaranTuhin MahmudManoj DusanapudiPhysical Signoff at Scale: Tackling TSV, Interposer, and ESD in 3DIC SystemsAuthorsMohannad AlshawiQi WangFirst-Time-Right Power Analysis: Data-Driven Test Selection Through Real-Time Validation of Clocks, Gating and Traffic-Dependent MetricsAuthorVinoth SelvanA Method to Automate the Conversion of .def File into .save.io One to Speed up the BE Digital Flow in Analog-on-Top DesignsAuthorsLuca PulvirentiMario BlangifortiLuca Francesco PerroniMichele BattistaMulti Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN ModelAuthorsRikuu HasegawaKazuki MontaTakuya WadatsumiMakoto NagataTianze KanLang LinNorman ChangML-Based Sigma Av–aware Switch Cell OptimizationAuthorSungsu ByunBSPDN: A Power Delivery Architecture for 19.8% Core Power Reduction and 9.3C Thermal Mitigation in Next-Generation AI ProcessorsAuthorsDean HuangJim YangJun LuEfficient Electromagnetic Extraction of Superconducting Circuits Used with Quantum Computers and Rapid Single Flux Quantum DesignsAuthorGarth Sundberg3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous IntegrationAuthorsMingyang LiuYi ChenZhang JieChunming WangYue Hengyu tianLiangzhen LaiRodger Luozhenghao chuAI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor DesignAuthorsJeroen KustersNina ZhangMike LukNicholas CarraraTim VelasquezChris Chan
