Session
System & Software Design
Session Chair
DescriptionThis session highlights advanced high-level approaches for improving the design, verification, and optimization at the system level, involving both software, the software/hardware interface, and the hardware design itself. Novel problems and opportunities for optimization appear as we move from components and IP-blocks to systems. A central theme is the use of automation, machine learning, and standardized design abstractions to accelerate early development—from generating executable RTL and verification environments from high-level specifications to enabling early verification through enriched IP-XACT and PSS flows, as well as ML-driven design exploration such as die-size estimation and QoS optimization.
Event Type
Engineering Presentation
TimeMonday, July 2710:30am - 12:00pm PDT
LocationSeaside Ballroom B
AI
EDA
Systems
Presentations
| 10:30am - 10:48am PDT | Accelerating RTL and Verification Development via Automated Visual-to-Executable Specification Generation | |
| 10:48am - 11:06am PDT | Automated Verification and Performance Analysis for Chiplets | |
| 11:06am - 11:24am PDT | Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow | |
| 11:24am - 11:42am PDT | Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information | |
| 11:42am - 12:00pm PDT | Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs |
