Session

DescriptionAdvanced packaging technologies (2.5D, 3D IC, chiplets, fan-out, heterogeneous integration) are reshaping semiconductor integration, offering unprecedented improvements in performance, efficiency, and miniaturization. Test is a key challenge in advanced packaging due to limited physical access, exploding interconnct densities, mixed technologies, the need to ensure known good die, and the lack of standards. Test cost can be 30–50% of total manufacturing cost for advanced multi-die packages. The cost, reliability risks, and lack of visibility inside the package make test one of the biggest barriers to scalable chiplet and 3D IC adoption. This special session will spotlight test solutions for cutting-edge advanced packaging techniques, highlighting packaging architectures, industry test practices, and research breakthroughs. Speakers include experts from chip and package design (AMD), advanced foundry technology (TSMC), and academia.