Session

DescriptionLarge Language Models (LLMs) and agentic workflows are rapidly reshaping the silicon design stack—from specification-to-RTL and verification to algorithm/tool evolution and physical layout closure—by writing, reading, and refactoring code across RTL (Verilog/SystemVerilog), Python, KLayout macros, C/C++, and Tcl-based flows. This special session brings together leaders from academia and industry to present concrete advances and a forward-looking roadmap for making code-capable LLMs trustworthy, reproducible, and production-ready for chip design.
We begin with front-end design where LLMs generate RTL and SystemVerilog testbenches from specs, propose debug strategies, and perform PPA-aware refactoring. Building on the Comprehensive Verilog Design Problems (CVDP) benchmark, we show how rigorous, community-vetted evaluation reveals capability gaps and drives progress across models and agentic systems. We then outline a roadmap toward tool-using AI agents that act as automated EDA R&D software engineers—moving beyond expert users of tools to expert builders of tools—with documentation-grounded reasoning, literature-aware planning, and guarded code synthesis. Complementing this,
we present self-improving algorithmic infrastructure: an autonomous, correctness-gated framework that rewrites C/C++ solver code and optimizes scripts/flows in ABC, pointing to a new paradigm of closed-loop EDA tool evolution. On the path to manufacturability, we introduce a multimodal benchmark for DRC that fuses GDSII, compressed layout imagery, KLayout/Python scripts, and design rule metadata—enabling LLMs and agents to localize, explain, and emit repair edits and macros. Finally, we explore LLM-aided algorithm discovery for inverse design of superconducting qubits using the open SQuADDS dataset, demonstrating generalizable ML pipelines that bridge physical constraints and device geometries.