Session
Gladiator Arena - Poster Battle One
Event Type
Engineering Poster Gladiator
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
AI
Chiplet
Design
EDA
Quantum
Security
Systems
Presentations
| 5:00pm - 5:07pm PDT | Flexible & Scalable Network Modeling for AI/HPC Network Verification | |
| 5:15pm - 5:22pm PDT | An AI-Enhanced Web-Based Real-Time Analytics & Prediction Platform for ASIC Physical Design (PD) Flows | |
| 5:22pm - 5:30pm PDT | Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition | |
| 5:37pm - 5:45pm PDT | Outsmarting State Space Complexity Through Proven Reset Abstraction Stratergies | |
| 5:45pm - 5:52pm PDT | Accurate Full-Custom Thermal and EM Analysis for Advanced Nodes | |
| 5:52pm - 6:00pm PDT | A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs |
