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Session

Research Manuscript
:
Revolutionizing Synthesis Flows
DescriptionEmerging technologies, such as Large Language Models (LLMs), Reinforcement Learning (RL), and Superconducting Circuits, are reshaping hardware synthesis workflows. This session explores the cutting edge of Logic Synthesis and Physical Design, focused on three core themes: 1) AI and Machine Learning in EDA, 2) Advanced Optimization Techniques, and 3) Emerging and Specialized Hardware.
Event Type
Research Manuscript
TimeTuesday, July 283:30pm - 5:30pm PDT
LocationMtg Room 201B
Topics
EDA
Tracks
EDA5. RTL/Logic Level and High-level Synthesis
Presentations
3:30pm - 3:43pm PDTMappingevolve: LLM-Driven Code Evolution for Technology Mapping
3:43pm - 3:56pm PDTGearls: Generalizable Reinforcement Learning Framework for Logic Optimization via Policy Similarity Metric
3:56pm - 4:10pm PDTRL4HDL: Code Diversity Guided FPGA Logic Synthesis Compiler Testing Via Reinforcement Learning
4:10pm - 4:23pm PDTDelay-Constrained Area Optimisation Using SAT-Based Local Improvement
4:23pm - 4:36pm PDTTranssyn: Scalable, Area-Oriented Transistor Network Synthesis via Cut-Based Mapper with SAT-Based Refinement
4:36pm - 4:50pm PDTShared Logic Unleashed: Multiple-Node Boolean Optimization for Next-Gen Synthesis
4:50pm - 5:03pm PDTDynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs
5:03pm - 5:16pm PDTBident: Optical Logic Synthesis via Optimal Configuration of Binary-Combiner Trees
5:16pm - 5:30pm PDTDuplication-Aware Retiming and Cell Interface Redesign for Superconductor Circuit Minimization