Session

DescriptionEmerging device technologies and novel interconnect architectures are redefining performance, energy efficiency, and scalability across the computing stack. This session highlights breakthrough advances - from fault tolerant in memory computing and superconducting logic to photonic matrix engines - alongside major progress in interconnect fabrics, 3D integration, and CXL enabled memory hierarchies. Showcasing innovations such as error resilient analog ECC, CAM based distance engines, wafer scale sparse matrix accelerators, and DTCO for 3 nm CPUs, these works demonstrate a compelling fusion of advanced device physics and system level architecture. Together, they signal a shift toward heterogeneous, hyper connected, high efficiency computing platforms where memory, logic, and communication co evolve to meet the demands of AI and data centric workloads.