Session

DescriptionModern hardware verification is increasingly driven by artificial intelligence tightly coupled with high‑performance execution platforms. This session highlights advances in AI‑enabled verification, including generative model–based processor fuzzing for RISC‑V, coordinated CPU fuzzing, and reinforcement‑learning–guided test‑time ensembles. Large language models are explored for automating UVM construction and assertion‑guided protocol patching, reducing manual effort in testbench development and debug. These learning‑based techniques are integrated with scalable simulation, emulation, and FPGA‑accelerated infrastructures to maximize coverage and throughput. Together, the papers demonstrate how generative AI, RL, and LLMs are transforming verification workflows by enabling adaptive stimulus generation, intelligent repair, and autonomous validation at scale.