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Session

Research Manuscript
:
From SAT to IC3: Modern Proof Techniques for Hardware Correctness
DescriptionAdvances in proof-centric RTL verification are showcased across agentic reasoning, scalable SAT/IC3, and high-throughput equivalence and model checking. Topics include a reasoning-enhanced programming agent, parallel SAT solving, and IC3 optimizations that cut SAT effort per obligation, complemented by data-driven lemma generation. Scalable combinational equivalence checking is addressed via miter-aware LUT mapping, parallel sweeping-based scheduling, and factored-form sharing. The session also covers complementary approximate reachability, invariant-driven verification of RISC-V cryptography extensions, and tensor-centric verification for domain-specific accelerators - highlighting how better structure and parallelism improve robustness and throughput on large designs.
Event Type
Research Manuscript
TimeWednesday, July 2910:30am - 12:30pm PDT
LocationMtg Room 202AB
Topics
EDA
Tracks
EDA2. Design Verification and Validation
Presentations
10:30am - 10:42am PDTPRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
10:42am - 10:54am PDTPRS: An Efficient Parallel SAT Framework
10:54am - 11:06am PDTDropping Multiple Literals per SAT Call in IC3 Model Checking
11:06am - 11:18am PDTLegend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
11:18am - 11:30am PDTMiter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
11:30am - 11:42am PDTParallel Combinational Equivalence Checking via Sweeping-Based Task Scheduling
11:42am - 11:54am PDTParallel Combinational Equivalence Checking Through Factored Form Sharing
11:54am - 12:06pm PDTParallelizing Complementary Approximate Reachability
12:06pm - 12:18pm PDTLeveraging Invariants for Scalable Verification of RISC-V Cryptography Extensions
12:18pm - 12:30pm PDTVten: Tensor-Centric Verification Framework for Domain-Specific Accelerators