Session

DescriptionThis session presents recent advances that combine algorithmic innovations and AI-driven techniques to improve test effectiveness, manufacturing analysis, and system resilience across the silicon lifecycle. The papers in this session address diverse problems, including drift-resilient compensation for RRAM-based in-memory computing, diffusion-based analysis of long-tailed wafer defects, and operator-aware scheduling for fault-tolerant AI accelerators. Additional works focus on improving test efficiency through scan activity probability modeling for programmable low-power LBIST and ATPG-free self-supervised learning for test point insertion. Advances in lithographic SEM contour extraction and LLM-driven assertion generation with fault criticality evaluation further demonstrate the growing role of data-driven methods in validation and safety analysis.