Session

DescriptionAs AI workloads continue to diversify across graph learning, diffusion-based generation, visual computing, and large-scale neural inference, accelerator research is increasingly shaped by the need for both domain-specific optimization and more systematic hardware design methodologies. This session brings together work that spans specialized accelerators for heterogeneous graph neural networks, diffusion models, and Gaussian splatting, along with innovations in GPU microarchitecture, approximate arithmetic, numeric formats, and automated DNN accelerator generation. Several papers highlight algorithm-architecture co-design, showing how workload structure, temporal reuse, sparsity, and token reduction can be directly translated into hardware efficiency gains. Others focus on more general architectural foundations, including register-file coordination, low-power approximate multipliers, and flexible low-precision formats for emerging AI models. The session also includes work on end-to-end design automation, reflecting the growing importance of frameworks that can rapidly explore, generate, and map accelerators for a broad range of workloads and quantization schemes. Collectively, these papers illustrate the breadth of current AI hardware research, where both specialized acceleration techniques and scalable design methods are essential to meeting the performance, energy, and programmability demands of next-generation intelligent systems.