Session

DescriptionLarge language models and mixture-of-experts architectures are creating new demands on specialized hardware, driven by growing model size, irregular execution, tight memory capacity, and increasing pressure on bandwidth and energy efficiency. This session brings together recent advances that address these challenges across multiple layers of the hardware stack, including expert caching, adaptive and mixed-precision computation, activation approximation and compression, reconfigurable dataflow design, and near-memory acceleration. Several papers focus directly on efficient LLM and MoE inference, proposing new architectural support for expert selection, speculative decoding, asymmetric GEMM, and bandwidth-aware execution on emerging memory systems. Others contribute techniques that improve the efficiency of core operators and model components through distribution-aware activation design, binary-coded quantization, adaptive precision, and robust activation compression for training. Taken together, these works reflect the rapid maturation of workload-driven AI hardware design, where performance depends not only on raw compute throughput, but also on how effectively architectures manage sparsity, precision diversity, data movement, and dynamic execution behavior in modern foundation models.