Session

DescriptionThe relentless pursuit of performance and area scaling requires the EDA community to fundamentally rethink conventional placement paradigms. This session highlights transformative optimization approaches that break free from traditional 2D standard-cell constraints to address the "More than Moore" era. Attendees will discover pioneering research on true-3D and mixed-size analytical global placement for face-to-face 3D ICs, addressing the critical challenges of 3D timing closure and macro orientation. Furthermore, the session showcases novel methodologies that dive deeper into the layout hierarchy, featuring cell-structure-independent transistor-level placement. Alongside these architectural shifts, the session will feature state-of-the-art analytical engines that integrate reinforcement learning, differentiable timing-driven models, and IR-drop awareness to squeeze optimal power, performance, and area (PPA) out of next-generation layouts.