Session

DescriptionThis session explores the frontier of hardware acceleration, covering circuit-level advances such as adaptive MAC units, as well as specialized architectures such as reconfigurable systolic arrays and Ising-model-based optimization. We then examine the evolution of memory systems, featuring low-power SRAM subarrays and ECC integration for LPDDR6. This session further delves into system-level innovations, including ML-assisted analog calibration and cross-stage redundancy elimination for AIoT. From these talks, attendees will gain a comprehensive understanding of the cross-layer optimizations from circuits to software.