Session
Structuring the Blueprint: Scalable Partitioning and Early-Stage Floorplanning
DescriptionAs modern VLSI and PCB designs scale to unprecedented complexities, laying a robust foundational blueprint is more critical than ever. This session explores cutting-edge advancements in the earliest stages of physical design, focusing heavily on highly scalable hypergraph partitioning frameworks that leverage spectral projection, GPU acceleration, and memetic algorithms to efficiently handle massive component counts. Beyond partitioning, the presentations delve into innovative early-stage floorplanning and layout synthesis techniques that bridge the gap to physical implementation. Highlights include a differentiable shaping model for rectilinear soft modules, force-based module deformation for rapid design space exploration, and LLM-assisted modular PCB placement. Together, these works provide a comprehensive look at how next-generation tools are intelligently dividing, shaping, and structuring designs to enable seamless downstream implementation.
Event Type
Research Manuscript
TimeTuesday, July 283:30pm - 5:30pm PDT
LocationMtg Room 203AB
EDA
EDA7-II. Physical Design and Verification
Presentations
