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Research Manuscript
:
Memory That Thinks: Scalable, Reliable, and Secure Compute-in-Memory Systems
DescriptionThis session brings together cutting-edge advances in memory-centric computing for AI, spanning digital and analog compute-in-memory (CIM), CAM-based accelerators, and DRAM/NAND-enabled computation. The papers highlight cross-layer innovation, from device-aware modeling and design technology co-optimization (DTCO) all the way to hardware-algorithm co-design, while addressing critical challenges in reliability and security for edge intelligence.
Event Type
Research Manuscript
TimeMonday, July 2710:30am - 12:30pm PDT
LocationMtg Room 203AB
Topics
Design
Tracks
DES2A. In-memory and Near-memory Computing Circuits
Presentations
10:30am - 10:43am PDTS2CIM: A Secure-Computation and Secure-Storage Compute-in-Memory Architecture with Circuit-Algorithm Co-Design for Efficient and Trustworthy Edge Inference
10:43am - 10:56am PDTHYPER-CIM: Hierarchical Predictive Exploration and Realizable Design Flow for High-Efficient Digital CIM
10:56am - 11:10am PDTNoisexplore: A Device-Aware Hierarchical Noise Modeling and DTCO Framework for Analog In-Pixel Computing Architectures
11:10am - 11:23am PDTDIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing
11:23am - 11:36am PDTNASiC: 3D NAND-Based CAM-Selected Multibit CIM Architecture for Efficient On-Device Mixture-of-Experts LLM Inference
11:36am - 11:50am PDTKCD-CAM: A K-Nearest-Neighbor Accelerator Based on Charge-Domain Content-Addressable-Memory for Point Cloud Processing
11:50am - 12:03pm PDTProbabilistic Memory Design for Efficient Trustworthy Edge Intelligence
12:03pm - 12:16pm PDTREPAIR: Reliability Enhancement of NVM FPGAs Through Lifetime-Aware Differential Partial Reconfiguration
12:16pm - 12:30pm PDTDRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access