Session

DescriptionDescription: As post-quantum cryptography, confidential virtualization, and encrypted data processing move from theory to deployment, hardware platforms are becoming the decisive battleground for both leakage and resilience. This DAC session brings together foundational advances and sobering attacks that redefine how we design, verify, and protect next-generation secure systems by presenting methods for significantly reducing side-channel overhead, a modular RISC-V extension tailored for post-quantum cryptography, and AI-inspired architectural techniques that accelerate LPN-based primitives critical to PQC deployments. This session will also shed light on analytical, timing-aware pre-silicon leakage estimation, practical fault-injection attacks targeting FPGA logic synthesis tools, and AI-assisted threat-to-assertion learning to improve SoC security verification coverage. Furthermore, this session will present sparsity-aware optimizations for encrypted sparse matrix multiplication through hardware–software co-design, processing-in-memory acceleration to scale fully homomorphic encryption databases, and securely migrating workloads across heterogeneous trusted environments without breaking isolation guarantees.