Search Program

3D-DuRA: Accelerating Next-Resolution Generation via 3D Near/in-Memory Architecture with Dual-Ring Sparse Attention

Research Manuscript

12:16pm - 12:30pm PDT Tuesday, July 28 Mtg Room 203AB

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionVisual Autoregressive (VAR) model, via innovative next-resolution prediction, demonstrates significant potential of GPT-style AR models in image generation. However, due to its coarse-to-fine nature, the input token-map size grows dramatically with each step, resulting in excessive memory access and computational overhead. In this paper, we propose 3D-DuRA, an algorithm-architecture co-design based on a hybrid 3D near-memory and in-memory computing architecture equipped with dual-ring sparse attention, for efficient next-resolution visual-autoregressive generation. Experimental results demonstrate that our proposed 3D-DuRA achieves 4.1× improvement in area efficiency compared with RTX 6000 Ada GPU, along with 3.5× and 9.1× speedups and 10.1× and 13.1× improvements in energy efficiency on Infinity2B and VAR-d36, respectively.

People

Research Manuscript

3D-ReSAC: A Near-3D-Stacked-DRAM Processor with Area-Efficient Sequential Refresh-Skip and High-Link-Utilization Arrowmesh Communication for Fast Low-Batch LLM Inference

10:43am - 10:56am PDT Tuesday, July 28 Mtg Room 203AB

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionLow-batch LLM inference on edge hardware places stringent demands on both memory bandwidth and computational capacity. While 3D-stacked DRAM accelerators offer a promising solution, they introduce two critical overheads that are frequently under-optimized: DRAM refresh and collective communication.
To mitigate these issues, we propose 3D-ReSAC, a near-memory processor based on 3D-stacked DRAM, equipped with an area-efficient sequential refresh-skip method and high-link-utilization ArrowMesh communication.
Our evaluations show that 3D-ReSAC reduces refresh and communication overheads by 7–100% and 53–75%, respectively, leading to a 1.12× to 2.02× latency reduction across low-batch LLM inference workloads.

People

Engineering Poster Gladiator

3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration

5:17pm - 5:25pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

Description3DIC chiplet heterogeneous integration faces significant challenges in cross-die timing signoff due to the lack of unified 3D PDKs and the inability of conventional STA to account for jitter from TSV+HB arrays. This paper proposes a 3DEM-driven PDK-independent STA approach for reliable cross-die timing signoff. The approach constructs cross-die channels with die final-stage buffers and cross-die sections, integrating 3D EM modeling for S-parameter acquisition, SPICE simulation for total jitter analysis, R/C parameter back-annotation, and jitter incorporation as uncertainty into STA. A case study on 9-layer stacking (1GHz) shows that the proposed method enables transmission pattern optimization (reducing jitter from 230.74ps to 120.28ps and achieving timing closure), which is unattainable with conventional STA. This work facilitates reliable and flexible 3DIC chiplet heterogeneous integration.

People

Mingyang Liu

Hangzhou Zhicun (Witmem) Technology Co., Ltd.

Yi Chen

Hangzhou Zhicun (Witmem) Technology

Zhang Jie

Hangzhou Zhicun (Witmem) Technology

Chunming Wang

Witintech

Yue Heng

Hangzhou Zhicun (Witmem) Technology Co., Ltd.

yu tian

Beijing Zhicun (Witmem) Technology Co., Ltd

Work in Progress

A 1.31 TOPS/W CGRA Hardware with SIMD and Programmable Memory Address Generation Unit for Edge AI

6:57pm - 6:58pm PDT Monday, July 27 Exhibit Hall

DescriptionCoarse-Grained Reconfigurable Arrays (CGRA) offers a balance between a processor's flexibility and a domain-specific accelerator's high energy efficiency. However, conventional CGRAs typically employ some of its Processing Elements (PEs) to compute the addresses for memory access, resulting in lower hardware utilization during workload execution. In this work, we propose a CGRA featuring a dedicated Address Generation Unit (AGU) that directly generates addresses for PEs to fetch and send data, thereby achieving higher utilization. Our simulation results show that incorporating the AGU improves CGRA utilization by a factor of 2× when executing a 64x8 square General Matrix Multiplication (GeMM) workload. The proposed CGRA also supports Single-Instruction-Multiple-Data (SIMD) to accelerate operations while boosting energy efficiency up to 3.96×. Implemented in 12nm FinFET technology, our post-layout simulation demonstrates that the proposed design operates at 1 GHz and achieves an energy efficiency of 1.31TOPS/W, which is 3.4× better than the state-of-the-art.

People

Rakshith Harish

Institute of Microelectronics, Agency for Science, Technology and Research

Vishnu Nambiar

Institute of Microelectronics, Agency for Science, Technology and Research

Yuntian Liu

School of Electrical and Electronic Engineering, Nanyang Technological University

Yi Sheng Chong

Institute of Microelectronics, Agency for Science, Technology and Research

Wang Ling Goh

School of Electrical and Electronic Engineering, Nanyang Technological University

Rahul Dutta

Institute of Microelectronics, Agency for Science, Technology and Research

Anh Tuan Do

Institute of Microelectronics, Agency for Science, Technology and Research

Research Manuscript

A Boolean Processor-Based Hardware Emulation System with Reconfigurable Interconnects

4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionExisting Boolean processor-based (BP-based) hardware emulation systems typically rely on fixed interconnects, which often suffer from severe bandwidth underutilization under highly imbalanced traffic. We propose a BP-based hardware emulation system with hierarchical reconfigurable interconnects. At both the inter-chip and intra-chip levels, our system dynamically reallocates idle interconnect lanes from low-traffic pairs to high-demand pairs, alleviating communication bottlenecks and improving interconnect utilization without modifying the underlying ASIC fabric. The hardware is co-designed with the compiler, which profiles communication, generates per-lane configuration tables and scheduling strategies, and programs the interconnect via registers. Experimental results on industrial digital designs show up to 64% emulation performance improvement and an average 27% reduction in compilation time, with only 7.4% area overhead compared to a fixed-interconnect baseline system.

People

Engineering Poster

A Chip-Level DTCO Framework for Yield-Aware Back-End Design: Layout-Aware Misalignment Correction in DRAM

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionWe propose a chip-level, layout-aware DTCO framework to correct deterministic interlayer misalignment. Using layout-driven features and machine learning, the proposed approach achieves ~70% variation reduction, enables fast inline prediction, and improves yield on silicon-proven products.

People

HyeJin Kim

Samsung Electronics

SoYoung Kim

Sungkyunkwan University

Engineering Poster

A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAutomotive radar systems rely on highly linear FMCW chirp signals to ensure accurate distance and velocity measurements for ADAS applications. Deviations in chirp linearity can compromise radar performance and violate functional safety standards. This paper presents a compact, all-digital IP for real-time chirp linearity monitoring integrated within the radar transmitter subsystem. The proposed solution leverages zero-crossing alignment between the chirp signal and an on-chip reference clock to compute instantaneous frequency slope deviations without requiring dedicated high-frequency clocks. The architecture includes counters, edge overlap detection, and an error computation engine, demonstrates detection of minor deviations as low as 0.001% across a 10 μs chirp duration. Implemented entirely in digital logic, the IP is technology-independent, incurs less than 5% area overhead, and operates with any available on-chip clock source. This scalable, low-cost solution enhances radar transmitter reliability and supports compliance with automotive safety standards, making it ideal for integration into next-generation radar SoCs.

People

Research Manuscript

A Correlation-Aware GKP Decoder for Fault-Tolerant Continuous-Variable Photonic Quantum Computers

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 203AB

Design

Quantum

DES6. Quantum Computing

DescriptionThe Gottesman–Kitaev–Preskill (GKP) encoding is a promising approach for realizing fault-tolerant continuous-variable (CV) photonic quantum computers.
Recent studies have investigated various GKP decoding algorithms, among which correlation-aware methods that exploit inter-qubit correlations achieve significantly improved error-correction performance.
However, hardware implementation of GKP decoding remains largely unexplored.
Error decoding in CV photonic quantum computers must operate within tens of nanoseconds to match the optical clock frequency.
A straightforward hardware implementation of correlation-aware decoding introduces substantial computational latency due to its arithmetic complexity.
To address this challenge, this paper proposes a high-accuracy and low-latency accelerator architecture optimized for correlation-aware GKP decoding.
Logic synthesis using 7-nm FinFET technology demonstrates that our decoder can complete correlation-aware GKP decoding with in 12.96 ns.
In addition, comprehensive design space exploration is conducted to evaluate tradeoffs among decoding accuracy, latency, and circuit area, leading to design guidelines for future correlation-aware GKP decoder implementations.

People

Ryosuke Matsuo

The University of Tokyo

Junichiro Kadomoto

The University of Tokyo

Research Manuscript

A Differentiable Approach to Task Graph Partitioning: A Case Study in RTL Simulation

5:18pm - 5:30pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionGraph partitioning is essential for many EDA applications that leverage task graph parallelism for faster execution. For instance, RTL simulators partition an input RTL design into dependent tasks and schedule them across threads. However, existing partitioners are largely limited to general-purpose heuristics that overlook real threading costs, resulting in suboptimal performance. Consequently, we introduce DiffPart, a differentiable task graph partitioning framework that automatically learns high-quality partitions under real operating conditions. Applied to RTL simulation, DiffPart improves state-of-the-art Verilator's partitioning quality, delivering up to 1.22--55.25x faster simulation runtime across diverse designs.

People

Aditya Das Sarma

University of Wisconsin-Madison

Wan Luan Lee

University of Wisconsin-Madison

Shui Jiang

University of Wisconsin, Madison

Boyang Zhang

Tsung-Wei Huang

University of Wisconsin-Madison

Engineering Presentation

A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes Designs

11:15am - 11:30am PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionFor large-scale SerDes designs, dynamic power integrity sign-off is becoming increasingly challenging due to growing design scale and performance demands. Modern SerDes integrate analog blocks, digital blocks, sensitive clocks, decaps with complex Power Delivery Network (PDN) design. Such designs can reach tens of millions of transistors and multi-million-node as design nodes shrinking, making full-chip dynamic EMIR sign-off and Chip Power Model (CPM) generation difficult. In addition, data rates are scaling from 56G to 112G and 224G, leading to higher switching activity and larger transient current peaks. Accurate sign-off and CPM generation require smaller, picosecond-level time resolution and long transient windows of up to hundreds of nanoseconds, making sign-off runtime even longer.
In traditional power integrity analysis, existing EMIR tools have limited distributed scalability for full-chip, multi-domain SerDes designs. Realistic dynamic simulations often exhibit low parallel efficiency and inefficient utilization of computing resources, resulting in long runtime to days or even weeks. To reduce runtime and resource usage, designers have to downsize current vector capture window or simplify extracted networks, which impacts overall power integrity analysis accuracy. Moreover, past early analysis is typically limited to simple static analysis, while dynamic analysis and CPM generation can only be performed at the sign-off stage, making chip-package-system PDN co-optimization hard to process in early stage.
Here, we adopt a distributed and scalable dynamic power integrity flow from early analysis to sign-off. Early-stage dynamic power integrity analysis based on Build Quality Metric (BQM) provides early EMIR insight and enables early CPM generation for package- and system-level power integrity analysis, allowing issues to be addressed earlier and reducing sign-off iterations. Distributed and scalable dynamic EMIR sign-off flow enables efficient full-chip analysis under realistic workloads through multi-machine, multi-thread parallelism, without simplifying extracted networks or reducing analysis windows. With the unified dynamic power integrity flow from early analysis to sign-off, analysis efficiency is significantly improved while maintaining accuracy and increasing confidence in SerDes design robustness.
keywords：large-scale Serdes designs, distributed and scalable, dynamic power integrity, Chip Power Model

People

Xin Shu

Jinrong Yan

Hang Sun

Xuewei Ding

Xiaofan Lu

A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis

Work in Progress

6:52pm - 6:53pm PDT Monday, July 27 Exhibit Hall

DescriptionClock meshes are an essential technique in high-performance VLSI systems to minimize skew and handle On-Chip Variation (OCV) especially in nanometer technologies. However, analyzing meshes is difficult due to reconvergent paths and multi-source drivers. The industrial standard is to use SPICE simulations since static timing analysis (STA) tools can not handle mesh loops. SPICE simulations are accurate but slow, and approximate models miss critical effects like input slew and input skew. In this work, we propose a Graph Neural Network surrogate model of the clock mesh represented as a graph with augmented structural and physical features. Trained on SPICE data, our model achieves high accuracy with average delay error of 1.70ps on unseen real designs versus 87.30ps from prior approximate models, while achieving speed-ups up to 3900x over multi-threaded SPICE simulation enabling faster and accurate analysis for clock meshes. Furthermore, we demonstrate the adaptability of our model through transfer learning and use it for OCV analysis.

People

Muhammad Hadir Khan

Matthew Guthaus

A Fully Analog Continuous-Time CIM Neural ODE Solver for Flow-Matching-Based Fluid Dynamics Generation

Research Manuscript

10:30am - 10:45am PDT Wednesday, July 29 Mtg Room 203AB

Design

DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionThe generation of fluid-dynamics fields is essential for understanding complex nonlinear systems and enabling real-time scientific computing. Conventional computational fluid dynamics pipelines rely on finite-element or finite-volume solvers on von Neumann architectures, which discretize continuous physical evolution into many iterative updates, leading to prohibitive latency and energy consumption. Inspired by neural dynamical systems in the brain, we propose a biologically inspired continuous-time hardware–software co-design framework for flow-matching–based turbulent-flow generation. (1) The flow-matching model adopts an MLP-Mixer architecture that emulates cortical-style information integration and hierarchical signal mixing, providing a compact backbone that naturally aligns with closed-loop analog computation. (2) A fully analog continuous-time RRAM CIM neural ordinary differential equation (ODE) solver is developed to physically realize neural-like continuous-time latent dynamics, enabling high-speed and low-power flow generation. (3) Noise-aware training and decoder retraining are jointly introduced to ensure robust generation quality in the presence of RRAM read/write noise. Experiments on three turbulent-flow datasets show that the MLP-Mixer backbone matches convolutional and attention-based flow-matching models in velocity-field accuracy while mapping efficiently to CIM hardware, and that the proposed analog ODE solver reduces energy consumption by 98.24% and latency by 99.99% compared with an NVIDIA A100 GPU, while maintaining stable generation fidelity under realistic RRAM read/write noise. This work establishes a new paradigm for high-speed, energy-efficient physical process generation and scientific AI acceleration using neuromorphic continuous-time CIM computing.

People

Songqi Wang

The university of Hong Kong

Meng Xu

Jichang Yang

Zhexu Chen

Hegan Chen

The university of Hong Kong

Sishuo Liu

Xinyuan Zhang

Kwun Hang WONG

Ning Lin

Yi Li

Southern University of Science and Technology

Zhongrui Wang

Han Wang

A Hamiltonian-Guided Pre-Trainer for Variational Quantum Algorithms

Research Manuscript

2:34pm - 2:47pm PDT Wednesday, July 29 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionThe optimization of variational quantum algorithms (VQAs) is notoriously challenging due to poor parameter initialization, which often traps optimizers in suboptimal local minima. Existing methods rely on a static guessing paradigm that is fundamentally limited. This paper presents a Hamiltonian-guided pre-trainer (HGP), a new approach that dynamically constructs a better starting point. HGP iteratively refines parameters by performing exact global optimization within low-dimensional subspaces. These subspaces are identified using a Hamiltonian-guided parameter blocking strategy, and the optimization is achieved by reconstructing the analytic landscape from a few quantum measurements via a Fast Fourier Transform. We evaluated HGP on canonical spin models, where it consistently produced superior starting points for standard optimizers. Ablation studies reveal Hamiltonian-guided parameter blocking reduces the initial energy error by nearly 30-fold versus the next best benchmark. These results highlight the importance of Hamiltonian guided pre-training for enhancing VQA performance.

People

Engineering Presentation

A Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI Applications

4:00pm - 4:15pm PDT Monday, July 27 Seaside Ballroom A

EDA

Systems

DescriptionAs AI, machine learning, and cloud workloads scale, interconnects must deliver higher bandwidth and lower latency without compromising system-level power integrity and PDN robustness. Massive parallel compute leads to high transient current demand, fast di/dt switching, and increased simultaneous switching noise, causing traditional PDN assumptions to break down at the system level.

A scalable system-level PI simulation flow is key to balancing accuracy and turnaround time for large, high-performance product designs under aggressive go-to-market timelines. This work presents a virtual validation framework for system-level power integrity sign-off analysis, including die, package, and PCB. It enables engineers to identify anomalously high impedance responses in the system; excessive transient voltage drops and elevated current ripples at each interface (per bump) of the system.
This approach helps to correct the design before tape-out, helping to avoid costly redesign cycles and potential product failures.

People

Engineering Poster

A Hybrid Simulation and Formal Verification Approach for Exhaustive Interrupt and Status Flag Verification

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionVerification of status flags and interrupts is critical for correct interaction between IP components, yet exhaustive validation of interrupt behavior remains challenging when relying solely on simulation-based approaches. This approach presents a hybrid simulation and formal verification methodology for interrupt and status flag verification using an interrupt Verification IP (VIP) and demonstrates its application on a Real-Time Clock (RTC) IP. Simulation-based verification is used to validate interrupt behavior under realistic programming scenarios, while formal verification is leveraged to exhaustively prove interrupt properties and corner cases that are difficult to cover in simulation. The results highlight the effectiveness of combining dynamic and formal verification through a reusable interrupt verification infrastructure to improve confidence in interrupt correctness at the IP level.

People

Engineering Poster Gladiator

A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs

5:52pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionPower consumption plays a key factor in SoC. With advances made in wireless technologies through 3GPP LTE & NR, IEEE Wifi and now with 3GPP 6G, there is a need for advanced architecture in SoC. Typically, a SoC uses sleep and wakeup (warmboot) procedure for saving battery. The warmboot procedure involves changing DRAM from refresh mode to active mode. This takes certain time until which other operations get delayed. Also usage of DRAM further consumes power. Hence, hardware design that enables software to have systematic control on wakeup (warmboot) and sleep operations is required. This idea discusses on design of SoC to use hybrid mode of SRAM and DRAM. SRAM and DRAM are memory entities which play a key role in wakeup, software execution and sleep. With combination of software control on proposed hardware design for system-on-chip, can efficiently increase sleep time by minimizing DRAM usage and wakeup time by managing with SRAM along with faster execution of procedures required during wakeup.

People

Venkata Raju Indukuri

Research Manuscript

A Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation

2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionAs integrated circuit (IC) designs grow increasingly complex and transistor counts per chip exceed ten billion, post-layout SPICE simulations involve large-scale sparse linear systems, severely degrading simulation efficiency
Current GPU acceleration methods, despite their promise, struggle with efficient load balancing and resource utilization, which restricts their effectiveness in ultra-large-scale circuit simulations.
In this paper, we propose a levelized load-balanced and structure-adaptive LU factorization framework for GPU-based circuit simulation.
Our method improves resource utilization and parallel efficiency by introducing computation-balanced dependency level partitioning, adaptive resource allocation, and a hybrid matrix indexing mechanism.
These strategies ensure that both the memory and computational resources of the GPU are fully leveraged.
We demonstrate significant acceleration over existing methods, achieving a 2.1X speedup compared to GLU3.0 and a 5.2X speedup over 16-thread PARDISO on circuit sparse matrices ranging from thousands to millions of dimensions.
Additionally, our framework has been successfully integrated into the open-source SPICE simulator Ngspice, accelerating circuit simulations with promising results and showcasing its potential for large-scale IC design verification.

People

National Center of Technology Innovation for EDA

Research Manuscript

A Locality-Aware Temporal Motif Mining Accelerator with Chunk-Based Search Tree Expansion

1:55pm - 2:08pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES3. Emerging Models of Computation

DescriptionMining temporal motifs in temporal graphs is essential for many critical applications. Despite several software/hardware temporal motif mining solutions have been proposed, they still suffer from substantial redundant and irregular off-chip communications due to misaligned search tree expansions across different motif matching tasks. In this work, we observe that different tasks traverse the same temporal graph edges in strict chronological order, exhibiting strong data locality among these tasks. Motivated by this insight, we propose LTMiner, a locality-aware hardware accelerator designed to efficiently handle temporal motif mining. Specifically, LTMiner proposes a novel chunk-based search tree expansion mechanism into the accelerator design to align the graph traversals of different tasks at the granularity of data chunks, substantially boosting the data locality among these tasks for lower data access cost. The results show that LTMiner gains 1.1×–652.6×, 1.8×–70.3× speedups and 3.9×–2050.9×, 1.2×–17.3× energy savings compared to the cutting-edge software and hardware solutions, respectively.

People

Yinbo Hou

Hao Qi

Jin Zhao

Yu Zhang

Yiling Lu

Hong Kong University of Science and Technology (HKUST)

Hui Yu

longlong lin

Southwest University

Wenbin Jiang

Xiaofei Liao

Hai Jin

A Method to Automate the Conversion of .def File into .save.io One to Speed up the BE Digital Flow in Analog-on-Top Designs

Engineering Poster Gladiator

5:42pm - 5:51pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIn analog-on-top design flows, ensuring pin position and ordering constraints from the analog layout team is critical for the Place & Route of digital IP blocks. Traditionally, digital layout engineers manually convert DEF files, which describe physical layout and pin information, into .save.io files required by Innovus. This manual editing is time-consuming, error-prone, and must be repeated frequently due to evolving constraints. We present "IO Generator," a Python-based tool that automates the conversion of DEF files into the .save.io format, significantly accelerating the backend digital flow. The tool accurately assigns pins to floorplan sides and computes offsets and skips based on LEF-defined pitch and width parameters. It includes robust error checking to ensure pin alignment and offers two modes: pin extraction for file generation and pin comparison for mismatch reporting between DEF and netlist files. With a user-friendly GUI and command-line interface, IO Generator reduces manual effort from hours to seconds, minimizes errors, and integrates seamlessly into existing flows. IO Generator has been successfully adopted across multiple projects, proving its effectiveness and versatility in modern analog-on-top digital design flows.

People

Luca Francesco Perroni

Michele Battista

A Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-Die Interconnect

Engineering Presentation

11:00am - 11:15am PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionThe rapid growth of AI and machine-learning workloads has driven adoption of advanced packaging technologies such as silicon interposers, bridges, and heterogeneous 3D integration in chiplet-based systems. These structures often require patterned ground planes, such as hatched or meshed geometries, to meet manufacturability and reliability constraints. However, these geometries introduce significant challenges for signal and power integrity analysis due to impedance variation, increased loss, resonances, and crosstalk.
This paper presents a practical mixed-domain interconnect modeling approach that combines specialized quasi-static 2D field solvers with full-wave Finite Element Method (FEM) solvers to efficiently analyze hatched ground planes in advanced interconnects. The proposed approach is designed to integrate into back-end interconnect simulation flows, balancing modeling accuracy with scalability suitable for design iteration and signoff.
Two test vehicles, a UCIe 2.0–based silicon bridge and a mobile flex PCB, are fabricated, simulated, and correlated against measured data. The results demonstrate strong agreement with measurements while improving modeling efficiency compared to standalone 3D EM analysis, enabling more reliable interconnect analysis and faster design turnaround for advanced packaging implementations.

People

Dr. Tim Wang Lee

HeeSoo Lee

A Novel Automated Methodology Python Driven for Test Coverage Improvement via Fault Injection and Simulation

Orlando Bell

Giga Design Automation

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe increasing complexity of digital circuits and stringent functional safety standards, such as ISO 26262 and IEC 61508, require test coverage levels above 99%, which often leads to significant area overhead due to traditional Design For Testability (DFT) techniques. This work presents a novel automated methodology, driven by a Python script, that combines ATPG patterns generated by TestMAX ATPG with functional fault simulation run using VC_Z01X to significantly improve test coverage without additional area overhead. The methodology was validated on a STMicroelectronics' synchronous step-down regulator, showing coverage improvements from 78.87% to 92.90% in full-scan configuration and from 42.09% to 84.25% in partial-scan mode, while drastically reducing ATPG untestable faults. The automated flow leverages the existing functional testbench, enhancing verification efficiency and repeatability. This approach advances the trade-off between achieving high test coverage and minimizing area impact, offering valuable benefits for safety-critical applications and designs with strict area constraints.

People

Mario Blangiforti

Luca Francesco Perroni

Luca Pulvirenti

A Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive Applications

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionWith the ongoing advancement of automotive intelligence, vehicles are incorporating an increasing number of semiconductor chips to improve efficiency and functionality. This technological progression results in elevated current levels across automotive systems, leading to two key physical challenges: electromagnetic compatibility (EMC) and thermal management. Properly managing these factors is crucial for ensuring system stability and reliability.

However, simultaneously addressing EMC and thermal effects is complex, as their respective physical impacts and design requirements are often conflicting. This complexity extends the design cycle needed to achieve a suitable balance between EMC and thermal considerations that meets chip specifications. To address this challenge, Denso and Siemens EDA have partnered to develop an automated optimization workflow by integrating Siemens' Solido Simulation Suite, HEEDS, and FLOEFD. This approach efficiently determines optimal design solutions for both EMC and thermal performance.

Utilizing this innovative workflow can reduce design timelines by up to 68% and decrease physical area requirements by as much as 20%. These improvements significantly accelerate time-to-market and lower costs associated with circuit design for automotive applications.

People

Engineering Poster

A Novel Methodology for Automated LVS Rule Deck Verification: Truth Table and Device Extraction Qualification

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern semiconductor fabrication faces an escalating verification challenge as technology nodes shrink to 3nm and beyond, where Layout Versus Schematic (LVS) verification complexity has grown exponentially. Today's LVS must go beyond comparing Schematic and Layout designs; it must extract R/C values for hundreds of devices, perform parasitic extraction (PEX), and analyze complex CAD layer interactions. At 3nm nodes, device extraction requires 30 to 50 CAD layers per device due to Mask Data Preparation (MDP) demands, making manual verification infeasible. This paper presents a novel automated Device Extraction Quality Assurance (QA) framework integrating three verification engines: Truth Table Checker, Compare Checker, and Device Extraction QA. The workflow ensures device extraction is properly performed as described by process development, extracting layouts from seed layers and supplying devices to SPICE netlists for simulation-based verification. Validated across technologies from 8-12 inch legacy processes to 3nm nodes, the framework enables early detection of truth table errors and parasitic device extraction issues through automated parameter qualification. The truth table checker flow has dramatically reduced turn-around time to rule deck release while significantly improving quality. With average runtimes under 30 minutes, qualification engineers receive comprehensive reports clearly indicating where attention is needed, enabling rapid issue resolution and high-confidence PDK releases.

People

Work in Progress

A Novel Way to Handle Non-Convergence of Properties in Formal Verification of Digital Systems

5:27pm - 5:28pm PDT Monday, July 27 Exhibit Hall

DescriptionThe increasing complexity of modern digital designs presents significant challenges for formal verification, particularly when properties fail to converge within practical proof bounds. Non-convergent assertions hinder verification sign-off and limit the ability to expose deep corner-case bugs. This work proposes a contract-based refinement framework to enhance property convergence in the formal verification of complex hardware systems. The methodology employs proof decomposition to identify refinement properties—helper assertions selected through overlapping cones of influence (COI)—which are then composed to strengthen the convergence of the target property. Implemented and evaluated using the Cadence JasperGold formal verification platform, the approach demonstrates improved proof bounds and enhanced bug detection across multiple architectures, including memory controllers and CPUs. Results show that the proposed technique systematically improves convergence for critical properties while maintaining scalability and broad applicability to diverse digital designs.

People

Research Manuscript

A Physics-Prior Intelligent Compact Modeling Framework for BEOL-Compatible DTCO: EKAN-Based Distillation from Neural to Symbolic Models

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionNeural compact models are increasingly explored for design–technology co-optimization (DTCO), yet their black-box nature hinders physical interpretability and seamless SPICE deployment. We introduce a physics-prior neural-to-symbolic compact modeling framework based on Efficient Kolmogorov–Arnold Networks (EKAN) trained on multidimensional oxide-FET data. EKAN first learns a smooth, bias-aware log-current surrogate; its spline activations are then distilled into a closed-form current expression via KAN-derived one-dimensional atoms, physics-guided feature libraries, and weighted sparse regression with monotonicity regularization. The resulting Verilog-A model is SPICE-ready, preserves key device trends across bias and process, and attains accuracy comparable to neural compact models while remaining interpretable.

People

Xufan Li

IMEC

Yi Li

Ning Lin

Institute of Microelectronics, Chinese Academy of Sciences

Xiaoyi Zhang

Yue Zhao

Institute of Microelectronics, Chinese Academy of Sciences

Jiaye Shen

Institute of Microelectronics, Chinese Academy of Sciences

xiaojuan qi

University of Hong Kong

Zhongrui Wang

Southern University of Science and Technology

Han Wang

University of Hong Kong

Zhenjie Yao

IMEC

Lingfei Wang

The Institute of Microelectronics of the Chinese Academy of Sciences

ling li

CAS

Ming Liu

A Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die Architectures

Engineering Presentation

11:30am - 11:45am PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionDynamic Thermal Management (DTM) techniques are increasingly critical for high-power heterogeneous chip designs, where sustained peak operation can lead to rapid thermal limit violations. We present a dynamic, probe-based thermal methodology to quantitatively evaluate settling time post peak power events and maximize peak state duration. Design comprises of a compute die along with HBM placed on interposer and then package. Distinct tile based power map was created for peak and lower activity (50-90%) states. Static thermal analysis was performed to find the corresponding maximum temperatures.
Next using DTM analysis, the settling time was extracted, which is required for each lower power state to reach steady-state temperature after exiting the peak. This was exponentially inverse to power. Lastly, peak state duration between certain thresholds was maximized depending on the settling time of each state. Maximum peak state duration of 80% and 76% were seen for peak to 50% and 60% power states respectively. This methodology enables evaluation of transient metrics using DTM analysis by linking power throttling decisions directly to time-domain thermal behavior, providing actionable insights for DVFS, workload scheduling, and safe peak performance budgeting.

People

Sumanth Suraneni

Annapurna Labs US Inc.

Nikhil Jayakumar

Amazon

Sujyesh Aanandh Manjunthan

A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control

Engineering Presentation

10:30am - 10:45am PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionThis work presents an automated EDA toolchain for synthesizing programmable and scalable CMOS analog optimization IP cores. Addressing the latency wall in real-time control, where conventional digital solvers face polynomial scaling bottlenecks, our methodology translates high-level mathematical specifications (AMPL/MPS) directly into verification-ready SPICE netlists. The synthesized IP utilizes a reconfigurable switched-capacitor architecture that implements continuous-time Karush-Kuhn-Tucker dynamics, allowing it to solve constrained optimization problems through parallel physics-based evolution rather than sequential algorithms.Unlike prior art limited to small-scale fixed-function circuits, our architecture incorporates a software-driven calibration layer to neutralize PVT variations, ensuring reliability in standard CMOS nodes. We demonstrate the flow's scalability on problem sizes ranging from dense 500-variable instances to sparse 10,000-variable workloads. Results show the generated IP achieves invariant sub-millisecond convergence regardless of complexity, delivering a >300X speedup over state-of-the-art digital interior-point solvers while maintaining solution accuracy within 0.02% relative error. This work provides a complete code-to-silicon path for deploying high-performance analog computing in edge AI and real-time control systems.

People

Cal Poly, San Luis Obispo

Research Special Session

A Quantitative Approach to Exploring Novel Image Sensor Architectures Towards Autonomous Edge Machine Vision

4:30pm - 5:00pm PDT Tuesday, July 28 Mtg Room 201A

Systems

DescriptionAutonomous edge machine vision requires image sensor architectures that simultaneously advance inference autonomy and energy autonomy. This paper introduces a quantitative modeling framework that spans conventional CMOS imagers and emerging designs—event-based/DVS sensors, coded-exposure sensors, and self-powered sensors with energy-harvesting pixels. We unify optical, circuit, and algorithmic modeling in a single analytical flow to capture how architectural choices in pixel structures, readout pipelines, compressive acquisition, and hybrid imaging–harvesting mechanisms propagate to power, latency, noise, and task-level vision performance. Extending first-principles models of self-powered vision systems, the framework also evaluates when energy-harvesting pixels provide system-level advantages over external solar harvesting, particularly in long-lived and hard-to-maintain deployments. By enabling rapid, physically grounded exploration and comparative analyses, our results reveal key trade-offs that determine when unconventional sensor architectures meaningfully enhance edge intelligence. This framework offers a principled foundation for designing next-generation energy-aware, autonomous machine vision systems.

People

Xuan Zhang

Northeastern University

Engineering Poster

A Real-Time Metric‑Driven Scorecard for Quantifying and Benchmarking Physical‑Design Quality and Deployment Progress

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionProblem Statement & Motivation

• This paper presents an automated scorecard analysis system designed to systematically evaluate and track design quality metrics throughout the development cycle.
• The system provides quantifiable insights into design using a weighted categorical scoring approach, highlighting optimization opportunities and flow gaps, enabling project teams to make informed decisions based on severity-categorized metrics.
• This Scorecard tracker application is designed to manage and display the scores of various physical design runs to ensure design quality through a structured checklist-based scoring process. This tool presents designers with categorized information to enable pin-pointed evaluation to improve quality while reducing manual efforts, leading to improved turnaround time for design closure.
• The tool offers various features such as quality assessment of flow logs, quality checks on run environment, highlighting missed checks and ensuring each manual checks is run and cleaned up. This is done along with binning checks into different categories to help designers prioritize debugs.
• The system allows users to monitor their runs efficiently. It is built with a focus on usability and monitoring various flow of physical design (Synthesis, PnR, reliability, CV, custom flows) which are used for the development of SOC.
• Results demonstrate improved prediction of design quality issues and more effective allocation of engineering resources, leading to measurable reductions in design iterations and validation time while maintaining high quality during implementation.
• Additionally, all the scores for each run, project and block are logged centrally which helps in analyzing trends of design closure during and after implementation of design. This can be an effective tool to collate learning during implementation and improving design cycle for up-coming designs.

People

Research Manuscript

A Remote Side-Channel Attack on Post-Quantum Key Encapsulation Mechanisms: A Case Study of ML-KEM on Intel x86

3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionAs post-quantum cryptographic (PQC) schemes are standardized, evaluating their resilience to side-channel attacks (SCA) becomes critical. While most prior studies focus on physical SCAs, the practicality of remote SCAs on full implementations of standardized PQCs remains largely unexplored. In this paper, we present the first generic remote power SCA on the Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM), evaluated on a modern Intel x86 processor. Our result demonstrates that power traces can be exploited remotely as a plaintext-checking oracle, enabling secret key recovery despite the scheme's theoretical IND-CCA security. Using ML-KEM as a case study, we show that complex microarchitectural mechanisms such as speculative execution and dynamic power management do not eliminate exploitable power leakage. We evaluated our attack on the PQClean implementation, achieving secret key recovery with a success rate up to 99.5%. These findings provide a realistic assessment of PQC leakage behavior on high-end processors and underscore the need for architecture-aware leakage models and co-designed hardware–software defenses to ensure secure PQC deployment in practice.

People

Mona Hashemi

National University of Singapore

Temasek Laboratories, Nanyang Technological University

Trevor E. Carlson

National University of Singapore

Engineering Presentation

A Rule-Aware Layout Conversion Framework for Back-End Physical Design

1:45pm - 2:00pm PDT Wednesday, July 29 Seaside RM 7

EDA

DescriptionAs technology nodes continue to scale, DTCO (Design-Technology Co-Optimization) increasingly requires layout teams to evaluate multiple architectural options early in the design cycle—especially in standard cells and SRAM periphery, where small structural changes can significantly affect area, performance, and DRC results.
In reality, layout implementation has not kept pace with this demand. Even modest architectural updates often invalidate existing layouts, forcing engineers to repeatedly rework structurally similar designs and slowing down DTCO feedback loops.

This work presents a lightweight, rule-aware layout conversion framework aimed at reducing repetitive layout modification effort at the cell- and library-level. Rather than introducing a new design flow, the framework focuses on automating common but time-consuming tasks such as cell-height migration, layout template regeneration, and structural refactoring under updated design rules. Each transformation step is performed in a DRC-conscious manner, helping preserve layout intent and physical consistency.

Experimental evaluations on standard cell and memory-related layouts demonstrate significant reductions in layout turnaround time while maintaining area efficiency and rule compliance comparable to hand-crafted designs. The framework integrates smoothly into existing back-end environments with minimal disruption, making it practical for everyday use.
In the longer term, this structured approach also establishes a solid foundation for future AI-assisted layout automation grounded in real layout expertise and reusable transformation logic.

People

Jaeeun Kim

Samsung

Juhyun Kang

Hyunchul Hwang

Samsung Electronics

Gwanghoon Yun

WoongSik Jung

A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionUltra‑large digital designs at advanced technology nodes now include billions of instances, deep hierarchies, and highly complex clocking and interconnect structures, making traditional flat static timing analysis (STA) increasingly impractical. Timing closure cycles have become prohibitively long due to excessive runtime, memory demands, and limited visibility across block boundaries. This work presents a scalable and silicon‑correlated timing analysis and closure methodology tailored for these massive designs. The approach unifies Boundary Model, Context‑Aware Timing, and Advanced Multi‑Input Switching (AMIS) to deliver accurate hierarchical timing without requiring design flattening. Boundary Model preserves interface logic by abstracting internal logic in order to reduce design size, while Context‑Aware Timing ensures that each block's interface timing remains aligned with top‑level requirements, regardless of differences introduced by independently developed constraints. AMIS effectively addresses inherent optimism in single‑input switching by capturing simultaneous switching effects. Combined with Tempus ECO and Certus, the methodology enables fast, localized optimization and predictable convergence. Applied to a multi‑billion‑instance design across 150+ timing views, the flow demonstrates 3.5×–5× runtime improvement, 50–65% memory reduction, and strong correlation with flat STA. This scalable methodology provides a robust foundation for achieving efficient timing closure in emerging high‑performance systems.

People

Avinash Sekar

Qualcomm

ABUBAKAR SIDDIK KANCHARA

Qualcomm

Arvind NV

Daksh Bakshi

Harivenkadesh Mohanraj

Himanshu Tanwar

Chaya N

Harish G

A Security-Centric Virtual Platform for Accelerating Shift-Left Security Firmware Development

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs the architectural complexity of SSD controllers increases, the demand for "Shift-Left" in security firmware (FW) development has become a critical necessity. Conventional firmware development heavily relies on hardware prototypes or FPGA environments, which often suffer from limited debuggability and late-stage availability, particularly for "hardware-enforced" security features.

People

Engineering Presentation

A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures

4:45pm - 5:00pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionModern Dual‑SIM‑Dual‑Standby (DSDS) designs must synchronize signaling, paging, and bearer scheduling to avoid QoS loss caused by radio conflicts, SIM‑switch delays, or RF‑resource contention creating challenges for preserving quality‑of‑service (QoS) across simultaneous networks. Dynamic Voltage and Frequency Scaling (DVFS) is a widely adopted power‑management technique in today's processors and system‑on‑chip (SoC) architectures. By dynamically adjusting supply voltage and clock frequency in response to real‑time workload demands, DVFS cuts both dynamic and static power while still meeting performance targets. In dual‑SIM devices that share radio resources between two protocol stacks, activity on one stack can induce a "blackout" on the other, leading to data inactivity and QoS degradation. The blackout duration is directly governed by the DVFS settings applied to the processor and bus while the opposite stack is executing its tasks. Existing state‑of‑the‑art methods focus on monolithic workloads, thermal‑throttling avoidance, or overall energy minimization, and they ignore the inter‑stack blackout overhead that is unique to dual‑SIM phones. This paper proposes a service‑energy based, intelligent DVFS framework that jointly optimizes the DVFS levels for both stacks by minimizing a weighted sum of throughput loss and total energy consumption. Simulation results show that the algorithm achieves a smooth, monotonic trade‑off, allowing a seamless shift between reduced blackout time and lower energy use.

People

Engineering Poster

A Simple and Predictable Solution for Early Full-Chip LVS Convergence

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionFor Large designs with multiple levels of hierarchies, predicting LVS convergence is very challenging if there are power and ground shorts and opens especially across hierarchies, as its debug could be time consuming and iterative. Also, it is difficult to identify all integration issues at next hierarchy level if any partition is LVS dirty. There are inherent disadvantages in traditional techniques such as black box LVS and destructive cleanup approach that can enable hierarchical level LVS run. To overcome these shortcomings, a simple and efficient solution which can be implemented at any stage of the partition's APR flow from floorplan to route, is described. In this solution critical interface details like Power-Ground network, global clock and signal routes which are pushed down to partitions, hard macros and partition ports are retained and are made LVS clean using this automated flow. This solution was wildly used for many partitions to identify and fix LVS issues accurately early on in multiple projects and enabled timely SoC tape-outs. This solution enabled seamless integration of late-coming partitions, as all the risks with integration were identified and fixed upfront.

People

Kumaresan Vallinayagam

Vishnu Chandrakar

A Soft-Microcode Engine to Power the Next Wave of Edge Intelligence

Engineering Presentation

3:30pm - 3:45pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionThis paper presents a CISC processor architecture designed for modern CMOS technology, featuring a compact and flexible datapath capable of operating efficiently on arbitrary data formats. The architecture supports high-level languages as well as graphics, signal processing, memory, and I/O workloads within a unified execution model.

The processor has evolved over several decades, from a TTL-based minicomputer to multiple generations of CMOS microprocessors implemented in different fabrication nodes. It has been deployed in a wide range of commercial applications worldwide. A recent dual-core implementation has been silicon-verified in 65 nm technology, and a corresponding 22 nm design has been functionally validated on FPGA.

Measured results demonstrate high energy efficiency, strong code density, and extensive support for specialized processing and peripheral control. Because much of the system functionality is implemented in writable microcode rather than fixed hardware, the architecture is well suited as a control processor in universal SoCs targeting mid-volume IoT/OT devices, where custom SoC development is impractical.

The core can also function as a processing element in AI accelerators, with microcode distributed across clustered PEs to implement individual DNN layers.

People

Stefan Blixt

Telesis Innovation

Engineering Special Session

A Unified Agentic Architecture for Rapid Deployment of Zero-Hallucination GenAI Applications

3:30pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionCorvicAI introduces an Intelligence Composition Platform designed to free enterprises from the complexity and rigidity of traditional AI data pipelines. Modern organizations struggle with fragmented tooling, extensive plumbing, and specialized expertise requirements across ingestion, parsing, feature engineering, retrieval, and reasoning. Corvic replaces this with a unified, agentic architecture that enables rapid deployment of zero-hallucination GenAI applications built on complex, multimodal data. The platform operationalizes three core laws—Agentic Data Transformation, Multimodal Retrieval Fabric, and Adaptive Agentic Orchestration—to ensure trustworthy data access, contextual understanding, and dynamic reasoning. By integrating graph AI, semantic search, multimodal retrieval, and explainable agentic workflows, Corvic delivers higher precision, full traceability, and dramatically faster time-to-value, reducing development cycles from months to days. The platform powers use cases across compliance, analytics, customer support, research, and predictive intelligence, offering enterprises a scalable path to reliable AI adoption.

People

Hadi Ahmadi

Corvic AI

Engineering Presentation

A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck

2:30pm - 2:45pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionHigh-quality standard-cell libraries are essential for reliable SoC design and sign-off. However, modern libraries span many views, PVT corners, and modeling formats, making validation increasingly complex, fragmented, and time-consuming when using ad-hoc or per-view approaches.
This work presents a structured quality-checking methodology based on Siemens Solido Crosscheck for systematic validation of standard-cell collaterals. The approach classifies checks by configuration complexity, ranging from simple Boolean validations to fully parametric checks requiring characterization-specific inputs. Native Crosscheck checks are leveraged and fine-tuned in collaboration with design and characterization engineers, while custom checks are introduced to address requirements not covered by native capabilities. The methodology supports both early, incremental validation during Liberty generation and comprehensive quality assessment once all views are available, enabling unified cross-view analysis.
The proposed framework enables scalable, parallel validation across thousands of configurations, improves detection of modeling and consistency issues early in the flow, provides structured reporting and traceability, and reduces late-stage rework ultimately accelerating time-to-market while improving release confidence and overall library quality.

People

Engineering Poster Gladiator

A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes

2:11pm - 2:22pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAdvanced‑node libraries must meet aggressive PPA targets across wide voltage ranges, including near‑/ultra‑low‑voltage operation where process variation is amplified and non‑Gaussian. Traditional sensitivity‑based LVF (SBA) fails to retain accuracy under these conditions, while Monte‑Carlo (MC) is impractical for full‑library, multi‑PVT production. We present a unified methodology that integrates
(i) ML‑based LVF to capture moments and sigma at ULV with production‑viable runtime,
(ii) MIS‑aware characterization to model simultaneous input switching for accurate gate delays—particularly on hold‑critical paths, and
(iii) in‑flow EM reliability generation and validation.
Across combinational and sequential cells, our ML‑LVF correlates closely with MC (comparable accuracy at a fraction of runtime), and MIS modeling closes the GLS vs. standalone delay gap observed on short paths. The flow also delivers signoff‑quality Liberty views with PrimeTime‑consistent timing/power correlation and enables early reliability checks. Overall, the methodology accelerates library turnaround while improving accuracy and reducing downstream timing/reliability closure risk for advanced‑node designs.

People

Analyst Presentation

A View from Wall Street

10:15am - 11:00am PDT Monday, July 27 DAC Pavilion, Exhibit Floor

DescriptionWe will examine the financial performance and key business metrics of the EDA industry through 2025, the consolidation of Engineering Software, and the material technical and market trends and requirements that are affecting the industry's business performance and strategies- including our AI/ML Phenomenonology. Among the trends and catalysts, we will again examine the progression of semiconductor R&D spending and how the market values of Cadence-Synopsys have evolved. Lastly, we will provide our updated financial projections for the EDA industry for 2026.

People

Jay Vleeschhouwer

Managing Director at Griffin Securities

Research Manuscript

Acc-SpMV: Accelerating General-Purpose Sparse Matrix-Vector Multiplication with GPU CUDA Cores

1:42pm - 1:55pm PDT Wednesday, July 29 Mtg Room 101B

AI3-II. AI/ML Application and Infrastructure

DescriptionGeneral Sparse Matrix-Vector Multiplication (SpMV) is a fundamental kernel in scientific computing, graph analysis and deep learning. However, to fully unleash the power of CUDA cores performance, systematic optimization is required for SpMV. In this paper, we propose OmniSpMV, a high-performance SpMV library on CUDA cores, with multiple optimizations, including data-locality-aware reordering, memory-efficient tiling , sparsity-aware load balancing and highly optimized SpMV kernel. Extensive experimental results on various NVIDIA GPU architectures with 2715 matrices show that, OmniSpMV achieves significant performance improvements on average, 2.58x (up to 6.39x) speedup on RTX 4090, 1.91x (up to 4.92x) speedup on A800, and 1.78x (up to 8.21x) speedup on H100 over cuSPARSE designed for CUDA cores, and 1.93x (up to 15.67x) speedup on RTX 4090, 1.70x (up to 15.02x) speedup on A800, and 1.75x (up to 14.53x) speedup on H100 over DASP designed for Tensor cores.

People

Tang Lei

Xin Zhikuang

Wang Zijian

Zhou Chunbao

Wang Jue

Wang Yangang

AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning

Research Manuscript

5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionDesign Rule Checking (DRC) is a critical yet computation-intensive stage in modern very large scale integration design. As processes evolve, the high computational cost of DRC has become a significant bottleneck for design efficiency. Current acceleration approaches do not fully leverage the parallelism of DRC, resulting in limited performance gains. To address this challenge, we propose AccDRC, an FPGA-accelerated DRC based on software–hardware co-design. On the software, we design a cell-aware partitioning strategy with a data preparation and task encapsulation mechanism, which reorganize layouts into balanced task units tailored for FPGA processing. On the hardware, we implements an acceleration architecture consisting of a locality-preserving data-loading module, a unified and reconfigurable check core, and a sparse result writeback module. This architecture exploits DRC's locality, structural commonality across rules, and sparse violation outcomes, enabling high-throughput dataflow execution with multi-level parallelism. Experimental results show that AccDRC achieves 522.11x ~1071.03x speedup over the CPU-based DRC tool KLayout, and 9.62x ~ 26.07 x speedup over the state-of-the-art GPU-based DRC tool OpenDRC.

People

Research Manuscript

Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator

1:42pm - 1:55pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionSRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators.

People

Anhui Polytechnic University

Work in Progress

Accelerated Dynamic Voltage Drop Prediction Using a Lightweight Machine Learning Model

5:21pm - 5:21pm PDT Monday, July 27 Exhibit Hall

DescriptionAccurate dynamic voltage drop (DVD) analysis is increasingly critical in advanced nodes, where higher densities, lower voltages, and complex packaging exacerbate power delivery challenges. Traditional simulations are computationally expensive and typically performed late in the design cycle, risking costly redesigns. We propose a lightweight ML-based DVD prediction model using multi-scale CNNs, fusion layers, and skip connections to capture spatial and hierarchical power grid features. The model uniquely incorporates package and grid inductance and supports both vectorless and vector-based inputs. Evaluated on a 16 nm RISC-V core, it achieves 80-86 % accuracy with 5 mV tolerance and over 25,000× faster runtime than commercial tools.

People

Itay Yonatanov

Ido Parchomovsky

Mohamad Omari

Freddy Gabbay

Accelerating AI+SAR Applications Through Enhanced Graph Optimization

Research Manuscript

2:21pm - 2:34pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionSynthetic Aperture Radar (SAR), benefiting from its all-weather, all-time, and high-resolution characteristics, has become a vital tool in earth observation.
A typical application of SAR first completes the imaging process of echo data and then conducts subsequent analysis.
As AI excels in image classification and recognition, integrating AI with SAR has garnered significant interest.
In order to leverage the acceleration capabilities of existing AI frameworks, particularly graph optimizations, while also reducing developing complexity, developers strive to streamline the entire SAR application within these frameworks.
However, a key performance challenge arises: SAR imaging differs greatly from typical AI tasks in both the requirements of data layouts and the composition of operators, causing graph optimizations to fail in effectively accelerating the SAR imaging process.
The fundamental reason is the failure of the two key graph optimizations: layout transformation and operator splitting.

In this paper, we first address the issue of significant transpose overhead introduced by the layout transformation strategy.
To this end, we propose a novel layout transformation strategy based on pseudo-transposition operators, which can completely eliminate transpose overhead while maintaining memory access efficiency.
Subsequently, we design a tailored splitting strategy based on movable reverse-order operators to compensate for existing frameworks' lack of capability in handling the core FFT operators.
The proposed strategies were implemented in PyTorch and LiteRT, yielding a significant speedup of 3.45x for SAR imaging process.

People

Yang Shi

Yaohua Wang

Zhe Li

Accelerating CPU Design in Advanced Nodes with AI-Powered Floor Planning and VT Optimization

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs technology nodes scale into the angstrom regime, design complexity has surged due to stringent performance, power, and area (PPA) targets and the need to manage diverse cell libraries across multiple PVT corners. Achieving optimal cell selection, macro placement, and layer distribution under these conditions is highly challenging, making manual tuning impractical given tight timing closure, power budgets, VT proliferation, and floorplan sensitivity. Automation is now essential to enable systematic design space exploration and maintain competitiveness.
This paper presents an AI-driven approach to automate floorplanning and VT optimization for macro-dominated, high-frequency CPU designs in sub-nanometer nodes. The proposed solution integrates VT-Optimizer (VT-Opt), which tunes multi-VT flows by generating adaptive VT recipes and validating them through full-flow runs, and FP-Opt, which explores alternative floorplans by adjusting bounding boxes, aspect ratios, and macro placements while targeting utilization, congestion, timing, and power. Optimal configurations are selected based on full-flow evaluations, followed by PPA optimization to achieve best-in-class results.
The methodology significantly reduces design turnaround time, mitigates risk, and improves PPA, demonstrating its effectiveness for next-generation CPU designs.

People

Lakshmidas K

Gowry Shanmugam

Accelerating DFT Verification and Enhancing Debuggability Using Veloce-Based Full Chip Gate-Level Emulation

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis paper describes the development of a full-chip gate-level emulation environment that enables DFT verification and the successful application of Debug STIL vectors generated by the Tessent DFT tool in the Veloce emulation environment, significantly improving debuggability and shortening the product verification time.

People

Engineering Presentation

Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation

4:30pm - 4:45pm PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionAs hardware designs grow in complexity, Formal Verification (FV) often hits scalability walls, resulting in "bounded" proofs rather than full closure.Deep state-space exploration is limited by computational resources. Overcoming this typically requires "helper" assertions (invariants), but manually identifying and writing these is labor-intensive and requires deep micro-architectural knowledge. In this presentation, we present our findings where we used AI/ML & GenFV to generate helpers to achieve full proofs and reduce the verification cycle time

People

Bindumadhava Singanamalli

Google

Pandithurai Sangaiyah

Google

Sean Safarpour

Sayandeep Sayandeep Sanyal

Engineering Poster

Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionHPC applications like Datacenter, Server, AI-Training and AI-Inference application chips are Multi Billion Big-Die Designs and requires huge compute and disk requirements for simulations. Depending on the type of design architecture logic subsystems are repeated 30 to 80% of full design. Full flat simulations on such designs take ~8k to 11k cores with a peak machine memory requirement of 200TB to 300TB. Disk space requirement would be ~50TB. Hence, running Full Flat simulations are not practical as they would be taking huge compute and disk space resources. Full chip EMIR checks are important to ensure Blocks and Subsystems are well connected with RDL/Bumps and to ensure signoff is within margin. This can be done at abstract level with blocks' and subsystems' current and parasitic modelled using Reduced Order Model (ROM).On using ROM, a significant reduction is observed in run-time and disk-space used while maintaining accuracy.

People

Work in Progress

Accelerating Functional Fault Grading for Flash and DRAM Designs

6:30pm - 6:31pm PDT Monday, July 27 Exhibit Hall

DescriptionFunctional fault grading is essential for post-silicon validation in scan-limited designs, but simulation cost grows with fault and pattern volume. We propose an optimization-driven methodology combining static fault optimization, fault clustering, design pruning, stimulus grading, dynamic fault optimization, and parallel fault simulation management. By leveraging both structural design information and stimulus behavior, the flow eliminates redundant computation by performing optimized simulations tailored to fault activation and propagation potential. Applied to a production-grade NAND Flash and DRAM designs, the approach achieved a 3.7x and 2x reduction in simulation time, respectively, while preserving test coverage. The methodology is broadly applicable to logic and SoC designs, offering scalable fault grading without reliance on scan structures.

People

Research Manuscript

Accelerating GPU Inference of Large Language Models with Moderately Unstructured Sparse Weight Matrices

3:30pm - 3:43pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionWith the growing deployment of large language models (LLMs), LLM inference cost has become a key challenge. Pruning techniques that introduce sparsity into weight matrices can accelerate inference. However, maintaining model quality typically limits pruning to moderate unstructured sparsity (around 50\%). At these sparsity levels, none of the existing GPU kernels for sparse matrix multiplication (SpMM) can outperform their dense counterparts. This paper proposes an efficient GPU inference method for LLMs with moderate sparsity. We propose a three-layer matrix storage format comprising: (i) a Sparse-TC layer enabling sparse tensor cores to accelerate SpMM; (ii) a Slot-Filling layer using parallel differential distance for matrix compression while supporting low-cost on-chip decoding; (iii) a lightweight Residual Layer ensuring correct SpMM computation. Building on this format, we design a SpMM kernel that jointly utilizes sparse tensor cores and CUDA cores. This design enables an efficient execution pipeline and overlaps on-chip computation with memory access. Evaluations show that our work is the first to outperform dense matrix multiplication on modern GPUs equipped with high-bandwidth memory (HBM). It achieves up to 1.64× kernel-level speedup over SpInfer (EuroSys'25, Best paper) and up to 1.41× end-to-end speedups over FlashLLM (VLDB'24). Our source code: https://anonymous.4open.science/r/spmm-32E1.

People

Tao Lu

National Univerisity of Singapore

National University of Singapore

Wenzhi Chen

Zhejiang University

Engineering Poster

Accelerating IR and Timing Convergence with Revolutionary IR-ECO

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionComplex applications (such as AI & HPC) and advanced tech nodes are driving a dramatic increase in design scale and complexity. It's currently impractical to construct a robust power delivery network (PDN) by consuming a large amount of design resources and the higher local cell density causes worse voltage drop(IR) violations than ever before. At the same time, the margin of the process is decreasing continuously, the influence of voltage drop on timing is becoming increasing prominent. Therefore, it becomes crucial to establish the correlation between IR and timing to avoid over-fixing.
In traditional flow,
§ We fix IR violations by fixing thousands of violation instances(victims). However, this approach has a low profit. It takes multiple manual iterations to resolve the violations, because the root cause of the violations(aggressors) is not identified.
§ The impact on timing cannot be considered during the manual IR violation fix cycles. Meanwhile, an instance with IR issue is usually also an instance that is sensitive to the timing. In this case, we finally need to perform a hard tradeoff between IR and timing.
§ Separated IR and Timing ECOs are very time consuming, costly and always posed significant challenges for design closure within tape-out timelines.
To minimize iteration counts and design changes, avoid timing degradation or chip failure, an automated late-stage timing-aware IR fix methodology is proposed here. The joint IR-ECO flow ensures seamless communication between the golden ECO tool PrimeClosure and golden IR/EM analysis tool RedHawk-SC, enables accurate identification of root cause aggressors, provides immediate feedback on the voltage impact of ECO operations proposed by PrimeClosure, and automatically fixes IR violations without timing hurt.
In our design, IR-ECO can fix over 60% of signoff-stage IR violations within a few hours, and introducing few/no negative impact on timing, which is very important for timing- critical blocks. Minimum number of instances changed by addressing aggressors. Fewer design change operations and minimum iterations can save several weeks of iteration period than traditional flow. This offering better PPA and significantly boosts the time to tape out.
keywords : IR-ECO, IR-timing closure, aggressor analytics, timing-aware IR fix

People

Engineering Poster

Accelerating Memory Cache Verification with AI-Powered Batch Flow Methodology

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAchieving rigorous 6-6.5σ yield targets in L1 caches and other memory IP components requires extensive high-sigma verification. However, traditional brute-force Monte Carlo simulations and manually piloted GUI-based analyses are too slow and inefficient to verify large numbers of cells within tight project timelines, limiting analysis scope and compromising critical worst-case corner identification.

This paper introduces an innovative AI-powered batch flow that automates and significantly accelerates high-sigma memory cache verification, ensuring accurate, full-coverage analysis across all cells and components. The proposed methodology leverages adaptive AI to rapidly identify worst-case corners and eliminates unnecessary high-sigma runs by only deploying brute-force accurate verification on the identified critical corners.

In an example testcase, this AI-powered batch flow achieved full-coverage verification across 726 netlists in 38 hours and 20 minutes, averaging 2,514 simulations per job, representing an average 3.25x runtime speedup and 2.4x simulation speedup per job over the previous GUI-based method. Enhanced modeling and yield solver algorithms also contributed to reducing per-job simulations, and the flow automation and parallelization reduced engineering effort and overall runtime, making full coverage verification feasible within production timelines and improving disk space management. This scalable, AI-driven flow provides a fast, accurate, and comprehensive solution for memory IP validation challenges.

People

Engineering Presentation

Accelerating RTL and Verification Development via Automated Visual-to-Executable Specification Generation

10:30am - 10:48am PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionThe accelerating scale and intricacy of system‑on‑chip (SoC) designs demand innovative methodologies for register‑transfer‑level (RTL) development and verification to sustain aggressive time‑to‑market objectives. Typical chip development starts with architectural planning and diagrammatical representations for visual reference (.vsdx). This is followed with generation of Block/Sub-System wise specifications to use it for RTL Development and Verification. However, conventional flow relies on manual abstraction of these downstream specifications, which is highly resource-intensive, error‑prone, and prone to inconsistencies with the canonical design intent. The proposed work introduces an automated utility that extracts structural information from high‑level architecture diagrams (.vsdm) and synthesizes a comprehensive JSON metadata repository. The generated metadata serves as a single source of truth for automatically deriving all downstream collaterals required for RTL coding and verification, thereby eliminating manual transcription errors and ensuring alignment with the golden architecture reference. The utility also incorporates a sanity checker that validates and corrects architecture diagrams to conform with design guidelines. Integration of the metadata with existing verification frameworks further streamlines test‑bench generation and compliance checking. Experimental deployment demonstrates a substantial reduction in specification‑related issue tickets and a measurable acceleration of RTL development and verification cycles, confirming the utility's effectiveness in mitigating human effort and error.

People

Engineering Presentation

Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation

1:30pm - 1:45pm PDT Wednesday, July 29 Seaside Ballroom A

EDA

Systems

DescriptionWith the advent of the A.I era, the amount of handling data of SOC has sky-rocketed and power consumption inevitably increased. To suppress this phenomenon, various low-power hardware architectures have been added to the SOC and consequently 1) "X" values that cause bugs at silicon level have appeared and 2) verification complexity and TAT have increased to detect "X". Emulator is a general solution for reducing verification time, but it degrades the quality of power verification since it can only express two logical states ("0" and "1"). In this study, we propose a high performance 4-state ("0", "1", "X", and "Z") RTL power-aware simulation methodology leveraging an emulator. This methodology focuses on the precise modeling of UPF (Unified Power Format) intents and 4-state logic, which are vital for capturing realistic power behavior. We demonstrate that the seamless verification of UPF-driven power scenarios at hardware speeds while maintaining the logic granularity of 4-state simulation. Finally, by applying to the latest SOC project, we confirm that there is a 35 times performance gain compared to conventional simulation.

People

Research Manuscript

Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators

1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 202C

EDA

EDA9. Test, Validation and Silicon Lifecycle Management

DescriptionTo meet the increasing computational demands of large language models (LLMs), multi-systolic-array architectures are widely adopted by AI accelerators. However, compared with single-array designs, hardware faults in multi-array accelerators propagate more complexly way and cause more severe reliability degradation. Directly deploying single-array fault-tolerant mechanisms to multi-array architectures will introduces significant overhead. To address this limitation, we propose a Reliability-Aware Scheduling framework that jointly considers hardware-level reliability variations, operator-level error sensitivity, and inter-operator data dependencies. The scheduler maps insensitive operators to faulty arrays and reserves reliable arrays for critical computations, significantly improving reliability with minimal performance loss.

People

Engineering Poster

Accurate Characterization Methodology for Combo-IO Design with Concurrent Switching Outputs for Precise Power Analysis at SoC

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs semiconductor technology scales to smaller nodes, achieving area-optimized and low-power integrated circuits require advanced design architecture ‘s coupled with precise power estimation. Accurate power analysis depends on NLPM data embedded in Liberty models, which guide critical architectural trade-offs.

This paper investigates internal power modelling challenges in modern System-on-Chip designs employing Combo-IO architectures, where multiple communication standards such as GPIO, I2C, and I3C are integrated within a single physical block. The absence of dedicated control signals causes multiple receiver outputs to switch simultaneously, leading to significant inaccuracies in conventional internal energy characterization.

A comparative study of two characterization methodologies, path-based vs design-based, is presented for Combo-IO, with experiments driven by Siemens Characterizer. Liberty models generated by these methods are validated through power analysis.

Results demonstrate that path-based characterization leads to a scalable overestimation of internal power, with errors ranging from 2X to 4X for designs containing two to four active outputs. The proposed design-based methodology accurately distributes energy dissipation across concurrently switching outputs, enabling reliable power estimation for advanced low-power ICs.

People

Engineering Poster Gladiator

Accurate Full-Custom Thermal and EM Analysis for Advanced Nodes

5:45pm - 5:52pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAnalyzing circuits for susceptibility to electro-migration has been a requirement for integrated circuit design since the 1960's. In fact, one of the basic equations for electro-migration, Black's Equation, was formalized in 1969 and is still in use today. In related work, Statistical Electro-migration budgeting (SEB) was developed by DEC in the 1980's. Both these equations are the foundation of the electro-migration analyses used in modern EMIR tools. One very important feature of these equations is that they are exponentially dependent upon the wire temperature and failures start to occur with increasing probability at higher temperatures. This fact is important because with the introduction of new device structures such as FINFET, GAA, and possibly CFET, the power per unit area and resulting heating generated by these structures has been increasing dramatically. In addition, the power dissipated by high resistance wires and vias is also increasing as these wires need to carry higher RMS currents to support higher frequency operation of the circuits. Therefore, it is becoming increasingly critical to model the temperature very accurately for small device structures to avoid EM failures associated with high device and wire heating. By utilizing the latest Finite Element solvers (FEM) available from various CAD vendors, accurate wire temperatures can be computed by solving the heat conduction equations at the device and wire nanoscale thereby providing very useful feedback to designers regarding thermal and EM SEB FIT reliability risk for unusual corner cases that require additional validation using these more accurate simulations.

People

David Newmark

Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip

Engineering Presentation

1:45pm - 2:00pm PDT Tuesday, July 28 Seaside RM 7

Design

EDA

DescriptionIt has been observed for several years that transistors of different threshold voltage types (VT) in one chip may contain different silicon to SPICE gap (S2S). This gap may result in risk of yield loss when industry uses SS (all VTs at SS) and FF (all VTs at FF) in signoff because of omitting risk when one VT is fast but the other VT is slow. This risk on timing is called as VT skew. Currently, there is no efficient approach that can accurately quantize VT skew risk. To solve this issue, this study introduces an analytical metric and an Monte-Carlo (MC)-based solution to accurately model Vt skew impact. The analytical metric can help give early quick assessment and the MC-based solution has been developed inside EDA tool.

People

Research Manuscript

ACE-NAS: A Zero-Cost NAS Framework for Co-Design of Architecture and Encoding in Spiking Neural Networks

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionSpiking Neural Networks (SNNs) promise exceptional energy efficiency for neuromorphic computing through event-driven processing. However, unlocking their full potential requires navigating a
complex, strongly coupled design space of network topology and
temporal neural encoding. Existing SNN Neural Architecture Search
(NAS) frameworks typically decouple these dimensions, focusing
exclusively on topology search while relying on manual, fixed encoding schemes. This limitation leaves a vast portion of the design
space unexplored, resulting in sub-optimal energy-accuracy trade-offs. To bridge this gap, we present ACE-NAS, the first zero-cost
NAS framework that automates the co-design of SNN architecture
and encoding mechanisms. Addressing the challenge of "encoding-blind" proxies, we introduce Jacob_cov, a novel Jacobian-based
spectral metric that efficiently quantifies the temporal discriminability of different encoding schemes without training. ACE-NAS
integrates Jacob_cov with structural proxies (ZiCo) into a hardware-aware, multi-objective evolutionary search strategy. On CIFAR-10,
ACE-NAS achieves 92.95% accuracy, effectively identifying Pareto-optimal designs that balance high performance with minimal spike
activity. By automating the joint optimization of structure and
dynamics, ACE-NAS delivers an orders-of-magnitude reduction
compared to standard training-based NAS and a 7× speedup over
state-of-the-art efficient SNN-NAS methods (e.g., AutoSNN).

People

Mingyu Qin

Sun Yat-Sen University

Liangming Fang

Wei Liu

Jinghai Wang

shanlin xiao

Achieving "zero Defect" Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & Verification

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAutomotive Ethernet ICs require robust design and extensive high-sigma verification to meet stringent "zero defect" quality standards, with every device parameter required to yield at least 5σ. Robustness by design is time-consuming and introduces PPA and EMI tradeoffs that must be mitigated by parameter optimization. Traditional brute-force Monte Carlo simulations are impractical for high-sigma verification, and manually trimming and optimizing parameters is time-intensive.

This paper presents an innovative AI-powered methodology that significantly accelerates high-sigma verification, trimming, and optimization for automotive ethernet solutions. This approach integrates adaptive AI for efficient parameter robustness screening and ML-based sensitivity analysis for identifying parameters that most contribute to variation, while intelligent, built-in trimming and optimization in-the-loop automatically mitigate sensitive parameters to bring critical measurements back into spec.

In the example Bandgap Reference to Low-Dropout (LDO) circuit, the proposed methodology achieves strong correlation with silicon production data, while providing >64,000x speedup over brute-force methods. This solution accurately predicts high-sigma failures, automatically determines trim codes, and automatically optimizes targets with minimal simulations, leading to substantial speedups, reduced resource requirements, and faster time-to-market.

People

Krishanu Dey

NXP

Ganesha Moorthy Krishnasamy

Engineering Poster

Achieving High-Integrity Safety for 360-Degree Automotive Display Soc's RETIME-IP: A Static Analysis Approach to ASIL-D Compliance

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe RETIME-IP is a critical component in OMNIVISION's image sensor SoC, used in automotive, 360-degree surround-view systems. This IP is responsible for receiving raw data from upstream image sources, processing it, and storing it into SRAM for consumption by downstream modules. Given that this SoC is classified as ISO-26262 ASIL-D, the RETIME-IP must also adhere to ASIL-D requirements, in accordance with the ASIL decomposition guidelines set forth in ISO 26262-10:2018, Clause 11. While the RETIME-IP was initially designed with several safety-mechanisms (SMs) to meet the necessary fault coverage, subsequent fault injection analysis identified the need for additional SMs to reach the ASIL-D targets.
This paper outlines a novel methodology using a Certified tool as per ISO26262-8:11. Using Static Analysis fault classification to find the safety gaps and thereby add SMs only in the areas required without the increase in the hardware. An intuitive way of fault classification to ISO26262 classification is employed. Also to reduce the faults that need to be simulated, Constant-Analysis, is employed to mark blocked faults as safe. The result was not only achieving the ASIL-D SPFM target of 99% but also achieving it in much less iterations, thereby saving project time compared to similar SoC projects.

People

Jerry (Chaojie) Chen

Omnivision Technologies (Shanghai) Co. Ltd

Niko (Bicheng) Guo

Omnivision Technologies (Shanghai) Co. Ltd

Sesha Sai Kumar C V

Optima Design Automation Ltd

Jamil R Mazzawi

Optima Design Automation Ltd

Research Manuscript

Achieving Intra- and Inter-Operator Communication Lower Bounds in Near-Memory Processing

10:56am - 11:10am PDT Tuesday, July 28 Mtg Room 203AB

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionNear-memory processing (NMP) is a promising way to overcome the memory wall in large language models (LLMs). However, dataflow optimization in NMP is fundamentally constrained, as existing analyses cannot efficiently handle the new distributed vault/channel organization. We propose the Remote-Access-Free (RAF) dataflow, which uses tensor rotation to abstract this distributed organization and eliminate all intra-operator remote access. On top of RAF, we apply analytical optimization to minimize intra-operator local access, thereby achieving the intra-operator communication lower bound. We then introduce data partitioning that removes inter-operator remote access and enable operator fusion to minimize inter-operator local access, so that the inter-operator communication lower bound is also reached. Experimental results show that RAF reduces energy by 50.4%, 39.0%, and 37.8%, and delivers speedups of 3.98×, 1.72×, and 1.57× over IANUS, H^2LLM, and OptiPIM, respectively.

People

Lei Xu

Chen Yin

Zelong Yuan

Weiguang Sheng

Jianfei Jiang

Qin Wang

Naifeng Jing

ACM SIGDA/IEEE CEDA University Demonstration

Student

10:00am - 7:00pm PDT Monday, July 27 Exhibit Hall

Student

Research Manuscript

Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge

1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS1. Autonomous Systems (Automotive, Robotics, Drones)

DescriptionVision-Language-Action (VLA) models have emerged as a unified paradigm for robotic perception and control, enabling emergent generalization and long-horizon task execution. However, their deployment in dynamic, real-world environments is severely hindered by high inference latency. While smooth robotic interaction requires control frequencies of 20--30 Hz, current VLA models typically operate at only 3--5 Hz on edge devices due to the memory-bound nature of autoregressive decoding. Existing optimizations often require extensive retraining or compromise model accuracy.

To bridge this gap, we introduce ActionFlow, a system-level inference framework tailored for resource-constrained edge platforms. At the core of ActionFlow is a Cross-Request Pipelining strategy, a novel scheduler that redefines VLA inference as a macro-pipeline of micro-requests. The strategy intelligently batches memory-bound Decode phases with compute-bound Prefill phases across continuous time steps to maximize hardware utilization. Furthermore, to support this scheduling, we propose a \textbf{Cross-Request State Packed Forward} operator and a Unified KV Ring Buffer, which fuse fragmented memory operations into efficient dense computations. Experimental results demonstrate that ActionFlow achieves a 2.55 times improvement in FPS on the OpenVLA-7B model without retraining, enabling real-time dynamic manipulation on edge hardware.
Our work is available at https://anonymous.4open.science/r/ActionFlow-1D47.

People

Yuntao Dai

Hang Gu

teng wang

Qianyu Cheng

Yifei Zheng

zhiyong qiu

IEIT Systems Co., Ltd.

Lei Gong

Wenqi Lou

USTC

Xuehai Zhou

Active Imitation Learning for Thermal- and Kernel-Aware LFM Inference on 3D S-NUCA Many-Cores

Research Manuscript

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionLarge Foundation Model (LFM) inference is both memory- and compute-intensive, traditionally relying on GPUs. However, their limited availability and high cost have driven growing interest in high-performance general-purpose CPUs, particularly emerging 3D-stacked Static Non-Uniform Cache Architecture (3D S-NUCA) systems. While these architectures improve bandwidth and data locality, they introduce severe thermal constraints and non-uniform cache latencies caused by 3D Networks-on-Chip (NoC). Efficient management of thread migration and V/f scaling remains challenging due to diverse LFM kernels and hardware heterogeneity. We propose AILFM, an Active Imitation Learning (AIL)–based scheduling framework that learns near-optimal thermal-aware policies from Oracle demonstrations with minimal runtime overhead. AILFM captures both core-level performance variations and kernel-specific behavior, maintaining thermal safety while maximizing inference efficiency. Extensive experiments demonstrate that AILFM outperforms state-of-the-art baselines and generalizes across diverse LFM workloads.

People

Yixian Shen

Chaoyao Shen

Jan Deen

George Floros

University of Thessaly

Andy Pimentel

Anuj Pathania

Activity Reloaded: Joules Flash Replay - A Methodology for Accurate, Delay-Based Activity Generation for Driving Optimization and Power Sign-off

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAccurate switching activity is essential for effective low‑power optimization in modern digital flows, however, activity fidelity rapidly degrades as RTL progresses through synthesis, mapping, and physical implementation. This loss of annotation forces downstream tools to depend on incomplete or vectorless estimates, diminishing the quality of power optimization. Glitch power, which can account for 20-30% of total dynamic power at advanced nodes, typically requires costly delay‑based Gate Level Simulation (GLS), resulting in prohibitive runtime and compute overhead. Conventional activity regeneration further relies on RTL or GLS teams, creating schedule bottlenecks and widening PPA gaps.

The proposed Flash Replay flow methodology eliminates these limitations by enabling rapid, on‑demand activity refresh using the Joules RTL Power tool, with minimal turnaround‑time impact on the full digital flow. It generates glitch‑aware power data significantly faster than GLS and reconstructs complete switching activity for vectorless or partially stimulated designs using lightweight seed vectors or prior RTL activity of the same design. Seamless integration with Genus and Innovus enables consistent, delay‑based activity generation throughout the RTL‑to‑signoff flow.

Results demonstrate up to 10% total power reduction when Flash Replay is incorporated into existing implementation flows, along with up to 25X speedup versus simulation‑based replay. These improvements establish Flash Replay as a practical, scalable solution for restoring activity accuracy and enhancing low‑power implementation efficiency.

People

Nimish Agashiwala

Activity-Aware Partitioning for Effective Multi-Threaded Event-Driven RTL Simulation

Research Manuscript

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionRegister-transfer-level (RTL) simulation is commonly accelerated through multi-threading and event-driven technique.
However, when these techniques are combined, severe load imbalance arises: in event-driven execution, circuit regions exhibit highly uneven activity, leaving many threads idle with very low utilization.
Existing multi-threaded RTL partitioning models often optimize full-cycle execution and ignore the dynamic activity variation that dominates event-driven workloads.

We present PGSIM, a multi-threaded event-driven RTL simulator that incorporates runtime activity information into its partitioning model.
Our model augments hypergraph weights with measured activity frequency and inter-block activation correlation, which is efficiently estimated through a lightweight MinHash profiler.
By aligning thread assignment with true activity patterns, PGSIM substantially reduces idle time and improves utilization.
Across experiments on large benchmarks, PGSIM achieves 20–30% higher performance than its activity-unaware version, delivers a simulation speed of 200-400 kHz and up to 8.9× speedup over Verilator.
These results demonstrate that runtime activity modeling is essential for scalable multi-threaded event-driven simulation.

People

Pengpeng Ren

Yun (Eric) Liang

Adagscale: Viewpoint-Adaptive Gaussian Scaling in 3D Gaussian Splatting to Reduce Gaussian-Tile Pairs

Research Manuscript

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionReducing the number of Gaussian-tile pairs is one of the most promising approaches to improve 3D Gaussian Splatting (3D-GS) rendering speed on GPUs. However, the importance difference existing among Gaussian-tile pairs has never been considered in the previous works. In this paper, we propose AdaGScale, a novel viewpoint-adaptive Gaussian scaling technique for reducing the number of Gaussian-tile pairs. AdaGScale is based on the observation that the peripheral tiles located far from Gaussian center contribute negligibly to pixel color accumulation. This suggests an opportunity for reducing the number of Gaussian-tile pairs based on color contribution. AdaGScale efficiently estimates the color contribution in the peripheral region of each Gaussian during a preprocessing stage and adaptively scales its size based on the peripheral score. As a result, Gaussians with lower importance intersect with fewer tiles during the intersection test, which improves rendering speed while maintaining image quality. The adjusted size is used only for tile intersection test, and the original size is retained during color accumulation to preserve visual fidelity. Experimental results show that AdaGScale achieves up to 9.47× speedup over the original 3D-GS on a GPU, with only about 0.2 dB degradation in PSNR.

People

Research Manuscript

Adahuff-GNN: A Convergency-Aware Adaptive Huffman Compression for Communication Reduction in Distributed GNN Training

11:23am - 11:36am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionDistributed training of Graph Neural Networks (GNNs) is hindered by communication overhead from exchanging embeddings and gradients. Existing quantization methods mitigate this cost by using shared bit widths at the layer or group level, followed by node-level uniform quantization, but such coarse granularity cannot fully exploit redundancy in long-tailed communication distributions. Entropy compression is well suited to these distributions, but static entropy compression schemes become less effective when training induces untracked distribution shifts. To address this issue, AdaHuff-GNN, a convergency-aware adaptive Huffman compression framework, is proposed to apply entropy compression to reduce communication cost in distributed GNN training. Within AdaHuff-GNN, loss-triggered codebook reconstruction and coarse-to-fine adaptive selection of codebook sizes jointly produce stage-wise codebooks that track distribution shifts. Binning-assisted clustering and conflict-free decoding reduce codec overhead on the communication critical path. Experiments show that AdaHuff-GNN reduces communication volume by 2.87× and shortens training epoch time by 37.5% over state-of-the-art methods without degrading model accuracy.

People

Zhiyu Sun

Jihe Wang

zhaohui jia

Yuanhua Xiao

Linying Wu

Adana: Accelerating Large Language Models via Adaptive Nonuniform Asymmetric Quantization

Danghui Wang

NPU

Research Manuscript

4:36pm - 4:50pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionWe propose \texttt{Adana}, a hardware-software co-design that enables efficient low-bit group-wise quantization for LLMs based on the adaptive nonuniform asymmetric numeric type. First, \texttt{Adana} introduces a novel numeric type that precisely captures the nonuniformity and asymmetry of data within small groups. In addition, an approximate metric for quantization error is proposed to facilitate efficient implementation of online adaptive activation quantization. Finally, a dedicated LLM acceleration microarchitecture is developed for \texttt{Adana}. Compared to state-of-the-art designs, \texttt{Adana} achieves 1.42$\times$--2.10$\times$ speedups and 18.9\%--48.5\% power savings on LLMs, while maintaining superior accuracy.

People

Xinkuang Geng

Siting Liu

Hui Wang

Leibo Liu

Tsinghua University

Jie Han

University of Alberta

Honglan Jiang

ADAPT: An Algorithm-Hardware Co-Design for Spiking Transformer with Training-Free Adaptive Token Pruning and Hierarchical Sparsity

Research Manuscript

1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionSpiking neural networks (SNNs) represent a promising solution for emerging architectures due to high sparsity and low power consumption. Spiking Transformers extend these advantages to attention-based modeling and show strong potential for energy-efficient applications. However, their practical deployment remains difficult. Spiking transformers demand substantial computation and memory access because of long token sequences and heavy workloads in feed-forward networks. Moreover, existing sparse optimization methods provide limited benefit for spiking transformers since they either focus only on unstructured bit-level sparsity or require model retraining. This work presents ADAPT, an algorithm–hardware co-design that exploits the hierarchical sparsity of spiking transformers. At the algorithm level, we propose Adaptive Token Pruning (ATP), a training-free method that evaluates token diversity and spike activity to remove redundant tokens. At the hardware level, we design a hierarchical-sparse accelerator that introduces a block-sparsity compression format and a pattern processing unit to leverage repeated bit patterns inside non-zero blocks. Experiments on multiple spiking transformer models demonstrate that ATP prunes 50\% of tokens with negligible accuracy loss. The ADAPT accelerator achieves average speedups of 3.1x and 4.2x over state-of-the-art SNN accelerators Prosperity and GPU, while reducing energy by 1.9x and 149.4x. These results show that exploiting hierarchical sparsity with algorithm–hardware co-design enables efficient deployment of spiking transformers.

People

Pinfeng Jiang

Yilong Fang

Letian Wang

Yi Wang

Mingde Zhu

Xiangshui Miao

Xingsheng Wang

Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification

Engineering Presentation

1:45pm - 2:00pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionAs chip complexity reaches tens of billions of transistors, standard cells are duplicated millions of times, making fast and accurate high‑sigma verification essential. Fixed‑sigma approaches are no longer viable. Each cell requires a flexible sigma target to avoid redesign and to enable yield‑based repurposing rather than discarding.
We present a fully automated, AI‑driven methodology that verifies an entire standard cell library in a single pass. Adaptive AI tailors verification jobs to individual cells, while Additive AI iteratively refines models across multiple PVT and input‑vector conditions, delivering brute‑force‑level accuracy without additional simulations.
The Worst‑Case Yield Solver (WCYS) identifies near‑target and worst‑case samples in the Solido PVTMC Verifier, builds predictive models, and triggers a reinforcement‑learning‑based High‑Sigma Verifier only when sign‑off criteria demand. Dynamic Constraint Yield Sign‑off (DCYS) automatically sweeps failing‑cell constraints until they pass, reducing the number of failed cells by 2.4×.
Compared with traditional scaled Monte‑Carlo methods, the proposed flow achieves a ten‑fold speedup, a tighter confidence interval (6.000 [5.900–6.098] vs 6.180 [5.067–7.146]), and a 60 % reduction in cells failing between 0.5 V and 0.6 V. This AI‑enabled verification provides 6‑sigma‑level confidence across massive libraries while substantially reducing verification time and resource consumption.

People

Engineering Poster

Adaptive Multi-Agent Framework for Automated Constraint Generation

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern semiconductor design demands managing diverse constraints-- timing, power, CDC, RDC, UPF-- across multiple EDA flows. Manual writing, scripting and validation of these constraints is slow, error-prone, and inconsistent.

We propose a multi-agent, debate-driven system--orchestrated by GitHub Copilot-- to transform this process into intelligent automation. The system orchestrates constraint generation and validation through a structured refinement loop: Generate, Critique, Debate, Human-Feedback and Evolution. The system becomes an expert that understands our silicon context by integrating human expertise into an adaptive feedback loop-- rapidly prioritizing corrective actions based on real-time violations. Advanced context engineering methodologies like RAG, RLHF, and MCP ensure consistent context management for the agents and effective constraint generation across diverse tool environments.

This approach accelerates signoff, reduces errors, and scales seamlessly across heterogeneous constraint domains-- paving the way for intent-driven, intelligent design methodologies.

People

Research Manuscript

Adaptive Multiply-Accumulate Unit with Scalable Critical Path for Aggressive Voltage Underscaling DNN Accelerators

3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionDeep neural network (DNN) accelerators have been investigated for efficient inference. Underscaling the supply voltage of MACs can effectively reduce the power dissipation. In this paper, we propose a bit-width adjustment circuit (denoted as ADA) for arbitrary MAC unit under aggressive voltage underscaling. Incurring 16% area overhead, the proposed ADA enables a MAC array to achieve zero accuracy loss. While preserving accuracy, the MAC array equipped with ADA achieves up to 48% power reduction compared to that without ADA. Furthermore, we propose ADA-Plus to optimize the MACs in output stationary systolic arrays, which reduces the area of ADA by 23%.

People

Tongjing Wu

Siting Liu

Tong Li

Hui Wang

Zhigang Mao

Jie Han

University of Alberta

Honglan Jiang

Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks

Engineering Presentation

2:45pm - 3:00pm PDT Wednesday, July 29 Seaside Ballroom A

EDA

Systems

DescriptionThis work presents a reinforcement learning (RL) approach to optimize System-on-Chip (SoC) performance by automatically tuning Quality of Service (QoS) knobs. As SoC complexity increases, manual optimization of diverse QoS parameters across varying scenarios becomes intractable. To address this, we develop a simulation environment mimicking the SoC, where an RL agent explores the design space to identify optimal knob settings. We employ Deep Q-Networks (DQN) and enhancements (e.g., Double DQN, Dueling Networks) within a Markov Decision Process (MDP) framework, defining states, actions, and reward systems based on key metrics like throughput, latency, and power. Techniques such as Temporal Difference (TD) learning and Prioritized Experience Replay (PER) improve sample efficiency and convergence. Our framework rapidly evaluates configurations under different SoC architectures. Experimental results demonstrate the RL model's ability to discover high-performance, power-efficient QoS settings through training, significantly improving over manual methods. This work highlights RL's potential in automating SoC design optimization, offering a scalable solution for complex multi-master systems and paving the way for future design automation research.

People

Research Manuscript

Adaptive Read Retry Table Extension for Enhanced Data Reliability in 3D NAND Flash Memory

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

Description3D NAND flash is widely used from PCs to data centers, but its major weakness is data reliability. As data is retained, charge leakage causes read errors. Vendors mitigate this using the read retry mechanism, which iteratively applies predefined read reference voltage combinations, called read retry parameters (RRPs), stored in a read retry table (RRT). However, the limited number of RRPs can lead to RRP burnout, a condition where all read retry parameter entries have been exhausted without successful data recovery.
In such cases, the data becomes undecodable and the corresponding block is marked as bad, degrading both capacity and lifetime of the NAND flash. Experiment showed that even a small portion of recovey failures may lead to significant capacity loss. We propose an Adaptive RRT Extension framework, integrating two key mechanisms: WL-Aware Interpolated Retry (WIR) and Multi-Dimensional Guided Retry (MDGR), to expand recovery capability. Experiments show that our method recovers up to 99\% of failed pages and preserves up to 99\% and 84\% of usable capacity under 12- and 30-month retention, respectively—where the baseline retains only 90\% or reaches end-of-life.

People

Han-Yu Liao

National Taiwan University and Innodisk Corporation

Chen-Xing Chang

Innodisk Corporation

Jen-Wei Hsieh

National Taiwan University of Science and Technology

Hung-Pin Chen

Innodisk Corporation

Yuan-Hao Chang

Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks

Research Manuscript

2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionProviding deterministic timing guarantees, beyond merely optimizing the accuracy-latency trade-off, is a mandatory yet unaddressed challenge for ultra-low-power spiking neural networks (SNNs) in resource-limited, safety-critical systems. In this paper, we propose RT-SNN, a novel adaptive SNN methods that integrates a system-level scheduling framework for SNN-based multi-object detection that, for the first time, co-optimizes inference accuracy while providing these strict timing guarantees. RT-SNN orchestrates SNN inference at both frame and timestep levels, introducing flexible timestep control and a novel membrane potential reuse mechanism to enhance accuracy without increasing latency. Evaluations on the KITTI dataset show that RT-SNN significantly improves the accuracy and energy efficiency compared to both state-of-the-art SNNs and traditional ANNs. Furthermore, a case study on a ROS-based F1/10 autonomous vehicle testbed demonstrates its real-time efficacy, validating its practical deployment in safety-critical systems.

People

Donghwa Kang

Korea Advanced Institute of Science and Technology (KAIST)

Woojin Shin

University of Seoul (UOS)

Cheol-Ho Hong

Chung-Ang University

Byunghoon Kang

Korea Advanced Institute of Science and Technology (KAIST)

Jinkyu Lee

Yonsei University

Hyeongboo Baek

Department of Artificial Intelligence, University of Seoul (UOS)

Additional Meeting

Additional Meeting - Accellera Luncheon: Embracing AI for Advanced Design and Verification

12:30pm - 1:45pm PDT Tuesday, July 28 Mtg Room 104C

DescriptionJoin Accellera for a dynamic luncheon exploring how artificial intelligence is reshaping the standards landscape for design and verification. As AI and machine learning are increasingly integrated into EDA workflows—from design generation to verification and system-level optimization—new challenges are emerging around interoperability, data exchange, trust, and reproducibility.

This session will highlight key areas where standards can enable scalable innovation, including AI-driven methodologies, training data availability, safety and security considerations. Attendees will gain forward-looking insights from industry experts and have the opportunity to share perspectives on where standardization is most needed across industry and academia.

Seating is limited and will be offered on a first-come, first-served basis.

People

Additional Meeting

Additional Meeting - CEDA Lunch: The Role of Open-Source Hardware in AI for EDA

12:00pm - 1:30pm PDT Tuesday, July 28 Mtg Room 104B

DescriptionSemiconductors have enabled today’s AI, and continued progress in AI will remain tightly coupled to advances in semiconductor hardware. This hardware is becoming increasingly specialized and heterogeneous, from accelerator-rich system-on-chip (SoC) devices to chiplet-based systems in advanced packages. At the same time, growing design complexity threatens this progress, as engineering and verification effort continues to rise and the semiconductor industry faces a persistent workforce gap. Agentic AI is expected to help address this challenge by boosting design productivity through a new class of EDA tools. Yet major obstacles remain. Hardware design is intrinsically different from software development, and many of the high-quality design artifacts, datasets, and workflows needed to train, evaluate, and validate AI-based methods are proprietary. Building on my experience developing ESP, an open-source platform for heterogeneous SoC design, this talk makes the case that open-source hardware is a key enabler for effective AI for EDA. By providing shareable artifacts, reproducible evaluation, and collaboration at scale across universities, government labs, and industry, open-source hardware can accelerate the development and validation of agentic AI workflows, while fostering curriculum innovation to train the next generation of hardware engineers and EDA tool developers.

People

Luca Carloni

Columbia University

Engineering Poster

Advanced Automation for DC Die Generation and Verification

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionA Daisy Chain (DC) die replicates the final package design mechanically to evaluate Board Level Reliability (BLR) and die-package interface. Typically the daisy chain die is created manually with some automation enabled for signal or ground routes. In case of package iterations, this causes rework especially depending on the ground bump pattern.

The paper looks at a semi-automated method to make the daisy chain connections thereby reducing manual effort and an automated way to confirm the integrity of the package-die connection. Using the proposed method the daisy chain die creation has been reduced from a couple of days to a couple of hours. The integrated checks also help catch real shorts if present on the package removing the need for manual review.

People

Engineering Presentation

Advanced Automation Framework for Clock and Reset Management in SoC Designs – Bridging Design Intent, Verification, Test and Implementation

10:30am - 10:45am PDT Wednesday, July 29 Seaside Ballroom A

EDA

Security

DescriptionAbstract
• Modern SOCs typically have dozens of clock domains, multi‑phase clock‑generation structures and dividers, complex reset-architecture and numerous exception constraints. This information must be handled consistently from RTL design to verification (DV) testbenches, DFT clock/reset architecture and finally to the timing constraints used for physical‑design implementation. Current practices rely on manual extraction of clocking, constraints and reset data from multiple documents, leading to long turnaround times, human error, and fragmented management of inconsistent data.
• This paper presents an advanced automation framework that is built on a Template Clock & Reset Management (CRM) document defined for a given family of devices. It generates timing constraints as well as the verification testcases from the CRM document, leveraging a lightweight parsing engine. The framework automatically generates UVM‑compatible DV testbench components (clock drivers, reset sequencers) and timing constraint files (source and generated clock definitions, case analysis, exceptions like multicycle path, false path, clock groups, etc.), ensuring strict traceability between design intent, verification, test and implementation. The automation framework also generates the DFT clock planner directly from the functional clock planner, which derives test frequency, test clock domains, shaping ICG creation and DFT overrides test structures ensuring error-free DFT RTL for higher quality, fewer iterations, and faster pre-silicon verification.

Motivation
• Increase productivity and reduce human error – By consolidating all clock, reset and exception related metadata (clock definitions, MCP entries, exception rules, reset ordering) into a single, version‑controlled document, the same data can be consumed automatically by scripts that generate DV test‑bench components, DFT clocking planner and PD constraint files. This eliminates repetitive iterations and ensures that any change is reflected everywhere instantly.
• Establish a single source of truth – A centrally maintained document provides traceability and auditability. Designers can track who modified a clock parameter, when it was changed, and what downstream artefacts were regenerated, supporting robust change‑impact analysis. It also enforces strict alignment between functional and DFT clock domain plans by streamlining DFT clocking to ensure DFT clocks follow related functional clocks. This in-turn helps in reducing any DFT timing overheads.
• Accelerate timing closure – Automated generation of SDC constraints, DFT case analysis and exception scripts shorten the PD flow, while automatically produced UVM‑compatible clock drivers and reset sequencers speed up verification. Early detection of mismatches between design intent and implementation reduces the risk of late‑stage bugs.
• Demonstrated maturity and extensibility – The tool has already evolved through multiple releases (e.g., addition of clock‑mode columns, MCP value fields, reset‑polarity handling, and auto‑generation flags), highlighting continuous improvement and real‑world applicability of template. Once the updates are made, all downstream collaterals can be updated using scripts which saves a huge chunk of effort across all domains, while maintaining high quality standards.
• Facilitate collaboration across domains – Because the document template is editable by both verification and physical‑design engineers, it encourages cross‑team communication and aligns expectations early in the design cycle.
• Create a foundation for future enhancements – With the data model in place, extensions such as power‑aware clock gating, dynamic frequency scaling, or integration with a broader "SOC timing data hub" can be added with minimal effort.

People

Suganthi VadivelMurugan

Engineering Presentation

Advanced Hard IP Integration Requirement Extraction and Checker

2:15pm - 2:30pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionMotivation: In SoCs 3rd party and TI internal hard IPs such as PHY, PLL, Dividers, etc are often required and integrated. An integration and specification document is often shared which contains the intricacies to be taken care during implementation. However, the integration requirements are often scattered across multiple pages, embedded on figures/tables, etc. The current manual approach of extracting, reviewing, and translating these requirements into actionable checklists is time-consuming and error-prone. The requirements can be scattered across different documents too. Eg ODP and efuse controller are expected to be in the same power domain but, the requirement is present in the fusefarm document and not in the ODP document. These need to be clubbed together and might be missed unless the user has read all documents.

Solution: An AI based automated approach in two phases. Phase 1 leverages AI-based document parsing to intelligently extract and categorize integration requirements into multiple categories - floorplan, IR, timing, placement etc. with automatically correlating cross-document dependencies. Phase 2 employs AI to translate these requirements into automated TCL-based checkers and where feasible, provide TCL based fix coding scripts.

Impact: The Physical Design (PD) team emerges as the most significant beneficiary of this AI-powered solution, as they are directly responsible for implementing majority of integration requirements extracted from specification documents. Experimental validation across various design integration documents have shown significant time saving up to 2 weeks and zero requirement omission rates, making it a scalable solution.

Future scope: While the current system requires prompt refinement and domain expertise for evolving IP types and documentation formats, future enhancements will incorporate automated prompt optimization to minimize specialist dependencies.

People

Mili Johnson

Ben Thomas

Kavithaa Rajagopalan

Pankaj Talwar

Advanced Hard IP Integration Requirement Extraction and Checker

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

People

Mili K Johnson

Ben Thomas

Kavithaa Rajagopalan

Digital Verification Manager

Pankaj Talwar

Research Special Session

Advanced Packaging: From Concept to Deployment

1:30pm - 2:00pm PDT Monday, July 27 Mtg Room 201A

Systems

DescriptionAdvanced packaging is deployed with increasing frequency to support heterogenous integration, chiplet design strategies, and enablement of large SOCs. For AI applications in particular, it is the only way to integrate the large compute silicon area and high memory capacity and bandwidth required for competitive products. This talk will review the usage of advanced packaging technologies in AMD products across various families, with an emphasis on AI products such as the AMD Instinct™ MI300, which blends 3D hybrid bond logic die stacking, 2.5D interposers, and HBM into a single SOC. Trends observed in AI products are then used to project the evolution of advanced packaging technologies, including finer pitch scaling, continued growth in module size, and increasing power delivery and thermal demands. These trends will finally be connected to design and test strategies. As cost and complexity grow, creating manufacturing flows that allow accurate screening at multiple steps in the process to ensure good yield and quality are an essential part of 'Design-Technology Co-optimiziation' (DTCO). Successful products will require careful consideration of test methods in every chiplet and at every step of the manufacturing flow.

People

Bill Lambert

Advancements in Heterogeneous Integration and 3D Packaging for Next-Generation Scalable Photonic Integrated Systems

Research Special Session

2:30pm - 3:00pm PDT Wednesday, July 29 Mtg Room 201A

EDA

DescriptionIn this talk, AIM Photonics presents advances in heterogeneous integration and 3D packaging within 300 mm silicon photonics at the Albany Nanotech Complex. We highlight results from laser integration on PICs using 2.5D and monolithic bonding, offering dense integration capabilities. The talk also covers 3D co-packaged optics (CPO) architectures that lead to large gains in optical interconnect efficiency and bandwidth. Finally, we discuss unique features of our design automation offerings, including feature-rich photonic PDKs and Assembly Design Kit, enabling efficient, accurate circuit design and packaging. These innovations address key challenges in manufacturability, scalability, and yield for next-generation photonic AI systems.

People

David Harame

AIM Photonics

Research Special Session

Advances in AI-Driven Hardware Code Generation: Insights from the Comprehensive Verilog Design Problems Benchmark

3:30pm - 4:00pm PDT Monday, July 27 Mtg Room 201A

DescriptionAI-driven hardware code generation, across both frontier LLMs and emerging agentic workflows, is advancing rapidly, yet it still trails the maturity of AI-driven software development. High-quality benchmarks are essential for catalyzing progress, revealing capability gaps, and guiding the development of new methodologies. The Comprehensive Verilog Design Problems (CVDP) benchmark, now adopted by the Silicon Integration Initiative's LLM Benchmarking Coalition, provides a foundation for evaluating these capabilities within the broader silicon design community. We survey the evolving landscape of language models and agentic systems for hardware design, examining their performance on RTL generation, testbench creation, debugging, and related tasks through the lens of CVDP. We highlight emerging trends, persistent challenges, and key opportunities for advancing trustworthy and automation-ready hardware design flows.

People

Nathaniel Pinckney

NVIDIA

Engineering Poster

Advancing CDC Formal Verification in Low-Power SoCs Using Power Intent and Smart Waiver Techniques

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIncorrect clock domain synchronization can cause critical functional bugs in SoCs, potentially requiring costly fixes. When low-power requirements with multiple switchable power domains are involved, CDC verification becomes more complex. In UPF-based low-power designs, isolation cells at power domain boundaries preserve signal integrity but may cause resynchronization issues if their enable signals are improperly synchronized, leading to metastability or failures. The presence of isolation cells, retention registers, and their enable signals increases the number of asynchronous paths to analyze.
This paper proposes a new flow based on formally proven' smart waiver CDC jointly with LPV that drastically reduces the number of CDC and RDC violations to analyze in a typical ultra-low-power SoC. Normally, the number of violations can be several hundred, but this flow safely waives those proved true through formal verification. The remaining violations can then be analyzed to uncover real resynchronization bugs.
In the presented test case, the number of violations to analyze was reduced by about 35%, enabling the discovery of bugs that might have been lost among the initial hundreds of violation reports. Formal verification remains the optimal method for CDC checking, and Jasper CDC with LPV enables power-aware CDC verification using UPF

People

David Vincenzoni

Erik Seligman

Greg Milano

Ran Zhao

Advancing Macro Placement: Integrating Proven Design Practices with Reinforcement Learning

Research Manuscript

5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionMacro placement is a critical stage in physical design, directly impacting the quality and performance of VLSI circuits. We propose a reinforcement learning (RL)-based macro placement framework that integrates proven design practices through a design-practice-embedded action mask, including peripheral placement, dead space avoidance, and proximal placement for macros with shared design hierarchy and physical footprint. Unlike previous RL based methods, our method uses macro clusters-formed according to design hierarchy and physical footprint-as the basic placement units, which reduces placement steps and consequently accelerates convergence and improves runtime. The proposed framework also introduces a novel compaction method to minimize wasted area caused by grid granularity, and jointly optimizes macro cluster location and tiling pattern for more effective exploration. Experimental results show that our approach achieves expert level placement quality and consistently outperforms three leading commercial macro placers on industrial designs, with reduced turnaround time. On public benchmarks, our method achieves up to 25.37% and 39.51% improvements in worst negative slack (WNS) and total negative slack (TNS), respectively, over five state of the art (SOTA) placers. These results demonstrate the effectiveness and real-world applicability of our RL based framework, paving the way for further advancements in physical design automation.

People

Engineering Presentation

Advancing Silicon Lifecycle Management with Embedded Trace

4:00pm - 4:15pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionSilicon Lifecycle Monitoring (SLM) addresses the lifetime silicon health and reliability challenges from early life to end of life. While ATPG based structural tests are very effective at detecting manufacturing defects there are many other complex failure mechanisms that manifest during operational lifetime and require in-field debug and continuous monitoring. The root cause of such failures are latent manufacturing defects, IR Drop, leakage currents, thermal effects, soft errors, and aging – many of which fall into the category of silent data corruption (SDC). Functional failures often manifest as program misbehavior that impact large scale deployment of highly connected systems such as web servers, 5G base stations, automotives and AI/ML processors.
We describe an SLM solution that uses an embedded trace system as its foundation. This collects time stamped data to analyze the trajectory of the transactions involving the CPU, memory, I/Os, peripherals, and other sub-systems. Trace data is highly compressible (up to 700 X) and can be easily stored in system or offloaded for analysis that executes in less than 165 milliseconds for these programs. Results on an industrial benchmark (for RISC-V CPUs) and an AI Inference engine silicon case study demonstrate the value and effectiveness of this approach.

People

Research Manuscript

Agent-Per-Qubit: Automated Qubit Placement for Fault-Tolerant Quantum Computing

2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionQuantum computing holds the potential to revolutionize numerous fields, yet the practical execution of quantum circuits depends on an efficient compilation process, including the placement of logical qubits on a quantum chip. This placement is a hard combinatorial problem that often defeats traditional heuristics and manual optimization. We present QAgent, a novel multi-agent reinforcement learning (RL) framework that autonomously optimizes logical qubit layouts on quantum processor. In QAgent, one agent is assigned to each logical qubit, and agents jointly learn placement policies that minimize circuit execution cost. To address the challenges of sparse rewards and credit assignment, we propose the Breakthrough Return Bonus (BRB), a dynamic reward shaping mechanism that encourages meaningful layout improvements and accelerates convergence. Extensive experiments on diverse quantum circuit benchmarks show that QAgent reduces execution costs by up to 53.9% compared to leading approaches, and significantly enhances circuit success rates. Ablation studies confirm that BRB is essential for stable training and effective policy optimization. These results demonstrate the promise of AI-driven, workload-aware placement for advancing fault-tolerant quantum computation.

People

Tian Li

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Yang Wang

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Tan Li

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Wan-Su Bao

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Analyst Presentation

Agentic AI and Friends: Why Everyone Suddenly Wants CPUs Again

10:15am - 11:00am PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

DescriptionLearn More in the DAC Pavilion!

People

Dr. Ian Cutress

More Than Moore

Work in Progress

Agentic AI for Chip Design and Verification: Results and Limitations from CVDP

5:13pm - 5:14pm PDT Monday, July 27 Exhibit Hall

DescriptionWe benchmark a new agentic AI approach for chip design and verification on the CVDP dataset. Our results show that multi-agent orchestration, custom system prompts, and improved tool-use guidance enable our agent to debug and complete substantially more complex hardware verification problems. On relevant CVDP problems, our agent demonstrates a relative advantage of 11.6% vs. CVDP state of the art performance and 15.3% vs. Claude Code. Beyond aggregate metrics, we analyze execution traces and find evidence of enhanced reasoning and debugging capabilities, as well as important limitations of under- and over-specified test harnesses.

People

DAC Pavilion Panel

Agentic AI in EDA: Who's in Control?

4:00pm - 4:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

DescriptionAbstract: EDA is on the brink of its most disruptive transformation yet. Agentic AI—multi-agent systems capable of autonomous, goal-driven decision-making—promises to move beyond assistive point solutions toward orchestrating entire design flows. From synthesis and verification to physical design and system optimization, these agents could redefine productivity and complexity management. Yet as autonomy grows, critical questions emerge: Who—or what—is really in control?

This panel will explore the technical, organizational, and ethical tensions surrounding agentic AI adoption. We’ll examine infrastructure and governance: securing sensitive IP and maintaining compliance when autonomous agents operate across hybrid environments. We’ll discuss interoperability and standards: for example, Si2’s AI/ML EDA ontology provides a standardized representation of design terminology and relationships, bridging graph representations, ML datasets, and tool semantics to enable agents to reason about workflows. Such efforts highlight both the promise and the challenge of enabling multi-vendor collaboration without fragmenting the ecosystem. Finally, we’ll confront trust and accountability: how do we reason about correctness, explainability, and oversight when design decisions emerge from interacting agents rather than deterministic scripts?

The discussion will surface points of disagreement across the ecosystem, including how much autonomy is desirable, which risks are acceptable, and whether current infrastructures and standards are sufficient. Attendees will leave with a clearer understanding of the readiness of agentic AI, practical tensions it raises, and open questions shaping its future adoption.
Watch for Si2 DAC updates!

Moderator:
Leigh Anne Clevenger | VP Technology | Si2

Speakers:
Natesan Venkateswaran | Program Director, EDA Analysis | IBM
Lindsey Kostas | Principal/Manager ML Research | Qualcomm
Ivan Kissiov | Principal Engineer | Siemens EDA
Srinivas Bodapati | Technical Leader-Pre-Silicon Design Risk Mitigation | Nvidia
Da Yang | Senior Director | Nvidia

People

Natesan Venkateswaran

Engineering Poster

Agentic AI Partition And Floorplan Assistance For PCIe/CXL Subsystem Physical Design

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe deployment of advanced high-speed protocols (e.g., PCIe Gen6/CXL) in multi-billion-gate designs creates a severe "Logical-Physical Gap," where traditional implementation flows suffer from unmanageable runtimes and convergence volatility. This work introduces a novel Cognitive Agentic Framework that orchestrates multi-objective partitioning and semantic-driven floorplanning to bridge this divide. Unlike conventional methodologies relying on blind min-cut algorithms or static placement rules, our approach utilizes HGNN to predict physical feasibility during logical partitioning, optimizing for size balance, boundary timing, and data stream integrity. Furthermore, we propose Dataflow-Driven Vision-Language Reinforced Semantic Floorplanning, where a Large Multimodal Model functions as a "visual perception sensor" within a physics-based force field. This allows the agent to iteratively "see" congestion hotspots and dynamically adjust repulsion forces to enforce semantic consistency. By embedding physical awareness into the architectural phase, our framework reduces the design iteration cycle, achieving superior PPA metrics and deterministic timing closure compared to standard industrial flows.

People

yuwenyuan gao

Agentic Time-Travel Debugging for HLS Code

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionHigh-Level Synthesis (HLS) code is often developed using a subset of C/C++, along with specialized libraries. This allows HLS engineers to make use of standard software engineering tools and techniques during the development and debug phase of their project. This talk introduces the topic of time-travel debugging, whereby the state of a design can be examined by going backwards and forwards in time. This approach saves huge amounts of effort, allowing the root cause of bugs, including challenging concurrency bugs, to be found with ease and a new codebase to be understood rapidly.
Beyond this, we will look at how you can connect the latest AI models to the time-travel debugging tools to enable Agentic Time-Travel Debugging capabilities to verify hypotheses and predictions against authoritative records of what did happen during execution, closing the loop to allow the AI Agents to iterate and improve their diagnosis of behaviour until they get a verified root cause diagnosis of issues during development and simulation. It is also possible to generate waveforms from the recordings and report detailed root cause explanations, using waveforms and language that potentially explains complex software issues to hardware developers generating or using the HLS models.

People

Jonathan Bonsor-Matthews

LightBlue Logic

Research Manuscript

Agenticdse: A Multi-Agent Design Space Exploration Framework with Multi-Phase Bayesian Optimization for Chiplet Accelerators

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionChiplet accelerators offer a scalable solution for LLM inference with reduced manufacturing costs. However, the design space exploration (DSE) of chiplet accelerators is challenging due to the complex design space. Prior black-box Bayesian optimization (BO) solutions lack domain knowledge, limiting their effectiveness. In this work, we propose AgenticDSE, a multi-agent DSE framework that incorporates the collaboration of three LLM agents, i.e., exploration orchestrator, architecture analyst, and optimization engineer. This multi-agent framework enhances exploration efficiency through analysis-driven design space refinement and phase-wise design exploration using ensemble surrogate modeling. Over the same number of explorations, AgenticDSE achieves up to 36.9% reduction of average distance to the real Pareto front, and 66% increase in diversity of explored Pareto front compared to state-of-the-art DSE solutions. Additionally, it offers scalable performance with 46x and 18x reduction in input and output token consumption compared to prior LLM-based solutions.

People

Engineering Poster Gladiator

Agile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts

2:33pm - 2:45pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionCo-packaged optics (CPO) presents unique physical design challenges: numerous small blocks with irregular shapes to accommodate photonics and analog integration, combined with frequent RTL changes extending close to tapeout due to evolving system architectures of cutting-edge silicon photonics design. Traditional manual PD flows widely used in the industry cannot sustain rapid iteration requirements while maintaining team scalability. We present a production-grade GitOps-based PD orchestration framework that treats PD recipes as version-controlled code, enabling automated synthesis through signoff with CI/CD integration. Our framework leverages YAML/Jinja configuration templates, parallel multi-block execution, commercial LLM APIs enabled with EDA tool docs, and human-in-the-loop validation via automated QoR regression and Slack notifications. Deployed at Lighmatter, a fabless CPO company, this system enabled a team of fewer than 10 PD engineers to successfully deliver multiple test chips and product tapeouts with boosted productivity compared to industry baselines, while seamlessly absorbing RTL changes in the final two months before tapeout. Beyond immediate productivity gains, this infrastructure establishes the data collection and execution framework necessary for AI-agent-assisted PD optimization, providing auditable run histories and structured metrics that serve as training data for autonomous design exploration.

People

Research Manuscript

AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices

11:23am - 11:36am PDT Wednesday, July 29 Mtg Room 101A

AI4-I. AI/ML Architecture Design

DescriptionSpeculative decoding enhances the inference efficiency of large language models (LLMs) by generating drafts using a small draft language model (DLM) and verifying them in batches with a large target language model (TLM). However, adaptive drafting inference on a mobile single-NPU-PIM system faces idle overhead in traditional operator-level synchronous execution and wasted computation in asynchronous execution due to fluctuations in draft length. This paper introduces AHASD, a task-level asynchronous mobile NPU-PIM heterogeneous architecture for speculative decoding. Notably, AHASD achieves parallel drafting on the PIM and verification on a single NPU through task-level DLM-TLM decoupling and specifically, it incorporates Entropy-History-Aware Drafting Control and Time-Aware Pre-Verification Control to dynamically manage adaptive drafting algorithm execution and pre-verification timing, suppressing invalid drafting based on low-confidence drafts. Additionally, AHASD integrates Attention Algorithm Units and Gated Task Scheduling Units within LPDDR5-PIM to enable attention link localization and sub-microsecond task switching on the PIM side. Experimental results for different LLMs and adaptive drafting algorithms show that AHASD achieves up to 4.2× in throughput and 5.6× in energy efficiency improvements over a GPU-only baseline, and 1.5× in throughput and 1.24× in energy efficiency gains over the state-of-the-art GPU+PIM baseline, with hardware overhead below 3% of the DRAM area.

People

Zirui Ma

zhihua fan

Institute of Computing Technology, Chinese Academy of Sciences

Wenxing Li

Haibin Wu

State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences

Engineering Special Session

AI and Multi‑die: A Reinforcing Cycle

10:30am - 12:00pm PDT Wednesday, July 29 Seaside RM 7

Chiplet

Design

EDA

DescriptionThe convergence of AI and multi‑die architectures is reshaping the fundamentals of compute efficiency. Near‑memory and in‑memory processing—enabled by advanced non‑volatile memory technologies—reduces data movement and latency, accelerating AI workloads at their source. Cost‑effective multi‑die integration unlocks scalable performance without escalating silicon expense, fueling innovation from edge devices to hyperscale cloud.

Automotive‑grade AI raises the bar further, requiring multi‑die reliability that meets rigorous functional‑safety demands. Sustainability pressures drive advances in interconnect efficiency, power‑aware partitioning, and intelligent storage hierarchies across AI–multi‑die systems. Collectively, these trends point toward a future where heterogeneous integration and intelligent compute evolve in tandem, delivering new levels of performance, robustness, and environmental efficiency.

People

Engineering Special Session

AI for Specifications Across the Stack: Formalization, Alignment, Reconstruction, and Handoff

3:30pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionSpecifications remain the foundation of silicon development, yet they suffer from systemic problems that compound across the stack. This talk addresses four critical challenges: (1) Formal vs. Informal Specs: Natural language specs create ambiguity, contradiction, and drift. AI enables incremental formalization - translating high-value sections into machine-readable formats while keeping specs accessible. (2) Living Documents vs. Snapshots: Specs diverge from implementation almost immediately. AI-powered drift detection and spec-as-code practices can keep specs aligned with reality throughout the development lifecycle. (3) Spec Archaeology: Legacy IP, acquisitions, and lost documentation create integration risk. AI can reconstruct specs from RTL/firmware and surface undocumented assumptions from tribal knowledge sources. (4) Cross-Company Interfaces: Specs crossing organizational boundaries become contractual documents where ambiguity has legal and financial consequences. Structured, AI-validated specs reduce handoff risk with IP vendors, OSATs, and customers.

People

Erfan Rostami

Co-Founder and CTO of Voltai

Welcome Address

AI Supercomputing Meets EDA: Accelerating the Future of Chip and System Design

5:00pm - 5:45pm PDT Sunday, July 26 Mtg Room 104B

EDA

DescriptionA new era is emerging where AI supercomputing and EDA come together to redefine what is possible in chip and system design. Accelerated computing, foundation models, and intelligent design flows are transforming every stage of the journey, from architecture and verification to deployment in complex, secure systems. As AI, Design, EDA, Security, and Systems converge, design cycles can shrink, chiplet-based and future quantum-ready platforms can become practical, and human creativity can be amplified. This keynote explores how collaborating with AI at scale can unlock breakthrough performance, faster innovation, and a new generation of chips and systems that power the world’s most ambitious ideas.

People

Timothy Costa

NVIDIA

Engineering Poster

AI‑Assisted Formal Verification: Improving Practical Adoption and Scalability

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs chip complexity continues to grow, shift-left verification has become critical for improving verification efficiency and design quality. Formal Verification is a key enabler of shift-left adoption, as it provides exhaustive analysis and exposes corner case bugs early in the design cycle. Despite these advantages, many design verification (DV) teams struggle to adopt formal methods due to expertise gaps, scalability limitations, and the perceived difficulty of manual property authoring.

This presentation introduces a practical, AI-assisted roadmap for scaling formal verification across IP, subsystem, and SoC level designs. The approach combines early "quick win" formal applications (linting, UNR, connectivity) with scalable intermediate techniques (CSR, CDC/RDC, safety and security), and extends to advanced Formal Property Verification (FPV). Recent advancements in AI-assisted assertion generation, leveraging natural-language-to-property workflows, context-aware reasoning, and automated constraint derivation significantly reduce the manual effort required for FPV setup.

The methodology has been field tested across real design teams, demonstrating improved scalability, faster proof convergence, reduced assertion authoring effort, and higher overall adoption. Key complexity management techniques, including modularization, abstraction, and constraint strategies, are also discussed as essential enablers for deploying formal verification at scale in modern front-end verification flows.

People

Muhammed Luqman Jukaku

Ai&cell Based Analog Circuit Topology Generator(ctgen)

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis provides the new analog design methodology which will generates schematic topology for practical usage.
The abstract concept of topology generation is following.
Decompose the many circuits schematic resources to small cells or blocks.
Then construct for the best combination topology to meet the each specific target under spice simulation base optimization for block level architecture schematic. This design could be existing schematic but partially structured as blocks which internally build by connected between selectable libraries' cells or blocks.
Each cell and block are already validated and parametric , the final schematic is acceptable by designers.
This tool is independent from circuit categories and any process. The evaluations are from spice simulation under PDK from testbenches.
This may produce better combined circuit topology than depending on designers experiences or skill.
The key technologies of this tool are
1. AI searching method in huge combinatorial space which is used like Alpha-GO
2. Recent Machine learning algorithm for circuit parameter optimization
3. Dived the stage as learning and inference which scalable by machine resources
This will improve the reusability and improve migration efficiency equipped with topology changing.
The final design sign off could be done in current customers design environments.

People

Kyoto Institute of Technology

Nobukazu TAKAI

Kyoto Institute of Technology

Shigetoshi NAKATAKE

University of Kitakyushu

Tetsuya IIZUKA

The University of Tokyo

Engineering Poster

AI-Accelerated Optimization Flow for Robust Analog and Mixed-Signal Circuit Design Against Process Variation

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionEkepower is committed to developing chips for advanced printing technology. A key feature of these innovative chips is their integration of diverse circuit block functionalities into a single device. These include high-voltage motor and printhead drivers, precise timing references essential for the entire system, and RF sensor integration capable of detecting signals with extremely low voltage. Finding a universal simulation and verification platform that efficiently accommodates the unique requirements of different circuit blocks remains a significant challenge.

By leveraging integration with the Solido Simulation Suite and Solido Design Environment, users gain access to comprehensive analysis and accelerated performance compared to traditional workflows, without compromising accuracy. Additionally, AI-driven variation-aware feature enable thorough verification and identification of circuit distributions, facilitating the efficient creation of trimming plans to optimize both analysis and circuit performance.

Ekepower leverages this design flow to efficiently verify and optimize circuit blocks with varying properties simultaneously through transient, RF, and mixed-signal analysis, achieving speed improvements of up to 7.6x over conventional methods. Additionally, the AI-powered and automated trimming flow effectively optimizes circuit blocks, resulting in an overall reduction in top-level voltage variation.

People

Engineering Poster

AI-Accelerated Signoff Verification and Glitch Analysis for Single and Multibit Level Shifters

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionLevel shifters are critical for reliable cross-voltage domain communication: their failure risks the integrity of the circuit, excessive power dissipation, and damage to components. Extensive verification is required to mitigate their susceptibility to device variability and multiple failure mechanisms. Traditional brute-force Monte Carlo analysis is infeasible for evaluating all failure modes across large corner sets at advanced nodes, making accurate, timely verification challenging.

This paper introduces an AI-powered, high-throughput batch flow for fast, accurate signoff verification of single and multibit level shifter cells. Adaptive AI performs rapid identification of worst-case corners, which are then verified with AI-powered, brute-force accurate high-sigma technology. This precision deployment optimizes runtime and resources by running high-sigma verification only when necessary.

The proposed methodology demonstrates significant improvements over previous methods. 3σ single-cell validation was 3x faster than traditional brute-force Monte Carlo, and high-sigma verification precision deployment reduced overall runtime by 10x across 256 cells at 6σ. Targeted analysis validated glitch heights in multibit level shifters at 3σ and 6σ, with precision deployment reducing overall runtime by >14x. This AI-driven solution optimizes compute and engineering resources to provide timely, accurate guidance on reduced verification timelines, ensuring full-coverage functional robustness, improved silicon quality, and faster time-to-market.

People

Engineering Presentation

AI-Assisted EDA Tools Development

10:30am - 10:45am PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionEDA tool development often suffers from redundant effort and complexity due to repeated implementation of common HDL parsing and construction tasks. This work introduces an AI-assisted framework that leverages MCP modular building blocks and an Agentic AI approach to automate tool generation, eliminating the need for deep parser expertise. The proposed methodology collects user specifications and synthesizes EDA tools using reusable components. Applied to IBM structural verification tools, the framework demonstrated significant productivity gains - reducing development time from an estimated four person-weeks to under 30 minutes. The generated implementation required 1,110 lines of code, with approximately 90% reused across checks, ensuring scalability and maintainability. By automating repetitive tasks and enabling rapid deployment of new checks, this approach accelerates design workflows, improves reusability, and shortens time-to-market for EDA tools. The results highlight a transformative shift from manual coding to AI-driven synthesis, addressing inefficiencies and empowering design teams to focus on innovation.

People

Engineering Poster

AI-Driven Co-Optimization of Power Delivery Network for High-Power Cores in 2.5D Advanced Packaging

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe increasing adoption of chiplet-based 2.5D advanced packaging has introduced formidable power integrity (PI) challenges, requiring the simultaneous optimization of static DC performance and dynamic AC response—a complex, multi-variable task traditionally reliant on manual expertise. This paper presents an integrated, AI-driven workflow that fully automates the PI co-optimization process. For DC performance, the methodology automates the design of the interposer Power-Ground (PG) mesh. It leverages AI-based multi-objective optimization within Redhawk-SC to intelligently adjust metal patterns, directly minimizing IR drop while adhering to process design rules. For system-level AC performance, the workflow automates the selection and configuration of the hierarchical decoupling network. By combining HSPICE simulation with optimizers (optiSLang/ASO.ai), it co-optimizes components from die MIMCAP and interposer Deep-Trench Capacitors (DTC) to package decaps and PCB MLCCs, targeting impedance and noise reduction under constraints of cost, area, and assembly rules. This automated approach achieves a 26% reduction in DC IR drop and a 12% improvement in AC noise margin. Ultimately, it consolidates fragmented manual procedures into a unified flow, reducing the total PI optimization timeline from over three weeks to approximately one week, thereby enhancing design robustness and significantly accelerating time-to-market.

People

Exhibitor Forum

AI-Driven Design Automation for Analog and Mixed-Signal Circuit Design

4:00pm - 5:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionMove Silicon presents Spaceman, an AI-driven design automation toolchain developed to accelerate and optimize analog and mixed-signal circuit design. Seamlessly integrated with leading EDA environments, Spaceman automates sizing, optimization, and design-space exploration, dramatically reducing both time-to-market and engineering effort for IP and ASIC development. The goal is not to replace analog designers, but to augment their capabilities, enabling faster, smarter, and more scalable design methodologies for the next generation of semiconductors.
At the core of these results lies Move Silicon’s proprietary AI modeling technology, capable of autonomously training neural network models directly from a circuit schematic and its testbench. This approach enables highly efficient and virtually unlimited IP reuse, significantly improving design productivity and portability across projects and PDKs. Spaceman goes beyond simply identifying the correct sizing for a given specification. It shifts the paradigm from traditional SPICE-driven iterative workflows toward AI-driven predictive models, enabling immediate exploration, analysis, and forecasting of the entire design solution space for any IP.

People

Ferdinando Frediani

MoveSilicon

Engineering Presentation

AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design

11:45am - 12:00pm PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionAs semiconductor designs scale to billions of transistors, compute demands for electronic design automation (EDA) increasingly exceed the capacity of traditional on-premises infrastructure. Migrating workloads to hybrid or cloud environments offers scalability, but many organizations face inefficiencies in job provisioning, resource utilization, and scheduling accuracy. This work introduces AI Assist for EDA Cloud Optimization, a framework leveraging graph neural networks (GNNs) and reinforcement learning (RL) to forecast compute requirements and optimize workload execution across heterogeneous environments.

By analyzing job metadata from synthesis, placement, and verification stages, AI Assist predicts runtime and resource needs prior to submission—reducing overprovisioning by 60–80% and improving runtime completion speed by 20–40% in test deployments. The adaptive scheduling layer learns policies that balance cost, performance, and licensing constraints across hybrid compute environments.

Complementary modules—such as placement optimization and hotspot prediction—apply similar AI paradigms to design optimization and verification, demonstrating measurable improvements in PPA efficiency and iteration time. Together, these solutions illustrate how AI Assist enables semiconductor firms to modernize their EDA workflows securely and efficiently while accelerating design convergence in the transition to cloud-scale engineering.

People

Engineering Poster

AI-Enabled Flow for Silicon Area Reduction and Design Closure

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAbstract—Artificial Intelligence (AI) has emerged as a transfor-
mative technology in electronic design automation (EDA) flows,
enabling significant improvements in power, performance, and
area (PPA) metrics. This paper explores the critical role of AI-
driven techniques in optimizing semiconductor design processes,
highlighting how intelligent algorithms can automate decision-
making, predict optimal design parameters, and effectively re-
duce silicon area. By integrating AI into the design flow, users can
achieve enhanced PPA trade-offs, minimize manual intervention,
and accelerate time-to-market. The study demonstrates practical
methodologies and case studies illustrating how AI empowers
designers to optimize chip layouts, improve resource utilization,
and achieve superior silicon efficiency.

Index Terms—EDA, PPA, Artificial Intelligence, Floorplanning,
Silicon Area Reduction

People

Engineering Poster

AI-Enabled High-Fidelity Power Amplifier Behavioral Modeling with Commercial EDA Tools

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis paper presents an advanced AI methodology for building a high-fidelity power amplifier behavioral model using Keysight commercial EDA tools SystemVue and Advanced Design System (ADS), in conjunction with AI-enabled modeling techniques. The example device is a power amplifier circuit modeled within ADS, which a corresponding behavioral model is developed in form of a neural network. Training data for the neural network model is generated through co-simulation between SystemVue and ADS, ensuring consistency and accuracy. The resulting behavioral model not only achieves high modeling accuracy but also enables the characterization of transient circuit behavior and supports operation within a broad power range. Once developed, the model can be seamlessly imported into system-level simulation for performance verification and subsequent system-level design.

People

Lei Li

Yanhua Cui

Tong Li

Ziquan Bai

Fei Cao

AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization

Engineering Presentation

11:45am - 12:00pm PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionWhile 3D disaggregated chiplets are viewed as the future of chip design, the approach inherently has drawbacks in thermal performance. This is because some of the chiplets in a given 3D stack may not be in contact with a good heat sink. In traditional 2D design methodology, a good heat sink is usually assumed to exist, which allows thermal analysis to be deferred to the end of design cycle. In 3D disaggregate designs, however, we may not have the luxury of deferring thermal analysis, as thermal violations may not be fixable without contact to sufficient heat sink. Therefore, it is imperative to optimize for thermal behavior along with traditional performance, power, and area (PPA) metrics early in the design flow. In this work, we propose an AI-driven methodology to incorporate thermal-aware module placement that simultaneously optimizes for thermal and other PPA targets. This methodology automatically experiments with hundreds of thermal-constrained scenarios in heterogenous 3D chiplet stacks using AI-assisted analysis to achieve the best possible thermal and PPA results, while requiring minimal user guidance and intervention.

People

Xiaohu Xu

Sonia Beghum

Keshava Manimunda

AI-Native Workflows from Architecture to Production Readiness

Exhibitor Forum

4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionCustom ASIC development remains out of reach for many hardware companies. Traditional design services are expensive, timelines are long, and off-the-shelf chips often leave major cost, power, and performance on the table. Visibl is building AI-native workflows that automate large portions of chip development, from architecture and design through verification and production readiness. In this presentation, we will show how a software platform can help engineering teams move faster by reducing repetitive work, improving regression triage, and accelerating the path from product requirements to manufacturable silicon. The goal is not just better internal productivity, but making custom chip development accessible to robotics, drones, industrial, IoT, and edge hardware companies that have historically been priced out of the market.

People

Jordon Kashanchi

Visibl Semiconductors

Research Manuscript

Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch

12:15pm - 12:30pm PDT Wednesday, July 29 Mtg Room 202C

Systems

SYS3. Embedded Software

DescriptionEliminating undefined behaviors (UBs) in Rust programs requires a deep semantic understanding to enable accurate and reliable repair. While existing studies have demonstrated the potential of LLMs to support Rust code analysis and repair, most frameworks remain constrained by inflexible templates or lack grounding in executable semantics, resulting in limited contextual awareness and semantic incorrectness. Here, we present AkiraRust, an LLM-driven repair and verification framework that incorporates a finite-state machine to dynamically adapt its detection and repair flow to runtime semantic conditions. AkiraRust introduces a dual-mode reasoning strategy that coordinates fast and slow thinking across multiple agents. Each agent is mapped to an FSM state, and a waveform-driven transition controller manages state switching, rollback decisions, and semantic checkpointing, enabling context-aware and runtime-adaptive repair. Experimental results show that AkiraRust achieves about 92% semantic correctness and delivers a 2.15× average speedup compared to SOTA.

People

Renshuang Jiang

Yichong Wang

Pan Dong

National University of Defence Technology

Xiaoxiang Fang

Zhenling Duan

Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation

Zhe Jiang

South East University

Research Manuscript

1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES3. Emerging Models of Computation

DescriptionComplex-Valued Neural Networks (CVNNs) have significant advantages in handling tasks that involve complex numbers. However, existing CVNNs are unable to quantify predictive uncertainty. We propose, for the first time, dropout-based Bayesian Complex-Valued Neural Networks (BayesCVNNs) to enable uncertainty quantification for complex-valued applications, exhibiting broad applicability and efficiency for hardware implementation due to modularity. Furthermore, as the dual-part nature of complex values significantly broadens the design space and enables novel configurations based on layer-mixing and part-mixing, we introduce an automated search approach to effectively identify optimal configurations for both real and imaginary components. To facilitate deployment, we present a framework that generates customized FPGA-based accelerators for BayesCVNNs, leveraging a set of optimized building blocks. Experiments demonstrate the best configuration can be effectively found via the automated search, attaining higher performance with lower hardware costs compared with manually crafted models. The optimized accelerators achieve approximately 4.5× and 13× speedups on different models with less than 10% power consumption compared to GPU implementations, and outperform existing work in both algorithm and hardware aspects. The code will be open-source after acceptance.

People

Zehuan Zhang

Imperial College London

Hao (Mark) Chen

Imperial College London

Research Manuscript

ALOHA: Area-Efficient and Low-Power Stochastic Computing with Hammersley Sequences

4:42pm - 4:54pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionCounter-based stochastic computing (CBSC) utilizes simple counting logic to realize multiplication. Inspired by CBSC, this paper proposes the ALOHA architecture that significantly reduces the computing latency and stochastic number generation (SNG) overhead. Specifically, ALOHA incorporates three key innovations, including input scaling, bit-reversal counter-based SNG, and sequence-aware optimization schemes. Experimental results show that the ALOHA multiplier significantly outperforms state-of-the-art CBSC designs in terms of accuracy, area and power consumption with reduced sequence length. In CNN and Transformer inference, ALOHA matches the accuracy of prior FSM-based multipliers while reducing area and energy.

People

Zhaojun Ni

Yutao Gong

Honglan Jiang

Siting Liu

Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search

Research Manuscript

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionAnalog layout design remains heavily dependent on manual expertise, with placement being the most critical stage that requires significant development time and domain knowledge. Current automated placement techniques face challenges in capturing expert design practices and fall short of practical deployment. To address this limitation, we present AlphaPlacer, a novel MCTS-based analog placement framework that learns from historical layouts to provide expert-guided placement optimization.
Our approach formulates analog placement as a hierarchical sequence pair search with a two level MCTS structure, embedding a pretrain learning framework that captures sequence pair distributions from expert layouts to guide the search toward high quality solutions.
Experimental results demonstrate that our method significantly outperforms existing baselines across multiple key metrics including area, wirelength, and post-layout performance.

People

Yapeng Li

The Chinese University of Hong Kong, Shenzhen

Peng Xu

Mingzi Wang

The Chinese University of Hong Kong, Shenzhen

Tinghuan Chen

Research Manuscript

AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability

11:36am - 11:50am PDT Monday, July 27 Mtg Room 101B

AI4-I. AI/ML Architecture Design

DescriptionModern LLMs use diverse integer, floating-point, and microscaling (MX) precisions, but most accelerators are optimized for only a few formats. We propose AMBER, a general-purpose LLM accelerator for plug-and-play multi-precision deployment and compression of weights and KV caches in cloud and edge. AMBER introduces bit-transposed encoding that exploits bit-level statistical concentration for lossless compression across all of INT, FP, and MX formats. A precision-agnostic, stage-pipelined bit-serial PE further reuses bit-level redundancy for efficient versatile precision computation. Evaluated on 8 LLMs and 10 formats, AMBER boosts memory efficiency 1.17× and compute 3.16×, surpassing Olive and Tender in throughput and energy.

People

Research Manuscript

Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services

4:06pm - 4:18pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionIn Large Language Model (LLM) inference services, it is challenging to make a parallelism strategy configuration, to efficiently process the requests of variance context lengths. Requests of long context require high degree of parallelism to provide more memory for Key-Value (KV) Cache, while requests of short context prefer low degree of parallelism to increase concurrency, thus improving throughput.

To maintain high throughput while supporting large context lengths on demand, we propose Amoeba, a runtime Tensor Parallel (TP) transformation for online LLM inference services, which adaptively adjusts the TP of running instances to align with the dynamics of incoming requests. Evaluations using real-world traces show that Amoeba improves throughput by 1.75×-6.57× compared to state-of-the-art solutions.

People

Research Manuscript

AMS Layout Automation Using Circuit-Level Analog Standard Cells and Self-Biasing Techniques in Digital PnR Tools.

3:54pm - 4:06pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionThis work presents a silicon-verified analog–mixed-signal (AMS) layout-automation framework integrating a circuit-level analog standard-cell (CLAS) library with self-biasing circuits in a digital place-and-route (PnR) environment. Unlike transistor-level stem-cell approaches, the CLAS library standardizes matched circuit-level blocks, including self-biased amplifiers, current mirrors, and delay cells. Fabricated 180-nm and 65-nm CMOS chips validate fully automated, DRC/LVS-clean layouts for a current source, adaptive-bandwidth PLL, and probabilistic computer. All benchmarks show strong pre-/post-layout and silicon correlation, with the PLL exhibiting 0.98–1.50 ps simulated and 4.1 ps measured jitter. The framework achieves ≥96 % area utilization, 14.4–69.5 % DCAP density, and <1 min–1 hr runtime, demonstrating scalable, silicon-consistent AMS automation.

People

Wonsik Oh

University of California, Santa Barbara

Luke Theogarajan

University of California, Santa Barbara

Engineering Poster

An Adaptive Dynamic Power Reduction Technique for Digital Filters

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionDigital FIR filters are typically designed for worst-case full-scale input precision, resulting in unnecessary dynamic power dissipation when processing low-amplitude signals. This paper introduces an adaptive technique that tracks real-time signal dynamic range and selectively disables toggling of sign-extended bits in datapath registers. By gating both data and clock for these redundant bits, the approach significantly reduces switching activity without impacting filter functionality or performance. Demonstrated on a 20-tap FIR filter in 28nm FDSOI technology, the proposed architecture achieved over 7% total power savings for a wideband OFDM signal with -24 dB input amplitude. The solution is fully digital, incurs minimal hardware overhead, and is easily deployable across existing filter architectures and technologies. Furthermore, it is scalable to other shift-register-based structures such as delay chains and FIFOs, making it a practical and efficient method for dynamic power reduction in contemporary signal processing systems.

People

Research Manuscript

An Adaptive Prediction of Tokens Fluctuation for Decoupled Prefetching to Accelerate Long-Context LLM Decoding

3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionThe prohibitively slow speed of long-context LLM decoding is a critical bottleneck, caused by massive Key-Value (KV) access that saturates memory bandwidth. Existing solutions fail due to a fundamental trade-off: static predictors cannot handle the Tokens Fluctuation, leading to permanent accuracy loss from irreversible eviction, while an on-the-fly scoring method creates a synchronous bottleneck that stalls the entire pipeline. This paper presents a co-designed system that breaks this trade-off by leveraging an Adaptive Prediction algorithm to enable a fully Decoupled Prefetching architecture. The proposed Adaptive Prediction model first mirrors the nature of Tokens Fluctuation, enabling a lightweight, reuse-based recovery mechanism that solves irreversible eviction. This high-fidelity prediction then unlocks the Decoupled Prefetching system, which completely hides data transfer latency and eliminates the synchronous bottleneck. On long-context LLM decoding tasks, the proposed system matches the accuracy of a full KV cache with just 256 tokens, while achieving an average 2.50x end-to-end speedup.

People

Yuanhua Xiao

Jihe Wang

Zhiyu Sun

Linying Wu

An Adjustable Length Compression Method for MBIST Repair Information

Danghui Wang

NPU

Engineering Presentation

11:30am - 11:45am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionEmbedded memories occupy the largest part of modern SoCs. As memories are high-density physical structure, they are more prone to failures than other circuits and concentrate the large majority of fabrication faults, affecting yield adversely. Hence, memory Built-In Self-Repair(BISR) is mandatory for maintaining acceptable fabrication yield. And the repair information will be burned into the electrically programmable fuse (efuse). As the chip scale increases and the number of memories increases, the required efuse resources also increase dramatically.
Therefore, researchers have proposed a series of methods to efficiently compress memory repair information and save efuse space. In the traditional compression method, there is a repair segment consists of zero compress and repair chain, to handle the worst case, the zero compress will be calculated with the whole chain length and the repair chain data will use the longest Bisr register.
This paper proposes an adjustable length compression method to effectively save the storage space of repair information. As the probability of memory faults is very low, and the fault location, number, and memory repair chain length vary. Therefore there is no need to store the longest bisr register and compress the whole repair chain. And the more fault points in the memory, the greater the benefit of the adjustable length compression method.

People

Research Manuscript

An Agile and Accurate Energy Estimation Methodology for CGRA-Mapped Algorithms: The Synchoros Approach

2:21pm - 2:34pm PDT Tuesday, July 28 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionCoarse-Grained Reconfigurable Arrays (CGRAs) are promising as
accelerators for energy and performance benefits. Agile and accu-
rate energy estimates are essential to explore the CGRA design
space and guide algorithm mapping decisions. Existing estimations
are agile but inaccurate since they do not factor in the impact
of wires in the design. This paper presents synchoros energy es-
timation methodology for post-route accurate estimations. The
methodology leverages the properties of synchoros VLSI design
style to incorporate the impact of interconnects in the design. Over-
all, our methodology achieves 98% estimation accuracy relative
to post-route results for algorithms irrespective of variations in
functionality, dimensions, and parallelism.

People

Ritika Ratnu

KTH Royal Institute of Technology

Dimitrios Stathis

KTH Royal Institute of Technology

Ahmed Hemani

KTH - Royal Institute of Technology

Engineering Poster Gladiator

An AI-Enhanced Web-Based Real-Time Analytics & Prediction Platform for ASIC Physical Design (PD) Flows

5:15pm - 5:22pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAn AI-enhanced real-time analytics and prediction platform designed to bring comprehensive intelligence to complex ASIC Physical Design (PD) flows. This tool automatically captures PD runs, parses massive volumes of logs and reports, and unifies timing, congestion, CTS, IR/EM, DRC/LVS, runtime, and resource metrics into centralized dashboards. By integrating AI-driven pre-run prediction, runtime anomaly detection, and post-run learning, the platform enables early identification of QoR regressions, resource bottlenecks, and failure risks before costly iterations are executed. The solution transforms PD workflows from reactive debugging to proactive, data-driven optimization, significantly reducing manual effort, improving resource utilization, accelerating convergence, and enhancing confidence in physical design closure.

People

Work in Progress

An Autonomous Design Agent of Parallel Feedforward Equalizer for Advanced Wireline Receivers

5:07pm - 5:08pm PDT Monday, July 27 Exhibit Hall

DescriptionFeedforward equalizers (FFEs) are critical digital signal processing (DSP) components in ultra-high speed wireline receivers, frequently limiting power and area efficiency while requiring extensive design effort. This work introduces an autonomous design agent that automatically generates FFEs from system specifications to Verilog implementation. The framework employs a computational data-flow graph model combining unfolding and fast FIR algorithm, along with nonlinear programming for architecture to circuit level optimization. A 128-parallel, 24-tap FFE for a 112-Gbps PAM-4 receiver is successfully synthesized in TSMC 28-nm CMOS within 6 hours using the design agent, achieving 14 % power and 25 % area savings.

People

Research Manuscript

An Efficient Heterogeneous Co-Design for Fine-Tuning on a Single GPU

12:03pm - 12:16pm PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionFine-tuning Large Language Models (LLMs) has become essential for domain adaptation, but its memory-intensive property exceeds the capabilities of most GPUs. To address this challenge and democratize LLM fine-tuning, we present SlideFormer, a novel system designed for single-GPU environments. Our innovations are: (1) A lightweight asynchronous engine that treats the GPU as a sliding window and overlaps GPU computation with CPU updates and multi-tier I/O. (2) A highly efficient heterogeneous memory management scheme significantly reduces peak memory usage. (3) Optimized Triton kernels to solve key bottlenecks and integrated advanced I/O. This collaborative design enables fine-tuning of the latest 123B+ models on a single RTX 4090, supporting up to 8× larger batch sizes and 6× larger models. In evaluations, SlideFormer achieves 1.40× to 6.27× higher throughput while roughly halving CPU/GPU memory usage compared to baselines, sustaining >95% peak performance on both NVIDIA and AMD GPUs.

People

Ruijia Yang

The Hong Kong University of Science and Technology (Guangzhou)

Zeyi Wen

Hong Kong University of Science and Technology (HKUST)

Work in Progress

An Energy-Efficient Automated Hardware Generator for Edge BCI Systems

6:39pm - 6:40pm PDT Monday, July 27 Exhibit Hall

DescriptionElectroencephalography (EEG) enables non-invasive monitoring of brain activity, but its high channel count and computationally intensive neural models pose major challenges to realizing energy-efficient edge accelerator hardware for real-time brain–computer interface (BCI) systems. This work presents EEGDeep, an energy-efficient and fully automated hardware generator that bridges neural network model development and deep-learning hardware accelerators for brain–computer interface (BCI) applications. The framework integrates three core modules: an EEG channel reduction module, which prunes non-informative channels to minimize model size and computational load, enabling practical deployment in wearable applications; an EEGDeep architecture evaluator, which performs constraint-aware neural architecture and hardware exploration through model optimization, a layer-reordering algorithm, and predefined deep-learning configurations to balance accuracy, area, latency, energy, and memory bandwidth; and an EEGDeep RTL generator, which converts optimized models into synthesizable RTL using a parameterized IP template. Using this automated framework, an EEGDeep design implemented in TSMC 90-nm CMOS technology achieves a 91.67% reduction in EEG channels, a processing latency of 1.43 ms per trial, and an energy consumption of 5.51 µJ per trial. These results correspond to a 65.9% reduction in area, a 98.49% improvement in latency, a 98.6% reduction in energy consumption, and a 93.19% improvement in memory bandwidth compared with conventional implementations, demonstrating its potential for practical, low-energy, and real-time BCI applications.

People

Research Manuscript

An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference

10:54am - 11:06am PDT Tuesday, July 28 Mtg Room 101A

AI4-II. AI/ML Architecture Design

DescriptionThe Mixture-of-Experts (MoE) model sparsely activates a subset of experts for each token, causing each expert to process a varying number of tokens during inference. However, existing GPU-based MoE inference frameworks adopt a fixed tensor size for the inputs to each expert, requiring padding when an expert receives fewer tokens, which leads to substantial redundant computation.
In response, we propose a token-stationary dataflow that uniformly abstracts the multiplication between an expert's parameters and input tensors with varying token counts. Based on this dataflow, we design a reconfigurable systolic array that eliminates padding-incurred redundant computation. Evaluation demonstrates that our design outperforms the state-of-the-art GPU-based MoE inference frameworks significantly.

People

Kexin Li

Qinggang Wang

Chuanhui Qi

Shaoxian Xu

Wenkan Huang

Xiangzheng Yang

Zhengzhou University

ruoshi li

Bo Liu

Zhengzhou University

Long Zheng

Xiaofei Liao

Hai Jin

An Engineering Case Study of Autonomous AI PCB Layout Under Real Manufacturing and System Integration Constraints

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAn engineering case study examining the practical implications of autonomous PCB layout in a real hardware development workflow. The automation used in this study is domain-specific and constraint-driven, not an LLM. The case study system is a Linux-capable computer comprising a SOM and baseboard with over 800 components and more than 5,000 pins, designed under realistic electrical, manufacturing, and assembly constraints.

Starting from completed schematics and a defined board outline, the design progressed through automated layout generation, human review and cleanup, fabrication, assembly, and system bring-up using standard advanced manufacturing processes. The system booted Linux and ran real workloads on the first spin.

This outcome required non-trivial human correction of automated results. These intervention points illustrate why experienced PCB designers remain essential, particularly for identifying and correcting failures that are not locally observable prior to system integration and bring-up.

Rather than focusing on tools or algorithms, this talk analyzes what was required for success at each stage of the workflow, where automation was effective, where expert intervention remained necessary, and which assumptions did not hold in practice. It examines how autonomous layout reallocates expert effort—from manual routing toward constraint definition, review, and exception handling—within a broader trajectory of system design.

People

Darin ten Bruggencate

Quilter

Engineering Poster

An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Systems

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionMicrochip FPGAs feature multiple I/O banks, each configurable independently for diverse standards such as SSTL, LVSTL etc., enabling designers to mix and match signaling protocols across the same device while covering a wide frequency range. I/O banks support voltages from 0.5V to 3.3 V, including high-speed DDR PHY interfaces for LPDDR4/5 up to 3.2Gbps. Robust signal integrity across wide frequency-voltage spectrum is achieved through on die IO PVT calibration which dynamically compensates for variations in silicon process, supply voltage, temperature ensuring consistent electrical characteristics like output drive strength and termination impedance. A SAR-based digital block and analog block collaboratively manage reference currents and voltages resulting in complex mixed-signal system.

Verification of this subsystem is paramount to prevent chip-level failures. Full-chip verification challenges include multiple IO banks distributed across chip periphery and CPU-individual bank connections. Validating signal paths from CPU to farthest IO bank necessitates analyzing significant portion of the chip, leading to increased simulation runtime and memory usage.

This presentation covers PVT calibration architecture and verification strategies. It highlights how Siemens Symphony Pro optimizes debugging, reduces simulation time by ~3x, improves memory usage by ~2-3x, and streamlines regressions ensuring reliable calibration verification across diverse I/O standards and extreme PVT conditions.

People

Engineering Presentation

ANA-MODELGEN: Automating Analog IP Model Generation and Validation for Efficient Mixed-Signal Verification

11:00am - 11:15am PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionAnalog IP verification remains a bottleneck in modern mixed-signal SoC development due to lengthy SPICE simulation times and integration challenges. This paper introduces ANA-MODELGEN, a comprehensive hierarchical modeling methodology that transforms analog IP verification through automated model generation and validation. Our approach enables rapid development and validation of behavioral models for any analog IP type, featuring direct integration capabilities with industry-standard verification environments. The methodology includes automated testbench generation for rigorous model validation and equivalence checking against SPICE references. Deployment in production SoC verification flows demonstrates substantial gains in functional coverage and execution speed, enabling earlier bug detection and faster time-to-market.

People

Aadhar Sharma

Analog Intelligence: Physics-Aware AI for Faster, More Accurate Verification

Srijan Soni

Texas Instruments

Engineering Special Session

2:30pm - 3:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

DescriptionThis talk explores the intersection of physics-aware AI and electronic design automation, focusing on how modern neural network architectures can transform analog and mixed-signal verification. We review the evolution of neural networks—from convolutional models to attention-based transformers—and discuss why purely data-driven approaches fall short for engineering problems governed by differential equations. Physics-aware AI embeds domain constraints directly into learning architectures, enabling models that respect conservation laws, device behavior, and circuit dynamics. This approach gives rise to “analog intelligence”: AI systems that reason over continuous-time, multi-physics behavior rather than discrete abstractions. By accelerating core analysis tasks such as transient and frequency-domain verification, physics-aware AI can significantly reduce verification turnaround time, improve design confidence, and enable faster time-to-market with higher first-silicon success rates.

People

Bijan Kiani

Mach42

Research Special Session

Analog Quantum Simulation on Google’s Willow Processor

10:30am - 11:00am PDT Wednesday, July 29 Mtg Room 201A

EDA

DescriptionGoogle's quantum chips have been designed to be ideal for running digital quantum circuits, particularly for performing quantum error correction with the surface code. However, starting in 2024, we have demonstrated that these chips can also be repurposed to run extremely high-fidelity analog quantum simulations. Furthermore, the two capabilities can be combined, mixing digital gates with analog evolution. In this talk, I will discuss several recent experiments that leverage our hybrid analog-digital simulation platform, including adiabatic preparation of low-energy states both within the qubit subspace and incorporating higher energy levels beyond |0⟩ and |1⟩, as well as an analog counterpart to random circuit sampling.

People

Aaron Szasz

Google

Engineering Presentation

Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration

4:45pm - 5:00pm PDT Monday, July 27 Seaside Ballroom A

EDA

Systems

DescriptionAs high-speed, highly integrated systems-on-chip (SoCs) advance, the design of robust power delivery networks (PDNs) becomes critical to ensure reliable operation. In 3D-stacked high bandwidth memory (HBM), the vertical stacking of multiple core dies (Cdie) on a base die (Bdie) introduces significant challenges, including increased PDN impedance and cross-die current interactions, necessitating full-stack 3D-IC IR-drop analysis. However, conventional EMIR tools face scalability bottlenecks due to the massive transistor count and terabyte-scale input in HBM Bdie designs, often leading to excessive runtime or tool failure. This study presents a scalable methodology using Synopsys Totem-SC to enable full-chip 3D-IC EMIR analysis for HBM. We introduce a (1) the DSPF-only flow with parallel parsing, eliminate redundant processes, (2) cell‑based decoupling capacitor method that cuts transistor count in DSPF files by up to 70% and (3) current copy methodology. Further enhancements include (4) improve runtime (up to 78.3%) and capacity (up to 2 billion transistors), in parasitic/current extraction, GDS-to-DEF conversion, and partitioned database generation stage. Successful 3D-IC analysis reveals a 442% increase in maximum IR-drop device point (from 0.5 to 2.21) compared to single-die analysis, highlighting the necessity of full-stack simulation. The proposed method enables efficient, high-capacity EMIR analysis for next-generation 3D-IC designs.

People

Research Manuscript

Analytically-Derived Hybrid Net–pin Weighting for Timing-Driven Global Placement

4:42pm - 4:54pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionTiming-driven global placement is critical in modern VLSI physical design for achieving timing closure. Among existing approaches, weighting is a mainstream technique, but traditional weights are often manually designed based on heuristics, which can lead to suboptimal timing performance. To address this, we present an analytically-derived model of interconnect and cell-delay contributions of pin pairs along critical paths, from which we obtain explicit and differentiable formulations approximating Total Negative Slack (TNS) and Worst Negative Slack (WNS). The formulations include three wirelength components: net wirelength, linear pin-to-pin wirelength, and quadratic pin-to-pin wirelength, where net and linear pin-to-pin wirelength are smoothed via the weighted-average (WA) model. Based on these formulations, we derive a hybrid net-and-pin weighting scheme and propose a novel timing-driven global placement framework that directly optimizes TNS and WNS. The weighting scheme features dynamic and cumulative updates, ensuring that consistently critical paths are prioritized throughout optimization. Experimental results on the ICCAD'15 benchmark demonstrate that our method achieves average improvements of 39% in TNS and 6% in WNS compared with state-of-the-art timing-driven placers, while maintaining competitive wirelength and runtime, validating the effectiveness of the analytically-derived weighting framework.

People

Engineering Special Session

Applying AI to Transform Specification-Driven Development and Engineering Productivity

3:30pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionSandisk will present how a leading semiconductor company applies AI to transform specification-driven development and engineering productivity. The session will showcase practical workflows that improve specification quality, accelerate downstream documentation, and help engineers ramp faster on complex systems. Examples include using AI to detect ambiguities, inconsistencies, and missing requirements in specifications, while recommending fixes and useful extensions. We will also cover multimodal capabilities for analyzing existing diagrams and generating new visual content directly from specification inputs. The presentation will demonstrate an AI-powered knowledge assistant integrated into engineers’ daily development environment, enabling fast access to trusted design information. In addition, AI-generated outputs such as verification plans, coverage plans, sign-off documentation, and structured work-item breakdowns from high-level requirements will be shown. This talk highlights practical ways AI can modernize semiconductor engineering workflows today.

People

Mariana Shenker

Sandisk

Research Manuscript

AQR-HNSW: Accelerating Approximate Nearest Neighbor Search via Density-Aware Quantization and Multi-Stage Re-Ranking

2:47pm - 3:00pm PDT Wednesday, July 29 Mtg Room 101B

AI3-II. AI/ML Application and Infrastructure

DescriptionApproximate Nearest Neighbor (ANN) search has become fundamental to modern AI infrastructure, powering recommendation systems, search engines, and large language models across industry leaders from Google to OpenAI. Hierarchical Navigable Small World (HNSW) graphs have emerged as the dominant ANN algorithm, widely adopted in production systems due to their superior recall vs. latency balance. However, as vector databases scale to billions of embeddings, HNSW faces critical bottlenecks: memory consumption expands, distance computation overhead dominates query latency, and it suffers suboptimal performance on heterogeneous data distributions. This paper presents Adaptive Quantization and Rerank HNSW (AQR-HNSW), a novel framework that synergistically integrates three strategies to enhance HNSW's scalability. AQR-HNSW introduces (1) density-aware adaptive quantization, achieving 4× compression while preserving distance relationships; (2) multi-state re-ranking that reduces unnecessary computations by 35%; and (4) quantization-optimized SIMD implementations delivering 16-64 operations per cycle across architectures. Evaluation on standard benchmarks demonstrates 2.5-3.3× higher QPS than state-of-the-art HNSW implementations while maintaining 98%+ recall, with 75% memory reduction for the index graph and 5× faster index construction.

People

Ganap Tewary

Arizona State University

Nrusinga Charan Gantayat

Arizona State University

Jeff Zhang

Arizona State University

Research Manuscript

ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy

4:30pm - 4:42pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionConventional SRAMs are designed for random access, resulting in significant energy waste under regular access patterns common in image processing, computer vision, deep learning, and dense linear algebra to name a few. We propose an energy-efficient ARC-SRAM subarray architecture that integrates three synergetic energy reduction schemes: (1) Address decoding energy reduction by relocating the address generation to the memory periphery; (2) Read energy reduction by reducing wordline activity to one pulse per row and minimizing precharge activity to suppress half-selection energy; (3) Write energy reduction by reusing the bitline charge across consecutive rows, and by minimizing wordline activation.
We implement a 64KB instance of our ARC-SRAM using an advanced gate all around nanosheet 1.4 nm research process design kit. At the cell-array level, the design achieves a 63–76\% energy reduction for reads and 68–72\% for writes in loop-nest dominated applications, with only 4\% area overhead.

People

Ismail Bourhaeil

Geerten Verweij

Mahmood Naderan-Tahan

National Technical University of Athens

Francky Catthoor

Said Hamdioui

ARCHITECT LABS: Ada: A Self-Improving AI System for HW-SW co-Design and Verification

Exhibitor Forum

3:15pm - 3:45pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

DescriptionAI-agentic flows for chip design have emerged with the potential to create a paradigm shift in the EDA industry. At Architect Labs, we are building the first generation of AI-native design methodology for chip development. In this presentation, we share details on our AI-based automation flow for fast and verifiable generation of frontend design-collaterals, including architectural exploration, software-modeling, RTL, and verification. Our methodology enables capturing the design intent of the architecture based on design specifications, while the human-in-the-loop iterates on the specs as the “architect”. At the core of this methodology, an agentic harness combined with ML methods including reinforcement learning and test-time-scaling achieves fully end-to-end autonomous HW design and verification capability, all while using SOTA EDA tools and proven chip design methods. As a demonstration vehicle, we further present how
our AI system autonomously designed a specialized AI hardware accelerator targeting FPGA deployment for running inference on a SOTA LLM model. In this end-to-end demo, we share details on how our harness performs architectural exploration under memory vs. compute bound workloads to generate performance models, firmware, RTL, AI kernels, and more. We will bring the FPGA for an in-person demo, and share quantitative results on both the methodology and the design results, such as number of engineers, time-to-design, and achieved performance numbers.

People

Ekin Sumbul

Architect Labs

Engineering Presentation

Architectural Coverage Analysis and ML-Based Automated-Test Generation

11:30am - 11:45am PDT Monday, July 27 Seaside Ballroom A

EDA

DescriptionVerification coverage analysis evaluates the effectiveness of verification stimulus on design verification. Significant computational resources are spent toward coverage closure. Robust infrastructure and tools are available to analyze large coverage data to efficiently allocate resources to the most effective testcases. While we have correlation of testcases to coverage events they are likely to discover, little is known about why.

Further investigation into components that comprise the testcases, both from a stimulus-completeness and coverage correlation perspectives, is necessary. In this work, we augment coverage data with instrumentation to collect testcase components. Our analysis in the POWER simulation environment guided resolution of undesirable biases in stimulus generation and inefficient tests previously unknown. Furthermore, using ML and statistical techniques, we establish correlation between test components and coverage events, allowing composition of new testcases from components highly correlated with desired event scenarios. Coverage analysis shows these super-tests are most likely to achieve hard-to-hit scenarios and therefore make up 86% of recommended testcases. Increasing likelihood of such unlikely events and tuning environment inefficiencies lead to savings in computational resources in the verification environment.

People

Engineering Presentation

Architectural Formal Verification of Configurable Address Translation Logic for Early Bug Exposers

4:45pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionHighly configurable, hash‑based address translation logic is central to modern memory subsystems, enabling scalability, parallelism, and load balancing(fairness) across multiple clients and lanes. However, the resulting configuration and address spaces grow far beyond what simulation can feasibly explore. Even subtle specification‑level errors in hashing or decoding semantics can silently propagate into RTL and system software, leading to persistent data corruption and costly late‑stage debug. This paper presents an architectural‑level formal verification methodology that shifts correctness assurance left, before RTL development. The intended hash and decoder behaviour is captured using an executable architectural reference model, independent of RTL implementation. Architectural intent is expressed as global invariants—such as no aliasing, load balancing(fairness), address safety, lane conflict avoidance, and controlled error propagation—and proven symbolically across all legal configurations and the full address space. The same reference model and proven invariants are then reused directly at the RTL level to perform invariant‑guided equivalence checking. By integrating these already verified block‑level properties as assumptions in the existing end‑to‑end RTL formal environment, system‑level correctness is validated without building a new formal setup or re‑verifying internal blocks. This approach uncovers mis‑integration bugs while avoiding over‑constraint. Applying this methodology exposed multiple critical specification bugs prior to RTL. The results demonstrate a scalable, reusable, and production‑ready formal flow for complex memory systems.

People

Research Manuscript

Are They All Safe? Practical Fault Injection Attacks on FPGA Logic Synthesis Tools

4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 202C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionFPGAs are widely deployed in critical systems, but flaws in EDA toolchains can enable malicious HDL injection, leading to severe hardware vulnerabilities. We propose DefVul-Risk, an automated framework for assessing fault-injection risks in FPGA synthesis tools. It constructs a defect knowledge base, generates triggerable vulnerability samples via large language models, and fine-tunes risk-assessment models to prioritize high-risk defects. DefVul-Risk enhances toolchain security evaluation and vulnerability remediation efficiency. We submitted 26 CVE reports, with 9 officially confirmed.

People

Jiaxin Li

Dalian Maritime University

Shikai Guo

Dalian Maritime University

Zhihao Xu

Dalian Maritime University

Qian Ma

Xiaochen Li

Dalian University of Technology

He Jiang

Dalian University of Technology

Research Manuscript

Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells

3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203AB

EDA

EDA7-II. Physical Design and Verification

DescriptionAs conventional FinFET architectures encounter severe scaling limitations, Complementary-FET (CFET) technology with vertically stacked PMOS and NMOS transistors has emerged as a promising solution for continued standard cell density scaling. However, aggressive area compaction in CFET standard cells drastically limits intra-cell routing resources, leading to routing congestion and design rule challenges. To mitigate this issue, multi-row CFET standard cell architectures have been introduced to improve intra-cell routability and alleviate block-level congestion. Nevertheless, these multi-row configurations introduce new placement-routing coupling and design rule complexities, making it challenging to achieve compact, DRC-clean, and routable layouts. Therefore, this work proposes an area-optimal and routability-driven layout synthesis framework for multi-row CFET cells, which effectively addresses the challenges of area efficiency, constrained pin accessibility, and DRC compliance under multi-row CFET architectures. Therefore, this work proposes an area-optimal and routability-driven layout synthesis framework for multi-row CFET cells, which effectively addresses the challenges of area efficiency, constrained pin accessibility, and DRC compliance under multi-row CFET architectures. and (3) a two-stage Satisfiability Modulo Theories (SMT)-based routing flow consisting of a Multi-Commodity Flow (MCF)-based routability-guaranteed pin-access selection and an Integer Linear Programming (ILP)-enhanced hierarchical routing to ensure DRC/LVS closure. Compared with state-of-the-art multi-row CFET cell generators, experimental results show that our algorithm consistently achieves the optimal layout area, while delivering significant improvements in solution quality and efficiency.

People

Research Manuscript

ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing

3:54pm - 4:06pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionSolid-State Drives (SSDs) now power data centers, high-performance computing, and artifical intelligence workloads, but the increasing complexity of modern SSD controllers has surpassed the capabilities of traditional rule-based verification, necessitating scalable, data-driven testing methods. In this paper, we present ARTEMIS, a reinforcement‑learning (RL)‑based framework for automatic SSD test case (TC) generation that operates directly on commercial devices. Our contributions are threefold. First, we formulate a novel RL problem, enabling seamless deployment across heterogeneous commercial products without requiring any device-specific customization. Second, to cope with the highly dynamic and non‑stationary operating environments of SSDs, we introduce an ensemble‑based inference mechanism that aggregates policies learned under diverse workload distributions, thereby improving generalization and robustness. Third, we validate the approach on two representative stress‑testing tasks: Meta and User Garbage Collection. We show that the RL‑driven tester discovers high-impact TCs that trigger critical blocking garbage collection events more frequently than conventional methods in diverse tasks.

People

Engineering Poster

ARTEMIS: Agentic AI for EDA

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionFront-end RTL verification workflows consume significant compute resources and engineer time, with Verilog simulations often failing due to syntax errors, testbench issues, or configuration problems detected only after resource consumption. Traditional workflow management lacks predictive intelligence to prevent this waste.
This presentation introduces ARTEMIS (Automated RTL Testing & Error Management Intelligent System), a production-deployed multi-agent AI architecture that optimizes front-end verification workflows through intelligent error detection. ARTEMIS employs four specialized agents working collaboratively: Debug Agent (error identification), Supervisor Agent (resource orchestration), Scheduler Agent (regression test sequencing), and Job Analysis Agent (real-time monitoring). The system integrates with Verilog and industry-standard schedulers through Model Context Protocol servers.

The intelligent error detection system analyzes iverilog output patterns to identify syntax errors, module instantiation issues, and testbench problems before they consume compute resources. When failures are predicted, the system automatically terminates jobs and releases resources.
Production deployment metrics demonstrate 15-25% reduction in compute costs and 45% reduction in debugging time. This presentation chronicles the journey from award-winning prototype to production MLP with actionable implementation guidance for EDA workflows

People

Research Manuscript

ASG-MOENN: Adaptive Sparsely-Gated Mixture of Experts Neural Network for Digital Predistortion in Quadrature Switched-Capacitor Power Amplifiers

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionFor the first time, this paper introduces an adaptive sparsely-gated mixture of experts neural network (ASG-MOENN) as a novel digital predistortion (DPD) framework for wide dynamic power range quadrature switched-capacitor power amplifiers (SCPAs). State-of-the-art (SOTA) DPD models suffer from fixed, high computational complexity, leading to inefficiency at lower power levels. To overcome this limitation, the proposed ASG-MOENN employs a dual-stage adaptive mechanism. First, it embeds the underlying physical principles of SCPA power variation to condition the input signal. Second, it incorporates an adaptive sparse gating mechanism that dynamically determines both which experts to activate and how many are required based on a cumulative confidence criterion, allowing the model to flexibly scale its run-time complexity according to the PA's operating state. Experimental results demonstrate that, compared with the SOTA baseline, the proposed model achieves superior linearization performance while reducing the average computational load by up to 50% across a 30-dB dynamic power range.

People

Research Manuscript

Asymcheck: Asymmetric Partitioned Checkpointing for Efficient Large Language Model Training

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionDistributed large language model (LLM) training faces prevalent failures and requires efficient checkpointing. State-of-the-art approaches employ partition-based pipelined checkpointing, splitting checkpoints into partitions for concurrent processing. However, existing solutions rely on a fixed partition size, which our analysis reveals is suboptimal for LLM training: large partitions cause bandwidth stalls during forward passes, while small partitions incur substantial startup overhead during backward passes. We propose AsymCheck, which employs asymmetric partitioning: small partitions for forward passes and large partitions for backward passes, plus selective partition compression and batched flushing optimizations. Evaluation on 64 GPUs shows AsymCheck reduces training time by 20.1%-48.2% over state-of-the-art methods, approaching no-checkpointing efficiency.

People

Zhangqiang Ming

Yuchong Hu

Zhiyuan Luo

Patrick P. C. Lee

Innovation Research Institute of Cethik Group Co., Ltd.

Yuanhao Shu

Xinjue Zheng

Wenxiang Zhou

Dan Feng

Athena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage

Research Manuscript

3:42pm - 3:54pm PDT Wednesday, July 29 Mtg Room 202C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionWe present Athena, a scalable analytical framework for pre-silicon side-channel leakage evaluation that avoids simulation entirely. Athena integrates static timing information with signal-probability propagation to model time-dependent circuit behavior, capturing leakage arising from input-arrival skew, glitches, and other timing-induced effects. The fine-grained leakage estimates produced, precisely identify vulnerable signals and time intervals, and supports evaluation of diverse countermeasures including masking, gate resizing, and differential logic. We evaluate Athena across a broad set of countermeasures on S-boxes and full ciphers, comparing both correctness and performance against state-of-the-art tools. Across all benchmarks, Athena delivers over 400x speedup over existing methods.

People

Janakiraman Viraraghavan

IIT Madras

Chester Rebeiro

IIT Madras

Research Manuscript

ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification

5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 202C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionThis work presents ATLAS, an LLM-driven framework that bridges standardized threat modeling and property-based formal verification for System-on-Chip (SoC) security. Starting from vulnerability knowledge bases such as Common Weakness Enumeration (CWE), the framework identifies SoC-specific assets, maps relevant weaknesses, and generates assertion-based security properties and JasperGold scripts for verification. By combining asset-centric analysis with standardized threat model templates, it automates the transformation from vulnerability reasoning to formal proof. Evaluated on three HACK@DAC benchmarks, ATLAS detected 39/48 CWEs and, out of that 39, ATLAS was able to generate correct properties for 33 of the bugs, advancing automated, knowledge-driven SoC security verification toward a secure-by-design paradigm.

People

Ishraq Tashdid

Kimia Tasnia

Alexander Garcia

Jonathan Valamehr

Sazadur Rahman

ATLAS: Asynchronous Topological Learning for Accurate FIT Prediction via Decoupled Graph Neural Networks

Research Manuscript

5:18pm - 5:30pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionSafety-critical integrated circuits targeting ISO 26262 ASIL-D require a failure-in-time (FIT) $<10$. These physics-based tools for FIT prediction, such as BFIT, are accurate but slow, while ML baselines suffer collapse under long-tailed FIT distributions. We propose \textbf{ATLAS}, a decoupled GNN framework that combines a bidirectional asynchronous topological message passing backbone, aligned with BFIT's forward and backward propagation, with RankNet and CalibNet synergistic heads. RankNet uses a gap-aware pairwise ranking loss with log-gap weighting $\Delta\log(t)$ and explicit emphasis on head samples to identify top-$k\%$ high-risk gates. CalibNet employs a dual-domain loss in log and linear spaces, incorporating importance weighting, for accurate calibration. The proposed design achieves $O(|V|+|E|)$ complexity, delivering up to 220$\times$ speedup over BFIT while reducing selective hardening area overhead by 53\% compared to DeepGate2 on ITC'99 benchmarks, thereby enabling the rapid reliability-aware design of large-scale circuits. We plan to open-source our data and model code after acceptance.

People

Yicheng Liu

Mingjun Wang

Songwei Pei

Yuntao Lu

Zizhen Liu

Institute of Computing Technology, Chinese Academy of Sciences

Boyu Han

Stanford University

Huawei Li

Shangguang Wang

ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer

Research Manuscript

4:54pm - 5:06pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionIn this paper, we propose an analytical method for 3D mixed-size placement that incorporates macro-orientation awareness in face-to-face (F2F) terminal-bonded heterogeneous 3D ICs. This work introduces a novel one-pass placement framework that bypasses the conventional 2.5D co-optimization, effectively narrowing the gap between partitioning and placement and achieving significant time savings. Our method constructs a differentiable distributed macro-rotation system that unifies partitioning, placement, and macro-orientation within 3D global placement. To compensate for deviations arising from wirelength estimation in 3D placement, we further apply an FM-based post-partitioner. Experimental results on the ICCAD 2023 contest benchmark show that our approach achieves an 8% higher quality than the first-place contest entry and a 2% improvement against the best published method with 1.6× runtime speedup.

People

Yutao Wang

Liang Xiao

Bangqi Fu

Lixin Liu

Evangeline Young

Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment

Engineering Presentation

11:00am - 11:15am PDT Wednesday, July 29 Seaside Ballroom B

Design

EDA

Security

Systems

DescriptionThis work presents a pre-silicon side-channel leakage assessment of an open-source AES-XTS hardware implementation at the RTL level. The complete encryption flow is functionally verified, and switching activity is captured and converted into high-resolution waveform data for power reconstruction. A Test Vector Leakage Assessment (TVLA) and Correlation Power Analysis (CPA) are applied to identify statistically significant leakage across encryption cycles and the key byte disclosures. Results reveal dominant leakage during early intermediate datapath operations, motivating targeted security refinement. The study demonstrates the effectiveness of integrating vector-based power reconstruction with systematic leakage evaluation to expose vulnerabilities prior to fabrication, enabling cost-effective mitigation and improved hardware security robustness.

People

Harikrishnan Balagopal

Emrah Karagoz

Ferhat Yaman

Sourabh Goyal

Attackonctf: Defending Hardware Security Competition Benchmarks in the Age of LLMs

Research Manuscript

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionHardware security competitions such as HackTheSilicon serve as benchmarking platforms for evaluating vulnerability detection methods and training human and AI. However, our study reveals that LLMs threaten their validity. Instead of genuine security reasoning, detectors exploit a diff-style syntactic comparison, achieving an 83% detection rate, undermining fair evaluation. To mitigate this, we propose the first LLM-oriented, semantics-preserving obfuscation framework for these benchmarks. Unlike IP-protection approaches, it applies human-readable transformations and controlled diff-noise while preserving functionality. On HackTheSilicon, the framework reduces LLM-based detection accuracy by 50% with only 10% obfuscation and by 78.6% under complete obfuscation, restoring benchmark reliability.

People

Mohamadreza Rostami

Technical University of Darmstadt

Nikhilesh Singh

Technische Universität Darmstadt

Stephen Muttathil

Texas A&M University

Lichao Wu

Technical University of Darmstadt

Chen Chen

Texas A&M University

Huimin Li

Technical University of Darmstadt

Jeyavijayan Rajendran

Texas A&M University

Ahmad-Reza Sadeghi

Technische Universitaet Darmstadt

Research Manuscript

Attentioncap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction

1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionAs capacitance extraction accuracy of rule-based pattern matching becomes difficult to sustain at advanced nodes, a growing trend emerges to develop deep-learning-based 2D capacitance models. However, existing MLP- and CNN-based methods constrain their input to fixed metal-layer combinations in a specific process node, limiting their usability in practice. Recognizing the inherent similarity between capacitance matrix and the prevailing attention mechanism, we propose AttentionCap, a customized Transformer for capacitance matrix learning, with a Gram representation framework, a physics-aligned symmetric-attention output layer, and a novel normalized Laplacian loss. We also introduce a process-node embedding to enable multi-node learning. Trained on synthetic data, AttentionCap attains 0.67%/3.99% self/coupling-capacitance error on unseen real designs under a multi-layer and multi-node setting, surpassing the CNN-Cap baseline with 4.6x/5.7x lower self/coupling error and 192x faster inference speed. A pretrained AttentionCap accurately transfers to an unseen node with only 5K samples and 4K finetuning steps. With sufficient accuracy on unseen real designs and strong transferability to new process nodes, AttentionCap offers highly practical value for modern EDA workflows. Code and data are available at https://anonymous.4open.science/r/AttentionCap-release-F698.

People

Research Manuscript

Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs

1:30pm - 1:42pm PDT Wednesday, July 29 Mtg Room 202AB

Security

SEC1. AI/ML Security/Privacy

DescriptionThis paper presents AttestLLM, the first attestation framework to protect device vendors' hardware-level intellectual property by ensuring that only authorized large language models (LLMs) can execute on target platforms. To overcome the scalability and efficiency limitations of prior work, AttestLLM leverages an algorithm/software/hardware co-design approach to embed robust watermarks onto the activation of LLM layers. In addition, it optimizes the attestation protocol within the trusted execution environment, providing efficient ownership verification without compromising inference throughput. Evaluations on various on-device LLMs demonstrate AttestLLM's attestation reliability, fidelity preservation, and efficiency. Furthermore, AttestLLM exhibits resilience against forgery, replacement, and system attacks.

People

Ruisi Zhang

University of California, San Diego

Yifei Zhao

University of California, San Diego

Neusha Javidnia

Mengxin Zheng

University of California, San Diego

Farinaz Koushanfar

Research Manuscript

ATTINA: Spatial Acceleration of Additive Number Theoretic Transform for Energy-Efficient zkSNARKs at the Edge

4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionModern zero-knowledge proof (ZKP) schemes are moving from costly elliptic curve-based systems towards algebraic proof systems. This transition is ushering in a new era of broad adoption of hardware-friendly ZKPs, implementable even on resource-constrained edge devices. Algebraic structures, such as towers of binary fields, are core components of such schemes, and they require hardware and algorithmic innovation to realize advanced ZKPs, such as Binius and Binius-FRI, efficiently.

Hence, this paper introduces the ATTINA framework, a high-throughput additive number theoretic transform (ANTT) accelerator operating over extended binary fields. ANTT is the most computationally intensive task for realizing Binius. ATTINA partitions ANTT tasks into multiple subtasks and strategically allocates them to processing elements (PEs) and hardware programmable logic (PL) kernels in an interleaved computing pattern. ATTINA features a scalable architecture that enables dynamic parameter changes for different cryptographic applications. To understand its applicability, this paper implements ATTINA on an edge-deployable heterogeneous Versal adaptive system-on-chip (ASoC) platform. ATTINA on Versal ASoC maintains a throughput of 10 Gb/s. ATTINA outperforms a benchmark CPU implementation of ANTT on a high-end processor (i9-14900K) by \textbf{139$\times$} and a PE-only implementation by \textbf{38$\times$} in terms of latency while operating at $\ leq$5W for a 4096-point ANTT. ATTINA's code is published at \url{https://anonymous.4open.science/r/ATTINA} for evaluation and reproducible research.

People

Yanze Wu

George Mason University

Devin Park

George Mason University

Md Tanvir Arafin

George Mason University

Work in Progress

Atto-Spinformer: An Energy-Efficient Magneto Electric Spin Orbit Logic-Based Compute-in-Memory Transformer Architecture

6:53pm - 6:53pm PDT Monday, July 27 Exhibit Hall

DescriptionTransformers form the foundation of modern natural language processing, but their performance is limited by GPU memory bandwidth and high energy consumption. In-memory computing (IMC) architectures mitigate data transfer overhead, yet remain constrained by power-hungry interfaces. We present a novel ultra-low-power Magneto-Electric Spin Orbit (MESO)-based IMC architecture optimized for dot product operation acceleration within transformers. By exploiting device non-volatility and a custom transmission-gate-based pulse application scheme, our design eliminates DACs at the CMOS-MESO interface and reduce interface power by 20.3x. We propose a custom computation scheme that significantly lowers the floating-point operations required by IMC architectures to compute outputs. Combined with the low-power MESO devices, these techniques enable our accelerator to boost computational efficiency by 4.4x relative to conventional IMC designs and 2.6x relative to the NVIDIA A100 GPU.

People

Hasita Veluri

Lawrence Berkeley National Laboratory

Dilip Vasudevan

Lawrence Berkeley National Laboratory

Engineering Presentation

Auto-Chk: Closing the Last-Mile Interpretation Gap in Digital Sign-off via a Neuro-Symbolic Compiler Framework

10:30am - 10:45am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionRecent RCA studies show that failures in digital sign-off rarely stem from EDA execution itself, but from the last-mile interpretation layer. Script-based automation, built on rigid syntax matching, breaks under tool/version drift and cannot enforce cross-stage causality, leading to silent misses. Human-centric checklists, introduced as a safety net, collapse under massive unstructured reports and schedule pressure, causing cognitive overload and false sign-off escapes.

We present Auto-Chk, a neuro-symbolic compiler framework that closes this interpretation gap. Instead of hard-coding scripts, Auto-Chk compiles natural-language verification intent into a deterministic intermediate representation, ItemSpec, which decouples intent from implementation. Generated checkers are stress-tested using adversarial, metamorphic validation without requiring golden data, and executed inside a secure sandbox with runtime monitoring. A cross-layer self-healing loop automatically adapts to log or tool changes. On top, an evidence-driven dashboard and role-based copilots transform raw logs into confidence-aware decisions and organizational knowledge.

Auto-Chk has been deployed at production scale, covering over 120 checklist items across multiple IPs, EDA tool versions, and process nodes. Results demonstrate a 20× reduction in checker development time, 100% semantic consistency, and sub-30-minute time to recovery, with full project convergence achieved within 15 hours. Outputs are delivered through a project-level dashboard and a role-based copilot, providing executable, resilient sign-off intelligence.

People

Wentao Dai

Auto-Formalization to Bridge Design Specifications Into Verifiable Hardware Logic

Exhibitor Forum

4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionAI can already help individual engineers write code faster, but generating the complex, interdependent artifacts that silicon design needs - like testbenches, reference models, checkers and RTL - requires intelligent harnesses and agent orchestration layers that understand how these artifacts relate and how they're validated.
Existing applications of AI for silicon design fall into two patterns: general-purpose coding agents that lack native understanding of silicon workflows, and LLM wrappers around legacy tool suites that reach baseline quality on isolated tasks but degrade as workflows chain across steps. Both generate artifacts in isolation, and each step can introduce errors that compound downstream. A holistic approach to generation requires continuous feedback among specifications, simulation results, downstream design metrics, and the engineers themselves.
Normal Computing addresses these limitations by building AI systems that learn from every artifact generated, every human edit, every simulation run, and every downstream signal about power, performance, and area. Generation and validation agents, trained on silicon engineering trajectories and simulation feedback, with native access to the toolchains, are the foundation. We treat continual learning as the architecture, and each interaction strengthens a shared knowledge base that grounds future generations in the design intent of the team, and the physics. Auto-formalization is one mechanism within this system, used to construct structured intermediate representations that keep complex artifacts coherent as they scale. Closing the loop with our own synthesis and analysis tools lets the system reason about quantitative design tradeoffs while it generates RTL and verification artifacts that are aware of the constraints they'll be measured against.
This talk presents the architecture behind these learning loops, benchmarks against general-purpose approaches on production-representative tasks, and results from deployments with top semiconductor partners globally

People

Johann George

Normal Computing

Engineering Poster

Automated 3Dblox File Generation: Enabling Extremely Rapid Solution Exploration by Streamlining Thermal and IR Analysis of 3D SOICs

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe rapid evolution of 3DIC stacking technologies has unlocked new opportunities for scaling and system technology co-optimization. However, these technologies also bring increased power density and thermal impedance while simultaneously expanding the design space. In this environment, the consequences of early architectural decisions are magnified, the information available to make them is sparce, and speed is of the essence.

We present an automated 3Dblox-based solution that streamlines the generation and evaluation of multi-die architectures, enabling architects to rapidly prototype, analyze, and optimize complex 3D Multi-Chip Modules for thermal and IR performance. Our work builds upon an existing GUI-driven prototyping system which supports flexible floor planning and power density specifications without requiring RTL or netlist data. Here we integrate the generation of industry standard 3dbv, 3dbx, and 3dbf files for analysis with EDA tools.

By leveraging a combined internal and EDA tool flow, we reduce simulation turnaround time for thermal and IR feasibility from days to minutes. This approach identifies thermal and IR hotspots, facilitating better-informed design decisions early in the process. We demonstrate a scalable and practical methodology for early-stage 3DIC design, shifting critical analysis left in the development cycle and enabling broader, more rigorous exploration of next-generation system architectures.

People

Late Breaking Results

Automated Design of Device Fingerprinting Circuits for FPGAs

5:09pm - 5:12pm PDT Monday, July 27 Exhibit Hall

DescriptionDesigning device fingerprinting circuits for FPGAs is challenging due to limited knowledge about device layout and manufacturinginduced biases, often resulting in poor uniqueness and biased responses. Existing mitigation techniques are typically device-specific, time-consuming, and difficult to generalize. We propose an automated EDA tool, that analyses the target FPGA to optimize circuit layout to maximise extracted entropy and mitigate systematic bias.
Across 100-device testbed, the tool outperformed comparable manual designs, achieving near-ideal uniqueness and bias. These results demonstrate that automated device-aware design can reliably estimate and approach the best achievable performance on a given
FPGA.

People

James Moore

Queen's University Belfast

Maire O'Neill

Queen's University Belfast

CHONGYAN GU

Queen's University Belfast

Research Manuscript

Automated Discovery, Classification, and Systematic Security Verification Methodology for Undocumented Instructions

11:23am - 11:36am PDT Tuesday, July 28 Mtg Room 203C

Security

SEC3-II. Hardware Security: Attack and Defense

DescriptionUndocumented instructions pose a growing security threat, yet current research is limited.
Existing work focuses on discovery with constrained techniques, while semantic analysis is manual and ad-hoc. Moreover, a significant gap exists in methodologies for systematic security verification. This paper presents a comprehensive framework for the automated discovery, systematic classification, and security verification of undocumented instructions. Our evaluation discovered 23 new instructions and classified 29 using a classifier with 99.8357% accuracy. Most importantly, we verified that 5 instructions have tangible security implications, demonstrating our approach's efficacy in addressing threats at the processor instruction level.

People

Yooseok Lee

Kangwon National University

Junho Jo

Kangwon National University

Hanjoon Kim

Furiosa AI

Wonjun Song

Kangwon National University

Engineering Presentation

Automated System for FPGA-Based SoC Prototyping

2:15pm - 2:30pm PDT Wednesday, July 29 Seaside Ballroom A

EDA

Systems

DescriptionDesigning System-on-Chips (SoCs) requires a well-organized development process. Pre-silicon validation/verification plays a crucial role; it can be performed in various ways. Here, simulation and prototyping are addressed. This presentation focuses on digital devices. Therefore, FPGA-based prototyping fits perfectly. SoC development requires significant time for RTL coding and IP integration. The design evolves daily. Continuous simulations are launched, and prototyping must keep pace. Hence, constant realignment between the two environments is necessary. The FPGA scenario differs slightly from the simulation one: some blocks must be replaced (memories, PLLs and others) when switching from one domain to another. This replacement essentially involves managing and modifying lists of source code files (Verilog, SystemVerilog and VHDL) used for simulation and FPGA synthesis. Given the complexity of modern designs, manual handling could lead to human mistakes. This presentation describes a system, based on Python scripts, for the automatic transition from simulation to prototyping (and back).

People

Engineering Presentation

Automated Validation of Liberty Models

2:45pm - 3:00pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionSignoff-quality standard cell libraries are critical for successful SoC tape-outs. Even minor inaccuracies in Liberty (.lib) models can lead to late-stage failures in timing, power, IR drop, and noise analysis. Manual QA of Liberty files are error-prone due to their complexity, especially with statistical LVF and CCS waveform data for advanced nodes.

Traditional validation methods are slow, resource-intensive, and often miss subtle inconsistencies. The need for a scalable, automated, and SPICE-accurate validation framework was driven by:
• Increasing complexity of Liberty views
• Growing number of PVT corners and cells
• Demand for early detection of outliers to reduce debug cycles

We present an automated validation framework methodology covering
• Moments-based LVF validation: Reduces false positives from traditional sigma checks.
• STA-like LVF comparison: Uses effective delay/transition metrics for realistic analysis.
• Automated SPICE setup: Supports all arcs, slew/load conditions, and parasitic.
• Insight-driven debug: Visual trend plots accelerate root cause analysis.

Applied to over 1000 cells across 30+ PVT corners, the methodology enables early outlier detection, improves SPICE level correlation, and delivers up to 2× productivity gains in validation and revision analysis. The results demonstrate a scalable approach to achieving consistent, signoff ready Liberty libraries with reduced silicon risk.

People

Merin Meyn

Gaurav Dhawan

Automated Verification and Performance Analysis for Chiplets

Engineering Presentation

10:48am - 11:06am PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionChiplets allow flexibility of design, enabling higher yields and faster turnaround times compared to monolithic SoCs. As part of creating the Cadence chiplet development solution, various areas for automation were identified to speed up the emulation and performance processes, thereby reducing the time required to bring chiplet designs to market.

Provision of emulation platforms early in the design cycle allow real hardware to be used by stakeholders such as system architects and software developers, allowing them to kick-off their activities significantly earlier, and reducing inter-team dependencies by creating a cohesive flow between all departments.

The verification flow uses outputs from design automation to generate the simulation & emulation platforms, the verification environment and tests. Tests are written using the Accellera Portable Test and Stimulus Standard (PSS) to allow C code to be generated for different target platforms, reducing duplication and saving effort and time.

The flow further generates the performance testing suite allowing metrics to be automatically retrieved between any defined source and end point using the Cadence System Performance Analyser. Availability of performance metrics early in the design cycle results in earlier design closure, reducing late architectural changes and increasing confidence in functionality and performance.

People

Joshua Lam

Batu Bayram

Automated Workload Analysis for Dynamic Voltage Drop Optimization and Faster Power Integrity Signoff in Complex SoC Designs

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs power integrity margins continue to tighten in advanced nodes and 3DIC designs, identifying the true worst-case PDN stress scenarios across multiple compute tiles has become increasingly complex and time-consuming. Traditional manual exploration of block workloads and vector combinations often requires expert intervention, exhaustive simulations, and significant runtime. To address this challenge, we present an automated RedHawk-SC framework that intelligently explores Reduced Order Models(ROM)-based block workload combinations to uncover high-stress PDN conditions with minimal runtime overhead.

The proposed flow introduces a novel scenario optimization algorithm that automatically generates, ranks, and prunes workload mixes for each compute tile, capturing die-package co-analysis through integrated RedHawk-SC simulations. The framework incorporates workload intelligence to learn per-block power impact, adaptive optimization to select optimal workload pairings using a greedy exploration algorithm, and scalability across multiple domains and workload vectors. Implemented as a Python wrapper, it delivers a plug-and-play architecture supporting automation and rapid integration within existing analysis environments.

This automated flow replaces expert-driven manual analysis with a data-guided methodology that ensures accurate prediction of voltage stress regions, early detection of grid vulnerabilities, and stronger silicon correlation. The approach simplifies scenario complexity, enhances reliability coverage, and accelerates sign-off for chiplet and 3DIC architectures.

People

Mohammed Yousuff Shariff

ARM

Engineering Poster

Automatic SDC Creation for Static Timing Analysis

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionTiming constraints are written to specify the design intent. SDC constraints are needed to properly: specify clocks in a design, instantiate on the correct pins/ports, compute uncertainty for clocks, and assert behavior/interaction of clocks in a design.

Timing constraints are typically manually written by the designer. The work can be tedious, time-consuming, prone to missing an interaction, or prone to calculation errors – leading to lengthy iterations, and the risk of hardware fails or excessive power.

We present a novel tool, ClockACE, to automatically create and apply all necessary timing constraints.
This saves significant amount of work for the designer. This prevents human error in computation or missing constraints. Any change to a clock spec is automatically re-computed within the timing run.
In this paper we present ClockACE for automatic constraint generation. We highlight a specific example using generated clocks, and the challenges with implementation of this clocking paradigm. We show how ClockACE handles this scenario automatically.

People

Engineering Presentation

Automating DFT Intelligence: Addressing TCPF Hotspots at Source Through Design Aware Test Points in Systemrdl-to-RTL Generators

11:15am - 11:30am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionAs SoC complexity scales, the resulting explosion in Automatic Test Pattern Generation (ATPG) pattern counts has become a primary driver of escalating manufacturing test costs. A critical bottleneck in this process is the emergence of "TCPF (Test cost Per Fault) Hotspots" across designs such as highly complex, auto-generated blocks such as Control and Status Registers (CSRs) that exhibit disproportionately high pattern counts due to deep combinational logic and structural bottlenecks like shared address buses. Traditional structural test point insertion often fails to address these architectural constraints effectively, as it operates on a late-stage netlist without design-specific context.

This paper proposes an "Extreme Left-Shift" methodology that moves DFT intelligence directly into the specification-to-RTL generation phase. By integrating Design-Aware Test Points (DATP) natively within a SystemRDL-to-RTL generator, we introduce architectural enhancements—including address parallelism, local protocol control, and optimized OR-reduction logic—that are structurally impossible to implement efficiently at the netlist level. This automated approach utilizes intelligent algorithms to analyze input RDL specifications and fine-tune DATP parameters at scale.

We demonstrate the efficacy of this methodology on a production-grade Tensor SoC. Experimental results show that while maintaining a minimal area overhead (~0.1%), the proposed DATP solution achieves a 4x improvement in TCPF at the IP level and a 50% overall reduction in ATPG pattern count at the top level compared to reference designs. By solving DFT bottlenecks at the source, this scalable framework provides a robust path for significantly reducing SoC test costs across the industry

People

Engineering Poster

Automotive Logic Test Power Management

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionTest coverage, test time, and test power are tradeoff on automotive system logic test. Unlike test coverage and test time, power is critical factor which is hard to be predicted and evaluated when implementation. Logic test usually has large amount of registers toggled at the same time and results in scan shift IR drop which might fail the test. Reducing pattern toggle would result in longer test time. Time consuming iterations for months are required to validate and fine tune scan structure with lower peak current until IR analysis is completed
Automotive System Logic Test Power management includes two parts: Pseudo-CPM Analyzer for test current prediction, and ASKA + POWA for shift power reduction. It helps user to fine tune design during design phase and IR drops reduce 3.2% with add-on clock skew on real product. The product also met design spec on logic test's coverage/test time/power and got silicon proven.

People

Research Manuscript

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 101A

AI2-I. AI/ML Algorithms and Models

DescriptionThis paper presents the first self-evolved logic synthesis framework, which leverages Large Language Models (LLMs) in a multi-agent setup to autonomously improve the source code of ABC. Our approach builds upon recent work in LLM-driven code evolution and extends the idea to the substantially more complex monolithic ABC codebase. We bootstrap the process with established human-designed optimizations and external research code. And in each iteration, the agents propose and implement code modifications which are then validated for correctness and evaluated on standard benchmark circuits to provide quality-of-result (QoR) feedback. Over time, the framework organically discovers improvements beyond the initial heuristics and complete the coding evolution autonomously in the whole ABC repository, effectively learning-to-progress better synthesis tool.

People

Cunxi Yu

University of Maryland/NVIDIA

Haoxing Ren

NVIDIA

Exhibitor Forum

Autonomously Handling of Digital Blocks From Initial Concept to Timing Constraints

4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionHu-mind.ai VLSI Teammate autonomously handles the full design cycle of a digital block, from initial concept to timing constraints. The Teammate execute these key phases: (1) Architecture: Transforming definitions into formal architecture documents. (2) RTL Design: Generating high-quality RTL code from architectural specs. (3) Test Planning: Drafting comprehensive test plans for robust verification. (4) Verification: Building SystemVerilog environments and test cases based on the test plan. (5) Debug: Running simulations and resolving design issues. (5) Timing: Composing SDC (Synopsys Design Constraints) for synthesis. Whether you're an RTL designer, a verification lead, or a physical design engineer, this shows how the VLSI Teammate augments your workflow to hit tape-out faster. With VLSI Teammates, every engineer steps into the role of a team leader. Communication with your virtual team is facilitated through a command-line interface, a web interface, or via your preferred instant messaging application on any device.

People

Gadi Laufer

Hu-mind

Research Manuscript

B-Flex: Exploration of Broader Flip-Flop Design Space Based on FSM Exhaustive Search

12:03pm - 12:16pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionFlip-flops (FFs) are a critical component affecting system-level power, performance, and area (PPA). Many logic-based FF design methods have been introduced to expand the scope of topology exploration beyond intuition. However, their exploration scope is still limited to 2-bit finite state machines (FSMs) because of inefficient search space representation. We present B-Flex, an automated FF FSM search that integrates a complete, graph-based behavioral equivalence check into a pruning-based generative search. This efficient and scalable approach vastly expands the design space and allows exhaustive exploration of 3-bit-state FSMs. B-Flex has identified over 568 million valid FF mechanisms, including many novel 3-bit-state FF designs. Topology synthesis on 20 sampled FSMs has produced several high-performance FF circuits that outperforms conventional FFs. For instance, FF1, achieves a 2.53× speedup over a transmission-gate FF (TGFF) and improved metastability window at 0.9 V.

People

Hyunsung Jeong

UNIST

Kyounghun Kang

Korea Advanced Institute of Science and Technology (KAIST)

Wanyeong Jung

KAIST

Jongeun Lee

Ulsan National Institute of Science and Technology (UNIST)

Research Manuscript

Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence

11:50am - 12:03pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS6. Time-Critical and Fault-Tolerant System Design

DescriptionThe increasing adoption of GPUs in real-time systems necessitates precise timing analysis for GPU thread blocks to ensure overall system predictability. However, the uncertainties of branch executions within GPU warps impose significant barriers for predicting the worst-case execution time (WCET) of the thread block. Existing WCET analysis for thread blocks typically assumes deterministic warp execution paths, which is unrealistic given the dynamic control flows of threads within the warps. Moreover, as the warp scheduler operates as a black box, the analysis must rely on relaxed scheduling assumptions, resulting in overly-pessimistic bounds in order to cover edge scenarios. This paper first establishes the need for static analysis by showing how branch divergence can trigger timing anomalies and influence block WCETs. We then develop an exact WCET analysis for a GPU thread block under the same scheduling constraints as prior work while not imposing any warp execution path assumptions. Furthermore, by enforcing a practical constraint on warp executions, we present a tighter analysis that enhances system predictability. Experiments show that the proposed analysis under warp execution constraints significantly reduces the WCET estimations of GPU thread blocks (by 19.13% on average and up to 39.39%).

People

Shuai Zhao

Chen Jie

Yaowei Liang

Mingyue Cui

Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

Research Manuscript

10:43am - 10:56am PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionCircuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness. Our code is avaiable at https://anonymous.4open.science/r/DeepSeq3-6760

People

Jingyi Zhou

Tsinghua University

Zhengyuan Shi

Jiaying Zhu

Ziyang Zheng

Qiang Xu

Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination

Research Manuscript

3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionDespite recent progress, every CPU fuzzer explores only a narrow slice of the vast micro-architectural state space due to its fixed mutation and feedback biases. While different fuzzers thus excel in disjoint regions, naïve combination fails because of conflicting strategies, seed pollution, and early saturation.
LiFU introduces micro-architecture-aware orchestration that dynamically profiles heterogeneous fuzzers, detects complementary strengths, decreases harmful interactions, and steers each fuzzer in real time using coverage and bug feedback, augmented by semantic seed triage.
Evaluated on the BOOM core, LiFU achieves 93.4% line, 43.6% FSM, and 95.7% condition coverage (90.1%, 75.0%, 78.3% on Rocket) with around 40% fewer tests than the best standalone fuzzer, consistently closing long-standing verification gaps in modern CPU.

People

City University of Hong Kong

Ning Wang

City University of Hong Kong

Zhe Jiang

South East University

Engineering Poster

Beyond Hierarchical Static Verification: Smart Stubbing for Next-Gen AI Accelerators

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern AI accelerators, such as Meta's MTIA, rely on massive arrays of Processing Elements (PEs) to maximize compute density. This architecture creates a design structure known as MIMs (Multiple Instantiated Modules). While these repetitive structures are essential for physical design optimization, they create a verification nightmare when doing flat analysis. Most modern flows rely on hierarchical verification using abstract models of smaller blocks at top level. However, in massive AI chips even this approach falls short due to the sheer volume of redundant Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) checks generated when large subsystems are instantiated repeatedly, causing chip-level flow runtimes to become unmanageable.

This paper presents a static verification methodology designed to overcome these scalability challenges in reticle-limit AI chips. While standard hierarchical flows utilizing Block Abstract Models attempt to manage complexity, the physical repetition of MIMs results in top analysis runs exceeds 26 hours and consuming up to 12x more memory due to redundant reporting.

To address this, we propose an RTL-based "stubbing" technique that selectively isolates unique instances of large blocks, such as Processing Elements, while neutralizing redundant copies via parameterized RTL defines. By shifting signoff to the block level and reducing the scope of top-level analysis, this methodology reduces the number of flat instances from 14.4 billion to 1.1 billion. Consequently, this approach eliminates redundant crossings, slashing verification runtime by 90% (down to 3.5 hours) and significantly reducing storage requirements, thereby enabling faster design convergence and feedback loops

People

Engineering Poster

Beyond Scripting: API Based HDL Generation

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionLooking at the block diagram of any modern SoC – whether a standalone device or a chiplet – and you will see that most of the blocks, and die area, consists of generated logic. From regular structures like RAMs and ROMs, to semi-regular structures like control/status register and NoCs, to entire processors, the HDL source and other input files for these blocks is produced by tooling from a higher-level specification, not typed by designers or output by AI. My work revolves around raising the level of abstraction used when writing HDL generators beyond scripts that output text. I propose that generators should not generate HDL text directly as with a "script", rather generators should be written with an API to assemble the HDL for output. This assures that the generator can only output syntactically valid HDL, and that errors are reported in the context of user input. This is especially important when an HDL generator is product, where failures and poor error reporting result in higher support costs for vendors, and poor outcomes for customers.

People

Jack Greenbaum

INTEGRITY Security Services

Work in Progress

Beyond Static Policies: Dynamic-PRAC for Balanced and Efficient Rowhammer Mitigation

6:44pm - 6:44pm PDT Monday, July 27 Exhibit Hall

DescriptionRowhammer attacks repeatedly activate DRAM rows and cause bit flips in adjacent rows. DDR5 introduced Per-Row Activation Counting (PRAC) to address this, but static thresholds and unnecessary distant-row refreshes limit its efficiency. This paper proposes Dynamic-PRAC, which adapts mitigation thresholds based on service-queue utilization and refines refresh actions by row distance. Experiments show that Dynamic-PRAC improves performance over PRAC, MOAT, and QPRAC while lowering overhead. Security results further demonstrate the lowest unmitigated activation count and up to 73% reduced energy use, offering an efficient and balanced Rowhammer mitigation mechanism.

People

POSTECH (Pohang University of Science and Technology)

Jinkyu Jeong

Yonsei University

Research Manuscript

BiBNN: 88.6% Computation Reduction in Bayesian Neural Networks via Post-Training Bernoullization

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionDeep neural networks tend to make overconfident predictions on unseen data, potentially raising risk in safety critical domains. Bayesian neural networks (BayesNNs) can estimate the uncertainty of prediction results, by modeling the uncertainty of model weights. However, BayesNNs have expensive
computing costs due to repeated sampling while evaluating uncertainty, which makes them inapplicable in practice. This work proposes a binarization framework for BayesNN, named Binarized Bayesian Neural Network (BiBNN), thus unlocking the potential for applications on embedded devices. We train real latent weight with Gaussian prior distribution by Variational Inference and use binary weight with Bernoulli distribution to perform inference. Experiment results show that the BiBNN retains similar uncertainty evaluation capability but with only 11.4% computing cost when compared to BayesNN. And BiBNN outperforms binary neural network by 1.5% on the CIFAR-10 dataset in terms of inference accuracy.

People

Research Manuscript

Bident: Optical Logic Synthesis via Optimal Configuration of Binary-Combiner Trees

5:03pm - 5:16pm PDT Tuesday, July 28 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionDespite decades of success, CMOS technology is increasingly constrained by power dissipation and propagation delay, thus motivating the exploration of photonic integrated circuits as an alternative for high-speed, energy-efficient computing. However, existing optical logic synthesis frameworks rely on an oversimplified efficiency factor model that fails to accurately capture physical attenuation and the hierarchical nature of signal degradation. This work presents Bident, a comprehensive optical logic synthesis framework that provides a physically accurate loss model and achieves optimal combiner configuration. We introduce the binary aggregate model, which explicitly reflects the binary-tree topology and input ordering in multi-input combiners. Based on this model, the Huffman tree optimization guarantees optimal Y-branch combiner configuration without requiring additional hardware resources. Meanwhile, a greedy algorithm optimally employs directional couplers at the leaf layer of a binarycombiner tree to achieve harmonic-mean efficiency at minimal hardware cost. Experimental results demonstrate that Bident achieves superior signal-attenuation reduction and lower switch cost than state-of-the-art methods, using both the conventional efficiency factor model and our binary aggregate model. A schematic-level optical circuit simulation further validates the feasibility and effectiveness of our binary-combiner configurations.

People

Jun-Wei Liang

Iris Hui-Ru Jiang

Kai-Hsiang Chiu

BIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Reasoning for RTL Synthesis and Summarization

Engineering Presentation

11:00am - 11:15am PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionAutomating Register-Transfer Level (RTL) code generation and summarization is critical for improving hardware design productivity and reducing time-to-market. However, existing approaches struggle due to limited Verilog and VHDL training data and the structural concurrency inherent in hardware description languages (HDLs). We propose BiMem-RAG, a dual-memory retrieval and bidirectional reasoning framework for HDL synthesis and documentation. BiMem-RAG combines (i) an exemplar memory of specification-to-code and code-to-summary pairs indexed using joint code and abstract syntax tree embeddings, and (ii) an analogical memory capturing reusable hardware design patterns such as sequential and combinational logic. The system employs modular decomposition, reinforcement-guided retrieval, and backward verification to improve semantic fidelity and reduce hallucinations. Experiments on Verilog and VHDL benchmarks demonstrate up to 19 percentage-point improvements in Pass@1 and 9-point gains in ROUGE-L over strong baselines. These results show that structured retrieval and verification significantly improve RTL generation and summarization, enabling more reliable hardware design automation.

People

Prashanth Vijayaraghavan

Research Manuscript

BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis

3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionIn advanced packages, large power/ground (P/G) planes are essential for power integrity but prone to warpage. While a uniform metal-density constraint combats warpage, mandatory degassing holes complicate adherence and degrade IR-drop. We propose BLADE, the first P/G plane synthesis methodology that enforces this constraint while optimizing power integrity. BLADE expands P/G planes from skeletons under metal density control to ensure connectivity, naturally leaving holes for degassing. Guided by a fast IR-drop evaluator, our bi-level Bayesian optimization framework efficiently navigates the design space. Experiments on six SiP cases demonstrate that BLADE satisfies the metal-density constraint and achieves superior IR-drop performance.

People

Siyuan Liang

Shanyi Li

Leilei Jin

Yuan Pu

Technical University of Munich

Yushen Zhang

Zhen Zhuang

Technical University of Munich

Kai-Yuan Chao

Siemens

Ulf Schlichtmann

Tsung-Yi Ho

Boosting IP Quality and Productivity Through Ipdelta Profile-Driven Change Detection

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAbstract:
Incremental changes are common during IP delivery, with approximately half of IP releases involving limited updates such as view additions, PVT updates, cell fixes, or layout modifications. While expected, these changes significantly complicate IP qualification, as conventional version-to-version validation often produces excessive false positives, increasing debug effort and slowing delivery cycles. Efficiently distinguishing intended modifications from unintended regressions is therefore critical to maintaining IP quality at scale.

This paper presents a profile-driven IP validation framework deployed at STMicroelectronics using Solido IPDelta and integrated within the internal IP QA infrastructure. The approach introduces predefined validation profiles that explicitly model expected changes between IP versions, such as layout-only updates, layout-plus-abstract changes, netlist updates, or liberty model revisions. By waiving known, intentional differences through profile definitions, the framework isolates unexpected inconsistencies for focused analysis across CAD views including GDS, OA, LEF, DEF, netlists, and liberty formats.

Applied across diverse IP types and technology nodes, the profile-based methodology significantly reduces validation noise and improves debugging efficiency. Measured results demonstrate up to a 60% reduction in manual QA effort per IP delivery, while provide a scalable and consistent validation solution for evolving IP ecosystems. This work shows that profile-driven change detection enables robust, efficient IP qualification in incremental delivery environments.

People

Research Manuscript

Brain-Like Hyper-Dimensional Graph Learning System with Hardware-Efficient Adaptive Sparsity

1:30pm - 1:42pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionGraph neural networks (GNNs) are crucial for numerous applications, yet their huge computational demands often lead to suboptimal performance.
Hyper-Dimensional Computing (HDC) is a brain-inspired learning approach for efficient and robust learning.
HDC-based Graph Learning (HDGL) shows significant improved computational efficiency and accuracy by learning graph representations in a high-dimensional space. Despite these advantages, general-purpose computing platforms such as CPUs and GPUs are insufficient for efficiently handling HDGL tasks.
In this paper we propose an accelerator called HDGAS through algorithm and hardware co-design for HDGL.
Based on the insight that not all node features in a graph are equally important, we propose to jointly optimize a lightweight filter with the HDGL model to dynamically identify and eliminate less significant node features during runtime.
Moreover, we design a specialized system architecture for end-to-end HDGL acceleration, harnessing the proposed dynamic sparsification technique in tandem with the inherent SpMM operations within HDGL.
Extensive experiments demonstrate that HDGAS achieves $6.76\times$ ($69.31\times$) speedup and $7.58\times$ ($80.12\times$) energy-efficiency improvements over GNN accelerators (GPU).

People

Haomin Li

Fangxin Liu

Zongwu Wang

Shiyuan Huang

Shanghai University

Ning Yang

Chenyang Guan

United Imaging Intelligence Co., Ltd.

Tao Yang

Huawei

Xinran Liang

Haibing Guan

Breaking Sequential Depth Barriers: An FSM-Driven Bridge for the Formal Verification of Virtually Address-Mapped Hardware Registers

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis paper presents the formal verification of a subsystem with indirect read mechanisms and a nonstandard access protocol. Verifying registers using the control and status register (CSR) protocol typically requires a proof accelerator to convert a standard bus into the CSR protocol. However, this secure design uses a custom protocol, creating unique formal verification challenges. In this design, writing to an IP register through the subsystem is straightforward and followed by polling a status register to check the write data status. The read data is available at a different address within the subsystem register map.
To address this, a protocol-to-protocol AMBA bridge is developed. The bridge converts write commands from the verification intellectual property (VIP) into writes for the device under test (DUT) and reads data from the DUT, returning it to the corresponding VIP address. Because the DUT does not return data at the same address, address conversion logic with several finite state machines (FSMs) is implemented. This approach allows the VIP to perform checks as expected, despite the indirect read mechanism.
Counter value abstraction is used to manage delays and simplify verification, ensuring efficient completion. This approach enables robust and efficient register verification for complex subsystems and saves significant time compared with the UVM register model.

People

Erik Seligman

Breaking the EDA Bottleneck for Agentic Chip Design

Exhibitor Forum

4:00pm - 5:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionOboe is accelerating the future of silicon development with next-generation Emulation and Waveform platforms purpose-built to unlock true agentic chip design. While AI has yielded remarkable productivity gains in software, hardware engineering lags behind as agents are severely bottlenecked by legacy EDA infrastructure. During frontend verification, both human engineers and autonomous agents waste critical time waiting for traditional simulation engines to return results, stalling the iterative loop and limiting agentic effectiveness. As agents drop the cost of forming hypotheses and generating tests, the burden of data generation, evaluation, and retrieval only become more acute. In this presentation, we discuss Oboe’s solutions for accelerating simulation, bringing the digital verification workflow to the speed of agents and ultimately enabling rapid and accurate root cause analysis.

People

Jonathan Birjiniuk

Oboe

Engineering Poster

Breaking the Simulation Wall – Practical Acceleration for Pre-Silicon Validation

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionNext-generation SoCs demand robust and high-confidence DDR subsystem verification, yet traditional simulation struggles to keep pace. Long-duration DDR behaviors—such as training loops, refresh cycles, retention checks, and hours of sustained traffic—consume excessive simulation time and slow down project velocity. These time-intensive patterns often stall coverage closure, push out debug windows, and delay subsystem readiness.

This work showcases a high-performance verification acceleration strategy using the Siemens Veloce Strato CS hardware emulation platform to remove these bottlenecks. By transitioning existing UVM stimulus into an emulation-optimized transactor environment, the flow executes long-running DDR workloads at speed order of magnitude faster while maintaining cycle-accurate behavior and full debug correlation. The result is faster iteration, increased test throughput, and earlier discovery of timing-sensitive issues that rarely surface in conventional simulation schedules.

Key highlights include an optimized DDR command/data transactor architecture for emulation, transparent reuse of simulation sequences, and targeted debug techniques purpose-built for hardware-assisted verification. This accelerated DDR flow enables teams to run extensive, hours-to-days traffic profiles within practical timelines—transforming verification productivity and delivering higher confidence in subsystem quality ahead of tape-out.

People

Research Manuscript

Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionYield Multi-Corner Analysis validates circuits across 125+ Process-Voltage-Temperature corners, creating combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^5$ samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier.
We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11\%) with zero tuning, reducing total validation cost by over $10\times$.

People

Wei Xing

University of Sheffield

Kaiqi Huang

Shenzhen University

Jiazhan Liu

College of Mechatronics and Control Engineering, Shenzhen University

Hong Qiu

Macau University of Science and Technology

Shan Shen

Nanjing University of Science and Technology

Research Manuscript

BREW-RC: Bit-Exact Recovery of ECCs from Write Timing in ReRAM Crossbars

12:03pm - 12:16pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC3-II. Hardware Security: Attack and Defense

DescriptionWe present BREW-RC, a non-invasive technique that uses a timing side channel to reverse engineer error-correcting codes (ECCs) in ReRAM crossbar memories. ECCs use a parity submatrix to extend data words with parity bits, forming codewords. These parity bits cannot be read directly, but BREW-RC reveals them by using write latency variability to determine the aggregate polarity of codeword transitions. Timing perturbations caused by ECC parity bit updates are encoded as a SAT instance whose solution yields the bit-exact parity matrix. Knowledge of the parity matrix enables: (1) improved timing models for side-channel attacks/mitigations and latency-sensitive applications, and (2) ECC-aware reliability characterization of devices whose error correction capabilities are unadvertised. We demonstrate BREW-RC on two commercial ReRAM products, recovering the complete ECC from multiple samples of each.

People

Tyler Sheaves

Alric Althoff

ARM

Dustin Richmond

Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe rapid adoption of chiplet-based architectures and high-speed die-to-die interconnects primarily driven by AI/ML massive data throughput requirements and integration complexity presents significant mixed-signal verification challenges. Traditional Digital Mixed-Signal (DMS) flows lack analog fidelity, while Analog Mixed-Signal (AMS) flows struggle with scalability and manual overhead. To address these fundamental limitations, Analog Port, in close collaboration with Siemens EDA, developed a unified, top-down verification methodology designed to bridge the gap between analog fidelity and digital performance.

This innovative approach leveraging Symphony Pro, part of the Solido Simulation Suite, extends the conventional UVM based digital verification framework to mixed-signal domain, enabling a holistic verification strategy while overcoming tool fragmentation and data integrity issues. It seamlessly combines high-fidelity SPICE simulation for critical analog blocks with high-performance digital simulation for the broader system.

In this presentation, we will demonstrate how Analog Port achieved up to 26X memory savings and more than 3X performance gain for their RX and TX simulations. We will also explore this novel methodology and its implementation, showcasing how it successfully verified a complex 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface, significantly enhancing productivity, improving silicon quality, and reducing time-to-market by resolving traditional mixed-signal verification trade-offs.

People

Engineering Poster

Bridging Hardware-Software Abstraction In UVM Verification

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIn advanced verification environments, standard UVM monitors may not offer enough flexibility or abstraction to capture and relay all relevant hardware events to the testbench. To solve this, a standardized mechanism is needed that allows smooth, event-driven communication from hardware interfaces to the UVM environment. This is especially crucial when the testbench must respond to complex hardware events—such as status changes, signal transitions, or protocol-specific conditions—and use these events to drive scoreboards, perform checks, or trigger reference model transactions. By adding proxy objects that serve as intermediaries between the hardware (HDL) and software (UVM) domains, the testbench can respond to hardware events in a modular and reusable way, reducing dependence on direct signal polling and improving maintainability. This approach is generally applicable to any hardware signal that needs to stay synchronized with the UVM environment.

People

Bhaskar Vedula

Chandrakanth Betageri

Bridging Physics and Engineering: Quantum EDA for Superconducting Qubits and Amplifiers

Engineering Special Session

3:30pm - 5:00pm PDT Monday, July 27 Seaside RM 7

EDA

Quantum

DescriptionAs quantum computing continues to advance, superconducting qubits have emerged as a leading platform due to their scalability and strong compatibility with microwave engineering. At the same time, quantum amplifiers are essential for enabling high fidelity readout by amplifying fragile quantum signals while minimizing added noise. Designing these systems, however, remains challenging due to tight performance margins, dense integration, cryogenic operation, and complex interactions between electromagnetic, circuit, and quantum effects. In this talk, I discuss how Quantum EDA techniques—tailored to the unique requirements of superconducting quantum circuits—can help bridge physics driven design and scalable engineering practice. I will highlight how EM and eigenmode analysis, automated quantum parameter extraction, and nonlinear circuit co simulation can be combined to guide the design and optimization of qubits, readout resonators, and quantum amplifiers within a unified workflow. These approaches illustrate how Quantum EDA can accelerate development toward robust and scalable superconducting quantum systems.

People

Chris Mueth

Bridging Quantum, AI, and EDA: The Next Frontier of Design Automation

Research Panel

10:30am - 12:30pm PDT Wednesday, July 29 Mtg Room 104A

Design

DescriptionQuantum technologies are rapidly transitioning from academic curiosity to practical enablers of next-generation electronic design automation (EDA). Yet the real opportunity lies not only in quantum computing itself, but in the convergence of quantum simulation, materials modeling, AI-native design, and system-level automation. This panel brings together leaders across quantum hardware, software, and industrial design workflows to examine how quantum technologies—paired with frontier AI—will transform the semiconductor and system-design landscape over the next decade.

Today's design challenges have outgrown classical scaling curves. Whether optimizing advanced node devices, discovering novel materials, modeling parasitic effects, or designing 3D-IC systems with extreme multiphysics coupling, classical simulation methods are straining under exponential complexity. Emerging quantum-accelerated approaches offer breakthrough potential: Hamiltonian-based solvers for nanoscale transport; quantum-enhanced simulation for chemical and materials discovery; quantum optimization methods for scheduling, routing, and verification; and hybrid quantum-classical pipelines that integrate seamlessly with existing EDA flows.

At the same time, generative AI and large language models (LLMs) are redefining design productivity. The intersection—Quantum × AI × EDA—is creating a new paradigm where quantum simulation feeds AI-driven design agents, AI discovers optimal materials for quantum and classical devices, and EDA frameworks orchestrate end-to-end system exploration. This compounding loop is catalyzing a shift toward Materials Design Automation (MDA), automated device co-optimization, and rapid multi-physics exploration at atomic accuracy.

This panel will explore four key themes:

1. Quantum Simulation for Materials & Devices: How quantum-accurate modeling (AIMD, MLFF, QMC, variational quantum solvers) unlocks breakthroughs in semiconductors, batteries, photonics, and superconducting components.

2. Quantum Hardware and Software Stack Evolution: Practical roadmaps, error-correction thresholds, algorithmic readiness, and how near-term quantum systems can augment industrial design workflows.

3. AI-Native and LLM-Driven Design Automation: How foundation models, retrieval-augmented simulation, and autonomous design agents interface with quantum tools to accelerate PPA and manufacturability.

4. Industrial Adoption & ROI: What it will take for design teams—fabless, IDM, EDA vendors, and hyperscalers—to integrate quantum capabilities into real production flows.
The session will conclude with a forward-looking discussion on how quantum technologies may reshape the future of design automation—shifting the industry from traditional scaling to physics-accelerated, AI-co-designed innovation. Attendees will leave with a clear understanding of what's real, what's coming, and how to prepare their organizations for the quantum-enabled EDA era.

People

Jimmy Cheng

Bridging the Modeling Gap: State-Aware Liberty Enhancements for Multimode IP Designs

Joseph Bardin

Google / UMass Amherst

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern SoCs integrate a wide range of IP types: I/O's, SerDes, PLLs, DACs, ADCs, memories...each operating across multiple protocols, voltage domains, and performance modes. While characterization flows accurately capture this mode dependent electrical behavior (including distinct thresholds, load limits, slew limits, and rail sensitivities), the Liberty (.lib) format remains largely scalar and static.

Key attributes such as max_capacitance, max_transition, and voltage_map can only be expressed as fixed per pin values, and existing constructs like when or mode_support affect only logical activation, not the underlying electrical state of the IP.

This fundamental limitation forces designers to maintain multiple mode specific .lib files, which increases configuration overhead and risks silent extrapolation during sign off when tools operate outside valid characterized ranges.

We propose a State Aware Liberty Modeling approach that introduces explicit constructs for both electrical configuration states and operational modes (protocol specific electrical constraints). This allows voltage mapping, thresholds, load limits, and slew limits to vary per mode within a single unified library. These enhancements generalize across all IP types, improving silicon to model correlation and enabling robust, mode accurate timing and power sign off for next generation SoC architectures.

People

SAURABH SRIVASTAVA

Bringing Graphs Closer to Memory: Compiler-Driven Data Transfer Reduction in the PIM Accelerator

Research Manuscript

10:43am - 10:56am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionProcessing-in-Memory (PIM) alleviates the memory bottleneck of modern AI workloads; however, its limited computational capability often necessitates hybrid architectures that integrate PIM with nearby processing units. In such heterogeneous systems, communication and host-side overheads remain dominant performance bottlenecks. Our profiling of SK hynix's AiMX reveals that CPU–AiMX communication and CPU-side data reordering account for 50.07% of end-to-end LLM prefill and 78.36% of decode execution time. Notably, 54.03% of reordering operations occur adjacent to AiMX-executable nodes, indicating significant untapped potential for near-memory execution to eliminate unnecessary data movement.
We propose a graph compiler that jointly optimizes computation and data movement for AiMX-based acceleration. The compiler performs (1) graph simplification to maximize AiMX-kernel coverage, (2) DMA-assisted tensor reordering and layout redefinition to offload host-side preprocessing, and (3) operator fusion to suppress redundant memory transfers. Integrated into the ONNX Runtime, our approach improves 2.00~2.73x speedup in the prefill phase and 18.50~38.29x in the decode phase, demonstrating the substantial benefits of graph-level co-optimization for PIM-enabled LLM inference and achieving performance comparable to hand-tuned AiMX execution.

People

Solution Advanced Technology, SK hynix

Ilkon Kim

Solution Advanced Technology, SK hynix

Seon Wook Kim

Korea University

Exhibitor Forum

BRONCO AI: AI-Native EDA in Production: Lessons from Customer Deployments

11:15am - 11:45am PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionBronco Debug in production is able to tackle multi-day, multi-person debugs in a matter of minutes. This session covers some of Bronco's AI-native EDA tooling that enables this work at full-chip SoC scale.

People

Exhibitor Forum

BRONCO AI: Introducing Dvbench: A Production-Grade Benchmark for Design Verification AI

2:30pm - 3:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

DescriptionAn announcement and overview of DVBench — Bronco's to-be-released benchmark that evaluates AI across real DV tasks spanning multiple data modalities and design hierarchies from block-level to full SoC, at production difficulty.

People

Jeffrey Pan

Bronco AI

Research Manuscript

BSGCN: Taming Diverse Sparsities in GCNs via Adaptive Band-Segmentation and Tailored Caching

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionAbstract
Graph Convolutional Networks (GCNs), a foundational technology
for relational data applications, are often bottlenecked by irregular
memory accesses caused by sparse graph structures. Existing accelerators face two fundamental limitations: their rigid dataflows
cannot adapt to varying graph sparsities, and their narrow focus on
high-degree nodes (HDNs) leads to systematic neglect of memory
traffic from the vast number of low-degree nodes (LDNs).
To address these issues, this paper introduces BSGCN, an accelerator built on a novel band-segmentation strategy. This approach partitions the graph such that the majority of LDNs are
grouped into large bands with similar data reuse characteristics,
while the remaining nodes form small bands containing only a few
LDNs. This segregation enables two co-designed innovations: 1) a
Band-Segmented Dataflow (BSD), which applies a tailored traversal strategy to each band type to handle diverse sparsity patterns,
and 2) a Band-Segmented Caching (BSC) hierarchy, combining a
specialized caching policy to exploit the reuse potential of LDNs
with a dedicated pinning mechanism for HDNs. Evaluation results
show that BSGCN achieves average speedups of 1.41× (up to 4.80×)
over state-of-the-art accelerators, while reducing DRAM traffic by
24.24% and improving energy efficiency by 1.30×.

People

BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs

Weisheng Zhao

Beihang University

Research Manuscript

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionBackside power delivery networks (BSPDN) provide superior power integrity while freeing backside routing resources. However, existing works fail to fully exploit these resources for power, performance, and area (PPA) optimization through strategic net allocation. This paper presents a co-optimization framework that maximizes PPA by strategically routing both clock and signal nets on the backside, enabling double-side routing. Experimental results demonstrate 88.1% IR-drop reduction, 23.0% frequency improvement, 10.9% power savings, and timing improvements (66.3% WNS, 40.2% TNS) over FSPDN with negligible nTSVs overhead.

People

Leilei Jin

Haoyang Xu

Siyuan Liang

Zhen Zhuang

Zhou Hu

Zixiao WANG

Bei Yu

Rongmei Chen

Tsung-Yi Ho

BSPDN: A Power Delivery Architecture for 19.8% Core Power Reduction and 9.3C Thermal Mitigation in Next-Generation AI Processors

Engineering Poster Gladiator

5:00pm - 5:08pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis work evaluates the performance and thermal benefits of Backside Power Delivery Networks (BSPDN) compared to traditional Frontside (FSPDN) architectures. Instead of push to max-performance, we proposed to focus on power efficiency. Our results demonstrate that BSPDN achieves a 19.8% reduction in power consumption under nominal operating conditions compared to FSPDN. Furthermore, the structural optimization of the power grid significantly enhances thermal dissipation, resulting in a 9.3°C reduction in peak operating temperature. These findings suggest that BSPDN is a critical enabler for next generation datacenter.

People

Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?

DAC Pavilion Panel

3:00pm - 3:45pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

DescriptionArtificial Intelligence is rapidly transforming semiconductor design automation, promising major gains in productivity across the design lifecycle — from system requirements and architectural specifications to verification, layout optimization, and design closure. Yet unlike traditional EDA tools, AI systems rely on proprietary data, evolving models, and complex integrations with mission-critical workflows. This raises a fundamental and provocative question for the industry: would you trust an AI system to make decisions that directly impact tape-out success?

This panel brings together leaders from startups, established EDA vendors, and semiconductor design houses to explore how AI is being applied to both upstream activities such as requirements definition and specification development, as well as downstream design and verification tasks. The discussion will examine trust, explainability, data ownership, and accountability when AI influences critical engineering decisions.

Panelists will debate the strategic build-versus-buy decision for AI-based design automation, including whether AI-generated requirements should be treated as authoritative inputs and how organizations can balance innovation with risk in cost- and schedule-critical silicon programs.

People

GM IP and Data Management Business

Engineering Presentation

Building an Ontology-Driven Knowledge Graph for Constraint-Aware Navigation of Semiconductor Design Documents

11:15am - 11:30am PDT Monday, July 27 Seaside Ballroom A

EDA

DescriptionSemiconductor design involves extensive documentation, often spanning hundreds of pages in documents with highly intricate and complex internal relationships, making manual navigation and cross-referencing highly inefficient. To overcome this critical bottleneck, we implemented a solution that significantly reduces manual effort by leveraging an Ontology-based Knowledge Graph (KG). Our core methodology involves defining a formal ontology to systematically model the diverse entities (e.g., modules, registers, protocols) and their complex dependencies across disparate documents (specifications, reports, manuals). This structured conversion process transforms unstructured conversion process transforms unstructured documentation into a unified, queryable KG, which is the key to easily mapping and understanding the intricate web of connections inherent in the design. This paradigm shift from keyword matching to relationship-aware knowledge representation significantly simplifies knowledge discovery. Furthermore, this meticulously constructed Knowledge Graph serves as the knowledge base for Graph RAG chatbot, which provides engineers with accurate, context-aware answers to natural language queries.

People

Research Manuscript

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

5:18pm - 5:30pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionThe scaling-up of large language models (LLMs) necessitates computing systems to have multi-processor-chip architectures, elevating the importance of chip-to-chip (C2C) communication. However, designing efficient C2C hardware architectures for LLM workloads faces three key challenges: generating realistic LLM-specific C2C traffic, accurately simulating hardware-level communication at scale, and efficiently exploring the exponentially large C2C design space. We propose C2C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator (switch/full-mesh, up to 512 chips), and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads. Validated against FPGA-based C2C prototypes, the C2C simulator achieves 2.46–8.23% end-to-end timing error across diverse traffic patterns. Its hybrid cycle & event model further accelerates large-scale simulation by up to 7.8× over a pure cycle-accurate baseline. Applied to a 32-XPU DeepSeek-R1-671B inference workload, C2C-Explorer identifies configurations that improve goodput by 44.1% and reduce memory by 98.4%. C2C-Explorer is open-source and available at https://anonymous.4open.science/r/C2C-Explorer.

People

Research Manuscript

Cache Where It Counts: Towards Workload-Aware I/O Coordination for NUMA Storage Systems

1:55pm - 2:08pm PDT Tuesday, July 28 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionModern Non-Uniform Memory Access (NUMA) servers equipped with distributed Non-Volatile Memory Express (NVMe) storage present new challenges for I/O coordination. First, conventional page cache allocators ignore storage topology, resulting in inefficient cross-node cache placement and performance issues. Second, CPU schedulers overlook cache and storage locality, causing frequent cross-node cache accesses and further degrading performance. Third, the OS page cache employs a rigid eviction policy that fails to adapt to diverse application workloads, while even programmable alternatives often require complex manual tuning. To address these challenges, we propose Laelaps, a workload-aware I/O coordination framework for NUMA storage systems. Laelaps introduces three key techniques: (1) storage-topology-aware page cache placement, co-locating cache pages with their backing NVMe devices; (2) storage-topology-aware I/O thread scheduling that aligns thread placement with cache distribution to minimize cross-node accesses; and (3) workload-aware adaptive page caching that automatically selects eviction policies based on observed application access patterns. Evaluation shows that Laelaps achieves 1.41× geometric mean throughput improvement with 3.5% runtime overhead.

People

Wenda Tang

Yanwen Wang

Yiduo Wang

Jie Wu

Cachence: Fine-Grained Cache Partitioning in Both Time and Space

Research Manuscript

4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionCache partitioning mechanisms improve system performance by judiciously adjusting cache space among applications. Its effectiveness can be enhanced by partitioning in both time and space. However, existing solutions are limited to only one dimension.

This paper presents Cachence, a fine-grained cache partitioning mechanism in both time and space. Cachence profiles cache access patterns with theoretically guaranteed accuracy while incurring fixed storage overhead. Based on runtime microarchitectural statistics, we also propose a lightweight yet precise performance prediction model. Our evaluation shows that Cachence outperforms existing approaches by an average of 9.5% to 28.2%, and up to 48.8% on a 16-core system.

People

Michigan Technological University

Diyu Zhou

Cacheparallel: Comprehensively Exploring Multi-Level Acceleration for Diffusion Models

Research Manuscript

1:30pm - 1:42pm PDT Wednesday, July 29 Mtg Room 101B

AI3-II. AI/ML Application and Infrastructure

DescriptionDiffusion models, despite their exceptional generative capabilities, are bottlenecked by slow inference owing to their complex architectures and multi-step iterative processes. Although caching is a promising acceleration method, previous approaches suffer from a tight coupling with specific network structures and low computational density. Moreover, caching is challenging to integrate with other methods to further enhance performance due to non-orthogonality, as simple integration often leads only to model performance degradation.

To address these challenges, we propose CacheParallel, a novel training-free scheme that optimizes both caching and parallelism at the intra- and inter-step levels to reduce the computational load and increase the computational density simultaneously. We first introduced the fusion node to abstract the network structures into generic pre-fusion and post-fusion computational streams. For the pre-fusion stream, we applied intra-step caching optimized by the proposed CPS algorithm. For the post-fusion stream, we exploit inter-step output correlations to enable parallel computing and boost computational density. To mitigate accumulated errors and non-orthogonality issues, an error correction mechanism was designed based on our observation of the inherent linear correlations of the models.

Comparative experiments showed that we achieved significant performance improvements across various models, with the peak improvement surpassing 100\%.

People

Qianru Lyu

Di Niu

Jinwei Xu

Jingfei Jiang

Xiangrui Yang

Sheng ma

Dongsheng Li

CADENCE DESIGN SYSTEMS: LLMs in Production With Chip Teams: Opportunities, Challenges, and Lessons Learned

Exhibitor Forum

10:30am - 11:00am PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionThe growing complexity and specialization of modern chips necessitate a fundamental shift in how we approach design and verification. Large Language Models (LLMs) present a timely and transformative opportunity to address key bottlenecks in chip design flows.

This talk will explore how the advanced natural language processing capabilities of LLMs can streamline design and verification processes, from automated verification plan generation to intelligent debug assistance—supported by real-world case studies. We will share insights from fine-tuning LLMs for DV-specific tasks, demonstrating measurable improvements in accuracy of LLMs on real-world examples.

Beyond the opportunities, we will discuss the challenges of deploying generative AI solutions in production chip design teams, including infrastructure constraints, reliability concerns, and building user trust. By integrating generative AI with modern methodologies and software stacks, this talk will outline how LLMs can accelerate chip design cycles and significantly reduce time to market for next-generation chips.

People

Kartik Hegde

CADSTROM: Beyond DRC: How AI-Driven Component Modeling Is Closing the Verification Gap Between Schematic and Silicon

Exhibitor Forum

5:15pm - 5:45pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionDesign verification has made enormous strides at the chip level, yet a stubborn class of errors continues to plague teams working at the board and system level — voltage mismatches, misconfigured interfaces, overlooked datasheet constraints, and derating violations that standard DRC tools weren't built to catch. These aren't exotic corner cases. They're fundamental checks that experienced engineers know matter but that are tedious to perform manually and easy to miss under schedule pressure. The result: unnecessary respins, late-cycle fire drills, and eroded confidence in design closure.

This session explores how AI-assisted validation can bridge that gap by automatically constructing detailed behavioral models for every component in a design — grounded in actual datasheet specifications, not heuristic rules — and running deterministic checks on interface compatibility, power sequencing, thermal derating, and bus configuration as the schematic evolves. Unlike LLM-based "copilot" approaches, this methodology produces findings that are verifiable, traceable, and citable back to source documentation, while keeping proprietary design IP fully protected.

We'll walk through anonymized case studies from design consultancies, medical device OEMs, and industrial electronics teams where automated validation uncovered previously unknown, fabrication-blocking issues early enough to resolve with a schematic edit instead of a board respin. Attendees will leave with a concrete framework for where AI-assisted verification fits alongside existing EDA workflows — complementing, not replacing, the tools and judgment they already rely on.

People

Margot Blouin

Cadstrom

Research Manuscript

Can Asymmetric Tile Buffering Be Beneficial?

4:30pm - 4:42pm PDT Monday, July 27 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionGeneral matrix multiplication (GEMM) is the computational back- bone of modern AI workloads, and its efficiency is critically depen- dent on effective tiling strategies. Conventional approaches employ symmetric tile buffering, where the buffered tile size of the input 𝐴 along the dimension 𝑀 matches the output tile size of 𝐶. In this paper, we introduce asymmetric tile buffering (ATB), a simple but powerful technique that decouples the buffered tile dimensions of the input and output operands. We show, for the first time, that ATB is both practical and highly beneficial. To explain this effect, we develop a performance model that incorporates both the benefits of ATB (higher arithmetic intensity) and its overheads (higher kernel switching costs), providing insight into how to select effective ATB tiling factors. As a case study, we apply ATB to AMD's latest XDNA2™ AI Engine (AIE), achieving up to a 4.54× speedup, from 4.8 to 24.6 TFLOPS on mixed-precision BFP16–BF16 GEMM, establishing a new performance record for XDNA2™ AIE.

People

Chengyue Wang

University of Illinois Urbana-Champaign

Qiran Pang

Xinrui Wu

The University of Texas at Austin

HyeGang Jun

University of Illinois

Luis Romero

EPFL

Endri Taka

Diana Marculescu

The University of Texas at Austin

Tony Nowatzki

Pranathi Vasireddy

Joseph Melber

Deming Chen

UIUC

Jason Cong

CANNON: A CXL-Based Near-Memory Processing Architecture for Approximate Nearest Neighbor Search on Real Hardware

Research Manuscript

1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 202C

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionApproximate Nearest Neighbor (ANN) search is a foundational primitive for AI applications such as Retrieval-Augmented Generation (RAG). CPU and GPU-based solutions face scalability bottlenecks due to limited local memory, while a multi-tier architecture using SSDs introduces high latency from coarse-grained I/O, mismatched with fine-grained data access patterns inherent to ANN search. We present CANNON (A CXL-Based Near-Memory Processing Architecture for Approximate Nearest Neighbor Search on Real Hardware), a fully offloaded Near-Memory Processing (NMP) architecture implemented on real CXL hardware. CANNON transforms the ANN search pipeline into a fine-grained, deeply pipelined dataflow architecture to maximize throughput, and introduces asynchronous hashing, a speculative execution mechanism that hides hash-check latency to prevent pipeline stalls. Evaluated on large-scale vector datasets, CANNON achieves up to two orders of magnitude performance improvement over state-of-the-art CPU and GPU baselines.

People

Research Manuscript

CAPA: Convertibility-Aware Mixed-Precision Accelerator for Asymmetric GEMM in Weight-Only Quantized LLMs

11:18am - 11:30am PDT Tuesday, July 28 Mtg Room 101A

AI4-II. AI/ML Architecture Design

DescriptionFP-INT GEMM accelerators for weight-only quantized large language models suffer from large partial sum (psum) overhead and a lack of precision-convertibility, limiting scalability. To mitigate this, we propose CAPA, an accelerator achieving high efficiency and versatility. (1) CAPA introduces Hybrid Delta Block Floating Point (HDBFP), a novel INT-based format that reduces psum overhead, preserves accuracy, and integrates BF16/FP16 arithmetic. (2) CAPA adopts Weight Decomposition to unify INT8 and INT4 arithmetic, enabling parallel processing. We demonstrate CAPA attains identical GPU accuracy, improving area efficiency by 3.98x and power efficiency by 4.38x over the FP-FP baseline.

People

Engineering Poster

Capacitance Modeling for Meander Co-Planar Waveguide Devices Used in Quantum Computers

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionSeveral companies have been developing quantum computers. Co-Planar Waveguides (CPWs) couple qubits in a quantum computer and are also used to probe the quantum state in qubits. The design of meander CPW devices is an emerging area where the modeling of signal conductor's capacitance is important. Due to the complex shape of a meander CPW, a field solver is exclusively used to find the total capacitance of the signal conductor of a CPW device. In this work, we show how to model 3D capacitance in a CPW efficiently. We properly decompose the space along the path of the signal conductor into multiple regions and thus reduce the complex 3D capacitance modeling problem to a set of smaller 3D capacitance problems. Some of these smaller 3D capacitance problems (where the segment of the signal conductor is straight) are treated as 2D capacitance problems for a fixed cross section, although the shape of the cross section can vary as one moves to a next cross section. Others (where the segment of the signal conductor is a half-circle, for example) are still 3D capacitance problems. These remaining true 3D capacitance problems are further reduced into equivalent 2D capacitance problems.

People

Research Manuscript

Capacitive Touchscreens at Risk: Recovering Handwritten Trajectory on Smartphone via Electromagnetic Emanations

10:43am - 10:56am PDT Tuesday, July 28 Mtg Room 202AB

Security

SEC3-I. Hardware Security: Attack and Defense

DescriptionThis paper reveals and exploits a critical security vulnerability: the electromagnetic (EM) side channel of capacitive touchscreens leaks sufficient information to recover fine-grained, continuous handwriting trajectories. We present Touchscreen Electromagnetic Side-channel Leakage Attack (TESLA), a non-contact attack framework that captures EM signals generated during on-screen writing and regresses them into two-dimensional (2D) handwriting trajectories in real time. Extensive evaluations across a variety of commercial off-the-shelf (COTS) smartphones show that TESLA achieves 77% character recognition accuracy and a Jaccard index of 0.74, demonstrating its capability to recover highly recognizable motion trajectories that closely resemble the original handwriting under realistic attack conditions.

People

Nanjing University of Aeronautics and Astronautics

Yuan Li

Shihui Zheng

Capbench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction

Research Manuscript

10:56am - 11:10am PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionWe present CapBench, a fully reproducible, multi-PDK dataset for capacitance extraction. The dataset is derived from open-source designs, including single-core CPUs, Systems-on-Chip, and media accelerators. All designs are fully placed and routed using 14 independent OpenROAD flow runs spanning three technology nodes: ASAP7, NanGate45, and Sky130HD. From these layouts, we extract 61,855 3D windows across three size tiers to enable transfer learning and scalability studies. High-fidelity capacitance labels are generated using RWCap, a state-of-the-art random-walk solver, and validated against the industry-standard Raphael, achieving a mean absolute error of 0.64% for total capacitance. Each window is pre-processed into density maps, graph representations, and point clouds. We evaluate 10 machine learning architectures that illustrate dataset usage and serve as baselines, including convolutional neural networks (CNNs), point cloud transformers, and graph neural networks (GNNs). CNNs demonstrate the lowest errors (1.75%), while GNNs are up to 41.4 times faster but exhibit the larger errors (10.2%), illustrating a clear accuracy–speed trade-off.

People

Engineering Special Session

Capturing Quantum Components in Quantum EDA

3:30pm - 5:00pm PDT Monday, July 27 Seaside RM 7

EDA

Quantum

DescriptionAs we drive toward building the Quantum EDA (QEDA) stack, a familiar enemy stands in our way. To fully model a quantum chip—whether accurately capturing the physics of an individual qubit or solving the compact model of an entire processor—one must solve the quantum many-body problem. This is the "exponential wall" that pushes us to build a QPU in the first place. In this talk, I will lay the groundwork and thesis for a comprehensive QEDA stack. I will then discuss how Kothar's classical solvers pave a path to modeling hundreds of qubits without sacrificing the "quantumness" of the chip's components. Finally, we will establish a critical roadmap: the transition toward "using quantum computers to design quantum computers.

People

Jonathon Riddell

Kothar

Research Manuscript

CARAMEL: Boosting Device Utilization in Control Flow Auditing

4:06pm - 4:18pm PDT Monday, July 27 Mtg Room 203C

Security

SEC4. Embedded and Cross-Layer Security

DescriptionMicrocontroller Units (MCUs) are widely used in safety-critical systems, making them frequent attack targets. This demands lightweight defenses that remain reliable even after software compromise. Control Flow Auditing (CF-Aud) strengthens Control Flow Attestation by ensuring authenticated control-flow logs (CFLogs) are reliably delivered from a compromised prover (Prv) to a remote verifier (Vrf), enabling assessment of system behavior and support for remediation. However, existing CF-Aud designs rely on a costly busy-wait phase that limits Prv's utilization. In this work, we propose CARAMEL: a hybrid hardware-software root-of-trust architecture that reduces this bottleneck by enabling log transmission without halting execution. Its minimal communication interface and implementation are open-source.

People

Alexandra Lengert

University of Zurich

Adam Caulfield

University of Waterloo

Ivan De Oliveira Nunes

University of Zurich

Engineering Poster

CDG-DNN: Scalable Test Template Generation Using Adaptive Neural Architecture for Industry Class CDG Hardware Verification

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionCoverage-Directed Generation (CDG) is essential for driving verification toward hard-to-hit coverage events, but existing DNN-augmented CDG flows have largely remained at proof-of-concept scale with strong GPU dependence. This work presents a production-grade, design-agnostic DNN-assisted CDG framework deployed on next-generation IBM POWER and Z processor units, scaling from 4 parameters and 320 events to 1,800 parameters and 36,000 events while remaining practical for industrial flows. By exploiting latent clustering in coverage events, hidden-layer width is sized by correlation structure (∼100 clusters) instead of raw event count, delivering a 508× memory reduction (30 GB to 60 MB) and 3.75× CPU training speedup (7.5 h to 2 h), enabling CPU-only deployment without accuracy loss. On a complex production unit, the DNN-guided CDG hits 59 of 74 RIT-critical no-hit events in 10 days—including 4 events missed for 272 days by state-of-the-art regressions—while requiring one template to match and surpass five baseline CDG templates. The same configuration generalizes across units without hyperparameter retuning, demonstrating scalable, transferable CDG acceleration suitable for real tapeout schedules.

People

Research Manuscript

Celestialeye: A Synergistic CPU-FPGA Engine for Accurate Frequency Measurement in High-Speed Data Streams

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionAccurate frequency measurement in high-speed data streams is crucial. While FPGA-based solutions are promising, existing designs often trade off throughput against accuracy due to limited hardware resources. This paper introduces CelestialEye, a CPU-FPGA synergistic architecture that employs a CPU-based heuristic decoding algorithm for high accuracy and offloads high-throughput tasks to the FPGA. Its pipelined hardware integrates hot/cold item separation, advanced compression, and encoding to optimize on-chip SRAM efficiency and bandwidth utilization. Furthermore, the frequency bounds generated by the FPGA process can accelerate the CPU's decoding. Experimental results demonstrate that CelestialEye significantly outperforms the state-of-the-art BitMatcher in both performance and accuracy.

People

Zhongxian Liang

Harbin Institute of Technology

Ying Li

Southern University of Science and Technology

Peng Cheng Laboratory

Harbin Institute of Technology

Research Manuscript

Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm

3:42pm - 3:54pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionStandard-cell-based design has long been the dominant approach in VLSI design, providing scalability and compatibility with established EDA tools. However, as design technology co-optimization (DTCO) becomes increasingly important at advanced process nodes, the fixed structure of standard cells limits the ability to optimize wirelength and area effectively, imposing a critical bottleneck at the Middle-of-Line (MOL) layers. In this context, dense pin access and M0 routing resources, critical for alleviating congestion on higher metal layers, are rigidly constrained by the cell boundary. A more flexible approach is to directly place transistors on the design canvas and perform routing at the transistor level, enabling physical-level optimization beyond the logic-level constraints imposed by standard-cell design. This work introduces a novel framework featuring cell-structure-independent transistor-level placement coupled with an MOL-aware routing engine. Experimental results demonstrate that the proposed framework achieves considerable improvements in wirelength and design area compared to the commercial standard-cell-based design tool and state-of-the-art transistor-level work.

People

Research Manuscript

Celle: Automated Standard Cell Library Extension via Equality Saturation

2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionAutomated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

People

Engineering Poster

Central DMA IP Verification Using Layered UVM Scoreboard

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionWe present a scalable verification strategy for a highly concurrent, partitionable Central DMA (CDMA) IP that supports inter‑execution‑environment transfers, multicast distribution, and native PCIe integration/exposure. The verification challenge spans deep AXI ID usage, unbounded read‑data interleaving, QoS and route‑by‑port attributes, ECC/parity reactions, and heterogeneous bus interfaces (AXI/APB/ACE‑Lite), compounded by system scale (dozens of station interfaces, MSI‑X vectors, and configurable engines/rings). Our solution is a layered, channel‑aware UVM scoreboard that cleanly separates transfer‑intent binding from protocol and data checking. A transactor decodes descriptors to publish transfer intent; the scoreboard binds read IDs (via first read ADDR of source), captures source data, then binds write IDs (via first write address of destination) to perform beat‑accurate data comparisons. Completed transfers sends out to specialized scoreboards—AXI attribute/protocol/bandwidth, writeback, and MSI‑X coalescing/ordering—with a unified completion model. Results show >50% reduction in average debug time, faster coverage closure (especially DMA cross bins), simpler scenario extensibility through reusable checkers, and earlier detection of critical issues; to date, no silicon issues have been observed. This layered approach improves observability, triage clarity, and reuse, accelerating time‑to‑market while lifting verification quality for CDMA variants.

People

Jagadish Rongali

NXP

Engineering Special Session

Challenges and Solutions in the next-Generation Emulation and Prototyping Solutions

3:30pm - 4:00pm PDT Tuesday, July 28 Seaside RM 7

Chiplet

EDA

Systems

DescriptionThis talk will explore the key challenges facing next-generation emulation and prototyping, including scalability, integration with heterogeneous systems, debugging capabilities, and support for emerging application domains such as AI and automotive. The session will then present cutting-edge solutions and best practices that address these hurdles, such as hybrid emulation approaches, cloud-based prototyping, improved hardware/software co-verification techniques, and advanced instrumentation for real-time analysis. Attendees will gain insights into recent technological advancements, practical deployment strategies, and future trends shaping the landscape of emulation and prototyping. This talk is intended for engineers, researchers, and decision-makers seeking to optimize verification flows and accelerate innovation in next-generation systems.

People

Engineering Poster

Channel Width Optimization for IR Drop Reduction in Advanced SoCs

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionPower delivery challenges in advanced System-on-Chip (SoC) designs are increasingly critical due to stringent performance, area, and reliability requirements. Traditional approaches to channel width optimization are performed late in the design cycle, often relying on post-RTL Engineering Change Orders (ECOs). These late-stage modifications are complex, error-prone, and risk project delays, while narrow or sub-optimal interconnects exacerbate IR drop and electromigration (EM) issues, degrading power integrity and yield.

We propose an early-stage methodology that shifts EM/IR analysis and channel width optimization to the early design phase, leveraging preliminary floorplans, power grid data, and pseudo currents derived from historical designs. This proactive approach enables identification of voltage drop and current density hotspots before RTL availability, allowing designers to balance IR drop mitigation against routing resource efficiency. Results from initial implementations demonstrate strong correlation with post-RTL simulations, validating the accuracy of early predictions.

By addressing EM/IR risks upfront, this methodology reduces reliance on late ECOs, improves design robustness, and accelerates turnaround time. Future integration with automated in-design IR-fixing techniques promises further efficiency gains, ensuring reliable power delivery in next-generation SoCs.

People

Research Manuscript

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs

3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionFunctional verification accounts for over 50% of the IC development lifecycle, making SystemVerilog Assertions (SVAs) indispensable for rigorous digital chip verification. However, manual SVA authoring is labor-intensive and error prone. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. The AgentBridge platform facilitates systematic data generation, augmentation, and validation, decomposing complex verification processes into modular, verifiable subtasks. ChatSVA achieves syntax and function pass rates of 98.66% and 96.12%, averaging 139.5 SVAs per design with 82.50% function coverage. A ChatSVA web service is publicly available.

People

Lik Tung Fu

National ASIC Center, School of Integrate Circuits, Southeast University

Jie Zhou

National Center of Technology Innovation for EDA

shaokai ren

mengli zhang

National Center of Technology Innovation for EDA

Jia Xiong