Search Program

3D-ReSAC: A Near-3D-Stacked-DRAM Processor with Area-Efficient Sequential Refresh-Skip and High-Link-Utilization Arrowmesh Communication for Fast Low-Batch LLM Inference

Research Manuscript

10:43am - 10:56am PDT Tuesday, July 28 Mtg Room 203AB

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionLow-batch LLM inference on edge hardware places stringent demands on both memory bandwidth and computational capacity. While 3D-stacked DRAM accelerators offer a promising solution, they introduce two critical overheads that are frequently under-optimized: DRAM refresh and collective communication.
To mitigate these issues, we propose 3D-ReSAC, a near-memory processor based on 3D-stacked DRAM, equipped with an area-efficient sequential refresh-skip method and high-link-utilization ArrowMesh communication.
Our evaluations show that 3D-ReSAC reduces refresh and communication overheads by 7–100% and 53–75%, respectively, leading to a 1.12× to 2.02× latency reduction across low-batch LLM inference workloads.

People

Engineering Poster

3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

Description3DIC chiplet heterogeneous integration faces significant challenges in cross-die timing signoff due to the lack of unified 3D PDKs and the inability of conventional STA to account for jitter from TSV+HB arrays. This paper proposes a 3DEM-driven PDK-independent STA approach for reliable cross-die timing signoff. The approach constructs cross-die channels with die final-stage buffers and cross-die sections, integrating 3D EM modeling for S-parameter acquisition, SPICE simulation for total jitter analysis, R/C parameter back-annotation, and jitter incorporation as uncertainty into STA. A case study on 9-layer stacking (1GHz) shows that the proposed method enables transmission pattern optimization (reducing jitter from 230.74ps to 120.28ps and achieving timing closure), which is unattainable with conventional STA. This work facilitates reliable and flexible 3DIC chiplet heterogeneous integration.

People

Mingyang Liu

Hangzhou Zhicun (Witmem) Technology

Yi Chen

Zhang Jie

Hangzhou Zhicun (Witmem) Technology

Chunming Wang

Witintech

Yue Heng

Beijing Zhicun (Witmem) Technology Co., Ltd

yu tian

Research Manuscript

A Boolean Processor-Based Hardware Emulation System with Reconfigurable Interconnects

4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionExisting Boolean processor-based (BP-based) hardware emulation systems typically rely on fixed interconnects, which often suffer from severe bandwidth underutilization under highly imbalanced traffic. We propose a BP-based hardware emulation system with hierarchical reconfigurable interconnects. At both the inter-chip and intra-chip levels, our system dynamically reallocates idle interconnect lanes from low-traffic pairs to high-demand pairs, alleviating communication bottlenecks and improving interconnect utilization without modifying the underlying ASIC fabric. The hardware is co-designed with the compiler, which profiles communication, generates per-lane configuration tables and scheduling strategies, and programs the interconnect via registers. Experimental results on industrial digital designs show up to 64% emulation performance improvement and an average 27% reduction in compilation time, with only 7.4% area overhead compared to a fixed-interconnect baseline system.

People

Engineering Poster

A Chip-Level DTCO Framework for Yield-Aware Back-End Design: Layout-Aware Misalignment Correction in DRAM

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionWe propose a chip-level, layout-aware DTCO framework to correct deterministic interlayer misalignment. Using layout-driven features and machine learning, the proposed approach achieves ~70% variation reduction, enables fast inline prediction, and improves yield on silicon-proven products.

People

HyeJin Kim

Samsung Electronics

SoYoung Kim

Sungkyunkwan University

Engineering Poster

A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAutomotive radar systems rely on highly linear FMCW chirp signals to ensure accurate distance and velocity measurements for ADAS applications. Deviations in chirp linearity can compromise radar performance and violate functional safety standards. This paper presents a compact, all-digital IP for real-time chirp linearity monitoring integrated within the radar transmitter subsystem. The proposed solution leverages zero-crossing alignment between the chirp signal and an on-chip reference clock to compute instantaneous frequency slope deviations without requiring dedicated high-frequency clocks. The architecture includes counters, edge overlap detection, and an error computation engine, demonstrates detection of minor deviations as low as 0.001% across a 10 μs chirp duration. Implemented entirely in digital logic, the IP is technology-independent, incurs less than 5% area overhead, and operates with any available on-chip clock source. This scalable, low-cost solution enhances radar transmitter reliability and supports compliance with automotive safety standards, making it ideal for integration into next-generation radar SoCs.

People

Research Manuscript

A Correlation-Aware GKP Decoder for Fault-Tolerant Continuous-Variable Photonic Quantum Computers

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 203AB

Design

Quantum

DES6. Quantum Computing

DescriptionThe Gottesman–Kitaev–Preskill (GKP) encoding is a promising approach for realizing fault-tolerant continuous-variable (CV) photonic quantum computers.
Recent studies have investigated various GKP decoding algorithms, among which correlation-aware methods that exploit inter-qubit correlations achieve significantly improved error-correction performance.
However, hardware implementation of GKP decoding remains largely unexplored.
Error decoding in CV photonic quantum computers must operate within tens of nanoseconds to match the optical clock frequency.
A straightforward hardware implementation of correlation-aware decoding introduces substantial computational latency due to its arithmetic complexity.
To address this challenge, this paper proposes a high-accuracy and low-latency accelerator architecture optimized for correlation-aware GKP decoding.
Logic synthesis using 7-nm FinFET technology demonstrates that our decoder can complete correlation-aware GKP decoding with in 12.96 ns.
In addition, comprehensive design space exploration is conducted to evaluate tradeoffs among decoding accuracy, latency, and circuit area, leading to design guidelines for future correlation-aware GKP decoder implementations.

People

Ryosuke Matsuo

The University of Tokyo

Junichiro Kadomoto

The University of Tokyo

Research Manuscript

A Differentiable Approach to Task Graph Partitioning: A Case Study in RTL Simulation

5:18pm - 5:30pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionGraph partitioning is essential for many EDA applications that leverage task graph parallelism for faster execution. For instance, RTL simulators partition an input RTL design into dependent tasks and schedule them across threads. However, existing partitioners are largely limited to general-purpose heuristics that overlook real threading costs, resulting in suboptimal performance. Consequently, we introduce DiffPart, a differentiable task graph partitioning framework that automatically learns high-quality partitions under real operating conditions. Applied to RTL simulation, DiffPart improves state-of-the-art Verilator's partitioning quality, delivering up to 1.22--55.25x faster simulation runtime across diverse designs.

People

Aditya Das Sarma

Wan Luan Lee

Shui Jiang

University of Wisconsin, Madison

Boyang Zhang

Tsung-Wei Huang

A Distributed and Scalable Dynamic Power Integrity Flow from Early Analysis to Sign-off for Large-Scale Serdes Designs

Engineering Presentation

11:15am - 11:30am PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionFor large-scale SerDes designs, dynamic power integrity sign-off is becoming increasingly challenging due to growing design scale and performance demands. Modern SerDes integrate analog blocks, digital blocks, sensitive clocks, decaps with complex Power Delivery Network (PDN) design. Such designs can reach tens of millions of transistors and multi-million-node as design nodes shrinking, making full-chip dynamic EMIR sign-off and Chip Power Model (CPM) generation difficult. In addition, data rates are scaling from 56G to 112G and 224G, leading to higher switching activity and larger transient current peaks. Accurate sign-off and CPM generation require smaller, picosecond-level time resolution and long transient windows of up to hundreds of nanoseconds, making sign-off runtime even longer.
In traditional power integrity analysis, existing EMIR tools have limited distributed scalability for full-chip, multi-domain SerDes designs. Realistic dynamic simulations often exhibit low parallel efficiency and inefficient utilization of computing resources, resulting in long runtime to days or even weeks. To reduce runtime and resource usage, designers have to downsize current vector capture window or simplify extracted networks, which impacts overall power integrity analysis accuracy. Moreover, past early analysis is typically limited to simple static analysis, while dynamic analysis and CPM generation can only be performed at the sign-off stage, making chip-package-system PDN co-optimization hard to process in early stage.
Here, we adopt a distributed and scalable dynamic power integrity flow from early analysis to sign-off. Early-stage dynamic power integrity analysis based on Build Quality Metric (BQM) provides early EMIR insight and enables early CPM generation for package- and system-level power integrity analysis, allowing issues to be addressed earlier and reducing sign-off iterations. Distributed and scalable dynamic EMIR sign-off flow enables efficient full-chip analysis under realistic workloads through multi-machine, multi-thread parallelism, without simplifying extracted networks or reducing analysis windows. With the unified dynamic power integrity flow from early analysis to sign-off, analysis efficiency is significantly improved while maintaining accuracy and increasing confidence in SerDes design robustness.
keywords：large-scale Serdes designs, distributed and scalable, dynamic power integrity, Chip Power Model

People

Xin Shu

Jinrong Yan

Hang Sun

Xuewei Ding

Xiaofan Lu

A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis

Work in Progress

6:55pm - 6:56pm PDT Monday, July 27 Exhibit Hall

DescriptionClock meshes are an essential technique in high-performance VLSI systems to minimize skew and handle On-Chip Variation (OCV) especially in nanometer technologies. However, analyzing meshes is difficult due to reconvergent paths and multi-source drivers. The industrial standard is to use SPICE simulations since static timing analysis (STA) tools can not handle mesh loops. SPICE simulations are accurate but slow, and approximate models miss critical effects like input slew and input skew. In this work, we propose a Graph Neural Network surrogate model of the clock mesh represented as a graph with augmented structural and physical features. Trained on SPICE data, our model achieves high accuracy with average delay error of 1.70ps on unseen real designs versus 87.30ps from prior approximate models, while achieving speed-ups up to 3900x over multi-threaded SPICE simulation enabling faster and accurate analysis for clock meshes. Furthermore, we demonstrate the adaptability of our model through transfer learning and use it for OCV analysis.

People

Muhammad Hadir Khan

Matthew Guthaus

A Fully Analog Continuous-Time CIM Neural ODE Solver for Flow-Matching-Based Fluid Dynamics Generation

Research Manuscript

10:30am - 10:45am PDT Wednesday, July 29 Mtg Room 203AB

Design

DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionThe generation of fluid-dynamics fields is essential for understanding complex nonlinear systems and enabling real-time scientific computing. Conventional computational fluid dynamics pipelines rely on finite-element or finite-volume solvers on von Neumann architectures, which discretize continuous physical evolution into many iterative updates, leading to prohibitive latency and energy consumption. Inspired by neural dynamical systems in the brain, we propose a biologically inspired continuous-time hardware–software co-design framework for flow-matching–based turbulent-flow generation. (1) The flow-matching model adopts an MLP-Mixer architecture that emulates cortical-style information integration and hierarchical signal mixing, providing a compact backbone that naturally aligns with closed-loop analog computation. (2) A fully analog continuous-time RRAM CIM neural ordinary differential equation (ODE) solver is developed to physically realize neural-like continuous-time latent dynamics, enabling high-speed and low-power flow generation. (3) Noise-aware training and decoder retraining are jointly introduced to ensure robust generation quality in the presence of RRAM read/write noise. Experiments on three turbulent-flow datasets show that the MLP-Mixer backbone matches convolutional and attention-based flow-matching models in velocity-field accuracy while mapping efficiently to CIM hardware, and that the proposed analog ODE solver reduces energy consumption by 98.24% and latency by 99.99% compared with an NVIDIA A100 GPU, while maintaining stable generation fidelity under realistic RRAM read/write noise. This work establishes a new paradigm for high-speed, energy-efficient physical process generation and scientific AI acceleration using neuromorphic continuous-time CIM computing.

People

Songqi Wang

The university of Hong Kong

Meng Xu

Jichang Yang

Zhexu Chen

Hegan Chen

The university of Hong Kong

Sishuo Liu

Xinyuan Zhang

Kwun Hang WONG

Ning Lin

Yi Li

Zhongrui Wang

Han Wang

A Hamiltonian-Guided Pre-Trainer for Variational Quantum Algorithms

Research Manuscript

2:34pm - 2:47pm PDT Wednesday, July 29 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionThe optimization of variational quantum algorithms (VQAs) is notoriously challenging due to poor parameter initialization, which often traps optimizers in suboptimal local minima. Existing methods rely on a static guessing paradigm that is fundamentally limited. This paper presents a Hamiltonian-guided pre-trainer (HGP), a new approach that dynamically constructs a better starting point. HGP iteratively refines parameters by performing exact global optimization within low-dimensional subspaces. These subspaces are identified using a Hamiltonian-guided parameter blocking strategy, and the optimization is achieved by reconstructing the analytic landscape from a few quantum measurements via a Fast Fourier Transform. We evaluated HGP on canonical spin models, where it consistently produced superior starting points for standard optimizers. Ablation studies reveal Hamiltonian-guided parameter blocking reduces the initial energy error by nearly 30-fold versus the next best benchmark. These results highlight the importance of Hamiltonian guided pre-training for enhancing VQA performance.

People

Engineering Presentation

A Hierarchical and Scalable Power Supply Network (PSN) Analysis Framework for FCBGA Packages in High-Power AI Applications

4:00pm - 4:15pm PDT Monday, July 27 Seaside Ballroom A

EDA

Systems

DescriptionAs AI, machine learning, and cloud workloads scale, interconnects must deliver higher bandwidth and lower latency without compromising system-level power integrity and PDN robustness. Massive parallel compute leads to high transient current demand, fast di/dt switching, and increased simultaneous switching noise, causing traditional PDN assumptions to break down at the system level.

A scalable system-level PI simulation flow is key to balancing accuracy and turnaround time for large, high-performance product designs under aggressive go-to-market timelines. This work presents a virtual validation framework for system-level power integrity sign-off analysis, including die, package, and PCB. It enables engineers to identify anomalously high impedance responses in the system; excessive transient voltage drops and elevated current ripples at each interface (per bump) of the system.
This approach helps to correct the design before tape-out, helping to avoid costly redesign cycles and potential product failures.

People

Engineering Poster

A Hybrid Simulation and Formal Verification Approach for Exhaustive Interrupt and Status Flag Verification

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionVerification of status flags and interrupts is critical for correct interaction between IP components, yet exhaustive validation of interrupt behavior remains challenging when relying solely on simulation-based approaches. This approach presents a hybrid simulation and formal verification methodology for interrupt and status flag verification using an interrupt Verification IP (VIP) and demonstrates its application on a Real-Time Clock (RTC) IP. Simulation-based verification is used to validate interrupt behavior under realistic programming scenarios, while formal verification is leveraged to exhaustively prove interrupt properties and corner cases that are difficult to cover in simulation. The results highlight the effectiveness of combining dynamic and formal verification through a reusable interrupt verification infrastructure to improve confidence in interrupt correctness at the IP level.

People

Engineering Poster Gladiator

A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs

5:52pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionPower consumption plays a key factor in SoC. With advances made in wireless technologies through 3GPP LTE & NR, IEEE Wifi and now with 3GPP 6G, there is a need for advanced architecture in SoC. Typically, a SoC uses sleep and wakeup (warmboot) procedure for saving battery. The warmboot procedure involves changing DRAM from refresh mode to active mode. This takes certain time until which other operations get delayed. Also usage of DRAM further consumes power. Hence, hardware design that enables software to have systematic control on wakeup (warmboot) and sleep operations is required. This idea discusses on design of SoC to use hybrid mode of SRAM and DRAM. SRAM and DRAM are memory entities which play a key role in wakeup, software execution and sleep. With combination of software control on proposed hardware design for system-on-chip, can efficiently increase sleep time by minimizing DRAM usage and wakeup time by managing with SRAM along with faster execution of procedures required during wakeup.

People

Venkata Raju Indukuri

Research Manuscript

A Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation

2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionAs integrated circuit (IC) designs grow increasingly complex and transistor counts per chip exceed ten billion, post-layout SPICE simulations involve large-scale sparse linear systems, severely degrading simulation efficiency
Current GPU acceleration methods, despite their promise, struggle with efficient load balancing and resource utilization, which restricts their effectiveness in ultra-large-scale circuit simulations.
In this paper, we propose a levelized load-balanced and structure-adaptive LU factorization framework for GPU-based circuit simulation.
Our method improves resource utilization and parallel efficiency by introducing computation-balanced dependency level partitioning, adaptive resource allocation, and a hybrid matrix indexing mechanism.
These strategies ensure that both the memory and computational resources of the GPU are fully leveraged.
We demonstrate significant acceleration over existing methods, achieving a 2.1X speedup compared to GLU3.0 and a 5.2X speedup over 16-thread PARDISO on circuit sparse matrices ranging from thousands to millions of dimensions.
Additionally, our framework has been successfully integrated into the open-source SPICE simulator Ngspice, accelerating circuit simulations with promising results and showcasing its potential for large-scale IC design verification.

People

A Locality-Aware Temporal Motif Mining Accelerator with Chunk-Based Search Tree Expansion

Research Manuscript

1:55pm - 2:08pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES3. Emerging Models of Computation

DescriptionMining temporal motifs in temporal graphs is essential for many critical applications. Despite several software/hardware temporal motif mining solutions have been proposed, they still suffer from substantial redundant and irregular off-chip communications due to misaligned search tree expansions across different motif matching tasks. In this work, we observe that different tasks traverse the same temporal graph edges in strict chronological order, exhibiting strong data locality among these tasks. Motivated by this insight, we propose LTMiner, a locality-aware hardware accelerator designed to efficiently handle temporal motif mining. Specifically, LTMiner proposes a novel chunk-based search tree expansion mechanism into the accelerator design to align the graph traversals of different tasks at the granularity of data chunks, substantially boosting the data locality among these tasks for lower data access cost. The results show that LTMiner gains 1.1×–652.6×, 1.8×–70.3× speedups and 3.9×–2050.9×, 1.2×–17.3× energy savings compared to the cutting-edge software and hardware solutions, respectively.

People

Yinbo Hou

Hao Qi

Jin Zhao

Yu Zhang

Yiling Lu

Hong Kong University of Science and Technology (HKUST)

Hui Yu

longlong lin

Southwest University

Wenbin Jiang

A Method to Automate the Conversion of .def File into .save.io One to Speed up the BE Digital Flow in Analog-on-Top Designs

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIn analog-on-top design flows, ensuring pin position and ordering constraints from the analog layout team is critical for the Place & Route of digital IP blocks. Traditionally, digital layout engineers manually convert DEF files, which describe physical layout and pin information, into .save.io files required by Innovus. This manual editing is time-consuming, error-prone, and must be repeated frequently due to evolving constraints. We present "IO Generator," a Python-based tool that automates the conversion of DEF files into the .save.io format, significantly accelerating the backend digital flow. The tool accurately assigns pins to floorplan sides and computes offsets and skips based on LEF-defined pitch and width parameters. It includes robust error checking to ensure pin alignment and offers two modes: pin extraction for file generation and pin comparison for mismatch reporting between DEF and netlist files. With a user-friendly GUI and command-line interface, IO Generator reduces manual effort from hours to seconds, minimizes errors, and integrates seamlessly into existing flows. IO Generator has been successfully adopted across multiple projects, proving its effectiveness and versatility in modern analog-on-top digital design flows.

People

Luca Francesco Perroni

Michele Battista

A Mixed-Domain Modeling Approach for Hatched Ground Planes in 3D Chiplet Die-to-Die Interconnect

Engineering Presentation

11:00am - 11:15am PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionThe rapid growth of AI and machine-learning workloads has driven adoption of advanced packaging technologies such as silicon interposers, bridges, and heterogeneous 3D integration in chiplet-based systems. These structures often require patterned ground planes, such as hatched or meshed geometries, to meet manufacturability and reliability constraints. However, these geometries introduce significant challenges for signal and power integrity analysis due to impedance variation, increased loss, resonances, and crosstalk.
This paper presents a practical mixed-domain interconnect modeling approach that combines specialized quasi-static 2D field solvers with full-wave Finite Element Method (FEM) solvers to efficiently analyze hatched ground planes in advanced interconnects. The proposed approach is designed to integrate into back-end interconnect simulation flows, balancing modeling accuracy with scalability suitable for design iteration and signoff.
Two test vehicles, a UCIe 2.0–based silicon bridge and a mobile flex PCB, are fabricated, simulated, and correlated against measured data. The results demonstrate strong agreement with measurements while improving modeling efficiency compared to standalone 3D EM analysis, enabling more reliable interconnect analysis and faster design turnaround for advanced packaging implementations.

People

Dr. Tim Wang Lee

HeeSoo Lee

A Novel Automated Methodology Python Driven for Test Coverage Improvement via Fault Injection and Simulation

Orlando Bell

Giga Design Automation

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe increasing complexity of digital circuits and stringent functional safety standards, such as ISO 26262 and IEC 61508, require test coverage levels above 99%, which often leads to significant area overhead due to traditional Design For Testability (DFT) techniques. This work presents a novel automated methodology, driven by a Python script, that combines ATPG patterns generated by TestMAX ATPG with functional fault simulation run using VC_Z01X to significantly improve test coverage without additional area overhead. The methodology was validated on a STMicroelectronics' synchronous step-down regulator, showing coverage improvements from 78.87% to 92.90% in full-scan configuration and from 42.09% to 84.25% in partial-scan mode, while drastically reducing ATPG untestable faults. The automated flow leverages the existing functional testbench, enhancing verification efficiency and repeatability. This approach advances the trade-off between achieving high test coverage and minimizing area impact, offering valuable benefits for safety-critical applications and designs with strict area constraints.

People

Mario Blangiforti

Luca Francesco Perroni

Luca Pulvirenti

A Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive Applications

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionWith the ongoing advancement of automotive intelligence, vehicles are incorporating an increasing number of semiconductor chips to improve efficiency and functionality. This technological progression results in elevated current levels across automotive systems, leading to two key physical challenges: electromagnetic compatibility (EMC) and thermal management. Properly managing these factors is crucial for ensuring system stability and reliability.

However, simultaneously addressing EMC and thermal effects is complex, as their respective physical impacts and design requirements are often conflicting. This complexity extends the design cycle needed to achieve a suitable balance between EMC and thermal considerations that meets chip specifications. To address this challenge, Denso and Siemens EDA have partnered to develop an automated optimization workflow by integrating Siemens' Solido Simulation Suite, HEEDS, and FLOEFD. This approach efficiently determines optimal design solutions for both EMC and thermal performance.

Utilizing this innovative workflow can reduce design timelines by up to 68% and decrease physical area requirements by as much as 20%. These improvements significantly accelerate time-to-market and lower costs associated with circuit design for automotive applications.

People

Engineering Poster

A Novel Methodology for Automated LVS Rule Deck Verification: Truth Table and Device Extraction Qualification

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern semiconductor fabrication faces an escalating verification challenge as technology nodes shrink to 3nm and beyond, where Layout Versus Schematic (LVS) verification complexity has grown exponentially. Today's LVS must go beyond comparing Schematic and Layout designs; it must extract R/C values for hundreds of devices, perform parasitic extraction (PEX), and analyze complex CAD layer interactions. At 3nm nodes, device extraction requires 30 to 50 CAD layers per device due to Mask Data Preparation (MDP) demands, making manual verification infeasible. This paper presents a novel automated Device Extraction Quality Assurance (QA) framework integrating three verification engines: Truth Table Checker, Compare Checker, and Device Extraction QA. The workflow ensures device extraction is properly performed as described by process development, extracting layouts from seed layers and supplying devices to SPICE netlists for simulation-based verification. Validated across technologies from 8-12 inch legacy processes to 3nm nodes, the framework enables early detection of truth table errors and parasitic device extraction issues through automated parameter qualification. The truth table checker flow has dramatically reduced turn-around time to rule deck release while significantly improving quality. With average runtimes under 30 minutes, qualification engineers receive comprehensive reports clearly indicating where attention is needed, enabling rapid issue resolution and high-confidence PDK releases.

People

Work in Progress

A Novel Way to Handle Non-Convergence of Properties in Formal Verification of Digital Systems

5:28pm - 5:29pm PDT Monday, July 27 Exhibit Hall

DescriptionThe increasing complexity of modern digital designs presents significant challenges for formal verification, particularly when properties fail to converge within practical proof bounds. Non-convergent assertions hinder verification sign-off and limit the ability to expose deep corner-case bugs. This work proposes a contract-based refinement framework to enhance property convergence in the formal verification of complex hardware systems. The methodology employs proof decomposition to identify refinement properties—helper assertions selected through overlapping cones of influence (COI)—which are then composed to strengthen the convergence of the target property. Implemented and evaluated using the Cadence JasperGold formal verification platform, the approach demonstrates improved proof bounds and enhanced bug detection across multiple architectures, including memory controllers and CPUs. Results show that the proposed technique systematically improves convergence for critical properties while maintaining scalability and broad applicability to diverse digital designs.

People

Research Manuscript

A Physics-Prior Intelligent Compact Modeling Framework for BEOL-Compatible DTCO: EKAN-Based Distillation from Neural to Symbolic Models

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionNeural compact models are increasingly explored for design–technology co-optimization (DTCO), yet their black-box nature hinders physical interpretability and seamless SPICE deployment. We introduce a physics-prior neural-to-symbolic compact modeling framework based on Efficient Kolmogorov–Arnold Networks (EKAN) trained on multidimensional oxide-FET data. EKAN first learns a smooth, bias-aware log-current surrogate; its spline activations are then distilled into a closed-form current expression via KAN-derived one-dimensional atoms, physics-guided feature libraries, and weighted sparse regression with monotonicity regularization. The resulting Verilog-A model is SPICE-ready, preserves key device trends across bias and process, and attains accuracy comparable to neural compact models while remaining interpretable.

People

Xufan Li

Yi Li

Ning Lin

Institute of Microelectronics, Chinese Academy of Sciences

Xiaoyi Zhang

Yue Zhao

Institute of Microelectronics, Chinese Academy of Sciences

Jiaye Shen

Institute of Microelectronics, Chinese Academy of Sciences

xiaojuan qi

University of Hong Kong

Zhongrui Wang

Han Wang

University of Hong Kong

Zhenjie Yao

The Institute of Microelectronics of the Chinese Academy of Sciences

Lingfei Wang

ling li

CAS

Ming Liu

A Probe-Based Time-Domain Methodology for Dynamic Thermal Management in Stacked-Die Architectures

Engineering Presentation

11:30am - 11:45am PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionDynamic Thermal Management (DTM) techniques are increasingly critical for high-power heterogeneous chip designs, where sustained peak operation can lead to rapid thermal limit violations. We present a dynamic, probe-based thermal methodology to quantitatively evaluate settling time post peak power events and maximize peak state duration. Design comprises of a compute die along with HBM placed on interposer and then package. Distinct tile based power map was created for peak and lower activity (50-90%) states. Static thermal analysis was performed to find the corresponding maximum temperatures.
Next using DTM analysis, the settling time was extracted, which is required for each lower power state to reach steady-state temperature after exiting the peak. This was exponentially inverse to power. Lastly, peak state duration between certain thresholds was maximized depending on the settling time of each state. Maximum peak state duration of 80% and 76% were seen for peak to 50% and 60% power states respectively. This methodology enables evaluation of transient metrics using DTM analysis by linking power throttling decisions directly to time-domain thermal behavior, providing actionable insights for DVFS, workload scheduling, and safe peak performance budgeting.

People

Sumanth Suraneni

Annapurna Labs US Inc.

Nikhil Jayakumar

Amazon

Sujyesh Aanandh Manjunthan

A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control

Engineering Presentation

10:30am - 10:45am PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionThis work presents an automated EDA toolchain for synthesizing programmable and scalable CMOS analog optimization IP cores. Addressing the latency wall in real-time control, where conventional digital solvers face polynomial scaling bottlenecks, our methodology translates high-level mathematical specifications (AMPL/MPS) directly into verification-ready SPICE netlists. The synthesized IP utilizes a reconfigurable switched-capacitor architecture that implements continuous-time Karush-Kuhn-Tucker dynamics, allowing it to solve constrained optimization problems through parallel physics-based evolution rather than sequential algorithms.Unlike prior art limited to small-scale fixed-function circuits, our architecture incorporates a software-driven calibration layer to neutralize PVT variations, ensuring reliability in standard CMOS nodes. We demonstrate the flow's scalability on problem sizes ranging from dense 500-variable instances to sparse 10,000-variable workloads. Results show the generated IP achieves invariant sub-millisecond convergence regardless of complexity, delivering a >300X speedup over state-of-the-art digital interior-point solvers while maintaining solution accuracy within 0.02% relative error. This work provides a complete code-to-silicon path for deploying high-performance analog computing in edge AI and real-time control systems.

People

Cal Poly, San Luis Obispo

Research Special Session

A Quantitative Approach to Exploring Novel Image Sensor Architectures Towards Autonomous Edge Machine Vision

4:30pm - 5:00pm PDT Tuesday, July 28 Mtg Room 201A

Systems

DescriptionAutonomous edge machine vision requires image sensor architectures that simultaneously advance inference autonomy and energy autonomy. This paper introduces a quantitative modeling framework that spans conventional CMOS imagers and emerging designs—event-based/DVS sensors, coded-exposure sensors, and self-powered sensors with energy-harvesting pixels. We unify optical, circuit, and algorithmic modeling in a single analytical flow to capture how architectural choices in pixel structures, readout pipelines, compressive acquisition, and hybrid imaging–harvesting mechanisms propagate to power, latency, noise, and task-level vision performance. Extending first-principles models of self-powered vision systems, the framework also evaluates when energy-harvesting pixels provide system-level advantages over external solar harvesting, particularly in long-lived and hard-to-maintain deployments. By enabling rapid, physically grounded exploration and comparative analyses, our results reveal key trade-offs that determine when unconventional sensor architectures meaningfully enhance edge intelligence. This framework offers a principled foundation for designing next-generation energy-aware, autonomous machine vision systems.

People

Xuan Zhang

Northeastern University

Engineering Poster

A Real-Time Metric‑Driven Scorecard for Quantifying and Benchmarking Physical‑Design Quality and Deployment Progress

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionProblem Statement & Motivation

• This paper presents an automated scorecard analysis system designed to systematically evaluate and track design quality metrics throughout the development cycle.
• The system provides quantifiable insights into design using a weighted categorical scoring approach, highlighting optimization opportunities and flow gaps, enabling project teams to make informed decisions based on severity-categorized metrics.
• This Scorecard tracker application is designed to manage and display the scores of various physical design runs to ensure design quality through a structured checklist-based scoring process. This tool presents designers with categorized information to enable pin-pointed evaluation to improve quality while reducing manual efforts, leading to improved turnaround time for design closure.
• The tool offers various features such as quality assessment of flow logs, quality checks on run environment, highlighting missed checks and ensuring each manual checks is run and cleaned up. This is done along with binning checks into different categories to help designers prioritize debugs.
• The system allows users to monitor their runs efficiently. It is built with a focus on usability and monitoring various flow of physical design (Synthesis, PnR, reliability, CV, custom flows) which are used for the development of SOC.
• Results demonstrate improved prediction of design quality issues and more effective allocation of engineering resources, leading to measurable reductions in design iterations and validation time while maintaining high quality during implementation.
• Additionally, all the scores for each run, project and block are logged centrally which helps in analyzing trends of design closure during and after implementation of design. This can be an effective tool to collate learning during implementation and improving design cycle for up-coming designs.

People

Research Manuscript

A Remote Side-Channel Attack on Post-Quantum Key Encapsulation Mechanisms: A Case Study of ML-KEM on Intel x86

3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionAs post-quantum cryptographic (PQC) schemes are standardized, evaluating their resilience to side-channel attacks (SCA) becomes critical. While most prior studies focus on physical SCAs, the practicality of remote SCAs on full implementations of standardized PQCs remains largely unexplored. In this paper, we present the first generic remote power SCA on the Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM), evaluated on a modern Intel x86 processor. Our result demonstrates that power traces can be exploited remotely as a plaintext-checking oracle, enabling secret key recovery despite the scheme's theoretical IND-CCA security. Using ML-KEM as a case study, we show that complex microarchitectural mechanisms such as speculative execution and dynamic power management do not eliminate exploitable power leakage. We evaluated our attack on the PQClean implementation, achieving secret key recovery with a success rate up to 99.5%. These findings provide a realistic assessment of PQC leakage behavior on high-end processors and underscore the need for architecture-aware leakage models and co-designed hardware–software defenses to ensure secure PQC deployment in practice.

People

Mona Hashemi

Temasek Laboratories, Nanyang Technological University

Trevor E. Carlson

A Rule-Aware Layout Conversion Framework for Back-End Physical Design

Engineering Presentation

1:45pm - 2:00pm PDT Wednesday, July 29 Seaside RM 7

EDA

DescriptionAs technology nodes continue to scale, DTCO (Design-Technology Co-Optimization) increasingly requires layout teams to evaluate multiple architectural options early in the design cycle—especially in standard cells and SRAM periphery, where small structural changes can significantly affect area, performance, and DRC results.
In reality, layout implementation has not kept pace with this demand. Even modest architectural updates often invalidate existing layouts, forcing engineers to repeatedly rework structurally similar designs and slowing down DTCO feedback loops.

This work presents a lightweight, rule-aware layout conversion framework aimed at reducing repetitive layout modification effort at the cell- and library-level. Rather than introducing a new design flow, the framework focuses on automating common but time-consuming tasks such as cell-height migration, layout template regeneration, and structural refactoring under updated design rules. Each transformation step is performed in a DRC-conscious manner, helping preserve layout intent and physical consistency.

Experimental evaluations on standard cell and memory-related layouts demonstrate significant reductions in layout turnaround time while maintaining area efficiency and rule compliance comparable to hand-crafted designs. The framework integrates smoothly into existing back-end environments with minimal disruption, making it practical for everyday use.
In the longer term, this structured approach also establishes a solid foundation for future AI-assisted layout automation grounded in real layout expertise and reusable transformation logic.

People

Jaeeun Kim

Samsung

Juhyun Kang

Hyunchul Hwang

Samsung Electronics

Gwanghoon Yun

WoongSik Jung

A Scalable Timing Analysis and Closure Methodology for Ultra-Large Designs

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionUltra‑large digital designs at advanced technology nodes now include billions of instances, deep hierarchies, and highly complex clocking and interconnect structures, making traditional flat static timing analysis (STA) increasingly impractical. Timing closure cycles have become prohibitively long due to excessive runtime, memory demands, and limited visibility across block boundaries. This work presents a scalable and silicon‑correlated timing analysis and closure methodology tailored for these massive designs. The approach unifies Boundary Model, Context‑Aware Timing, and Advanced Multi‑Input Switching (AMIS) to deliver accurate hierarchical timing without requiring design flattening. Boundary Model preserves interface logic by abstracting internal logic in order to reduce design size, while Context‑Aware Timing ensures that each block's interface timing remains aligned with top‑level requirements, regardless of differences introduced by independently developed constraints. AMIS effectively addresses inherent optimism in single‑input switching by capturing simultaneous switching effects. Combined with Tempus ECO and Certus, the methodology enables fast, localized optimization and predictable convergence. Applied to a multi‑billion‑instance design across 150+ timing views, the flow demonstrates 3.5×–5× runtime improvement, 50–65% memory reduction, and strong correlation with flat STA. This scalable methodology provides a robust foundation for achieving efficient timing closure in emerging high‑performance systems.

People

Avinash Sekar

Qualcomm

ABUBAKAR SIDDIK KANCHARA

Qualcomm

Arvind NV

Daksh Bakshi

Harivenkadesh Mohanraj

Himanshu Tanwar

Chaya N

Harish G

A Security-Centric Virtual Platform for Accelerating Shift-Left Security Firmware Development

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs the architectural complexity of SSD controllers increases, the demand for "Shift-Left" in security firmware (FW) development has become a critical necessity. Conventional firmware development heavily relies on hardware prototypes or FPGA environments, which often suffer from limited debuggability and late-stage availability, particularly for "hardware-enforced" security features.

People

Engineering Presentation

A Service-Aware Energy-Efficient DVFS Framework for System-on-Chip Architectures

4:45pm - 5:00pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionModern Dual‑SIM‑Dual‑Standby (DSDS) designs must synchronize signaling, paging, and bearer scheduling to avoid QoS loss caused by radio conflicts, SIM‑switch delays, or RF‑resource contention creating challenges for preserving quality‑of‑service (QoS) across simultaneous networks. Dynamic Voltage and Frequency Scaling (DVFS) is a widely adopted power‑management technique in today's processors and system‑on‑chip (SoC) architectures. By dynamically adjusting supply voltage and clock frequency in response to real‑time workload demands, DVFS cuts both dynamic and static power while still meeting performance targets. In dual‑SIM devices that share radio resources between two protocol stacks, activity on one stack can induce a "blackout" on the other, leading to data inactivity and QoS degradation. The blackout duration is directly governed by the DVFS settings applied to the processor and bus while the opposite stack is executing its tasks. Existing state‑of‑the‑art methods focus on monolithic workloads, thermal‑throttling avoidance, or overall energy minimization, and they ignore the inter‑stack blackout overhead that is unique to dual‑SIM phones. This paper proposes a service‑energy based, intelligent DVFS framework that jointly optimizes the DVFS levels for both stacks by minimizing a weighted sum of throughput loss and total energy consumption. Simulation results show that the algorithm achieves a smooth, monotonic trade‑off, allowing a seamless shift between reduced blackout time and lower energy use.

People

Engineering Poster

A Simple and Predictable Solution for Early Full-Chip LVS Convergence

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionFor Large designs with multiple levels of hierarchies, predicting LVS convergence is very challenging if there are power and ground shorts and opens especially across hierarchies, as its debug could be time consuming and iterative. Also, it is difficult to identify all integration issues at next hierarchy level if any partition is LVS dirty. There are inherent disadvantages in traditional techniques such as black box LVS and destructive cleanup approach that can enable hierarchical level LVS run. To overcome these shortcomings, a simple and efficient solution which can be implemented at any stage of the partition's APR flow from floorplan to route, is described. In this solution critical interface details like Power-Ground network, global clock and signal routes which are pushed down to partitions, hard macros and partition ports are retained and are made LVS clean using this automated flow. This solution was wildly used for many partitions to identify and fix LVS issues accurately early on in multiple projects and enabled timely SoC tape-outs. This solution enabled seamless integration of late-coming partitions, as all the risks with integration were identified and fixed upfront.

People

Kumaresan Vallinayagam

Vishnu Chandrakar

A Soft-Microcode Engine to Power the Next Wave of Edge Intelligence

Engineering Presentation

3:30pm - 3:45pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionThis paper presents a CISC processor architecture designed for modern CMOS technology, featuring a compact and flexible datapath capable of operating efficiently on arbitrary data formats. The architecture supports high-level languages as well as graphics, signal processing, memory, and I/O workloads within a unified execution model.

The processor has evolved over several decades, from a TTL-based minicomputer to multiple generations of CMOS microprocessors implemented in different fabrication nodes. It has been deployed in a wide range of commercial applications worldwide. A recent dual-core implementation has been silicon-verified in 65 nm technology, and a corresponding 22 nm design has been functionally validated on FPGA.

Measured results demonstrate high energy efficiency, strong code density, and extensive support for specialized processing and peripheral control. Because much of the system functionality is implemented in writable microcode rather than fixed hardware, the architecture is well suited as a control processor in universal SoCs targeting mid-volume IoT/OT devices, where custom SoC development is impractical.

The core can also function as a processing element in AI accelerators, with microcode distributed across clustered PEs to implement individual DNN layers.

People

Stefan Blixt

Telesis Innovation

Engineering Special Session

A Unified Agentic Architecture for Rapid Deployment of Zero-Hallucination GenAI Applications

3:30pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionCorvicAI introduces an Intelligence Composition Platform designed to free enterprises from the complexity and rigidity of traditional AI data pipelines. Modern organizations struggle with fragmented tooling, extensive plumbing, and specialized expertise requirements across ingestion, parsing, feature engineering, retrieval, and reasoning. Corvic replaces this with a unified, agentic architecture that enables rapid deployment of zero-hallucination GenAI applications built on complex, multimodal data. The platform operationalizes three core laws—Agentic Data Transformation, Multimodal Retrieval Fabric, and Adaptive Agentic Orchestration—to ensure trustworthy data access, contextual understanding, and dynamic reasoning. By integrating graph AI, semantic search, multimodal retrieval, and explainable agentic workflows, Corvic delivers higher precision, full traceability, and dramatically faster time-to-value, reducing development cycles from months to days. The platform powers use cases across compliance, analytics, customer support, research, and predictive intelligence, offering enterprises a scalable path to reliable AI adoption.

People

Hadi Ahmadi

Corvic AI

Engineering Presentation

A Unified QA Framework for Intel Library Validation Using Siemens Solido Crosscheck

2:30pm - 2:45pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionHigh-quality standard-cell libraries are essential for reliable SoC design and sign-off. However, modern libraries span many views, PVT corners, and modeling formats, making validation increasingly complex, fragmented, and time-consuming when using ad-hoc or per-view approaches.
This work presents a structured quality-checking methodology based on Siemens Solido Crosscheck for systematic validation of standard-cell collaterals. The approach classifies checks by configuration complexity, ranging from simple Boolean validations to fully parametric checks requiring characterization-specific inputs. Native Crosscheck checks are leveraged and fine-tuned in collaboration with design and characterization engineers, while custom checks are introduced to address requirements not covered by native capabilities. The methodology supports both early, incremental validation during Liberty generation and comprehensive quality assessment once all views are available, enabling unified cross-view analysis.
The proposed framework enables scalable, parallel validation across thousands of configurations, improves detection of modeling and consistency issues early in the flow, provides structured reporting and traceability, and reduces late-stage rework ultimately accelerating time-to-market while improving release confidence and overall library quality.

People

Engineering Poster Gladiator

A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes

2:11pm - 2:22pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAdvanced‑node libraries must meet aggressive PPA targets across wide voltage ranges, including near‑/ultra‑low‑voltage operation where process variation is amplified and non‑Gaussian. Traditional sensitivity‑based LVF (SBA) fails to retain accuracy under these conditions, while Monte‑Carlo (MC) is impractical for full‑library, multi‑PVT production. We present a unified methodology that integrates
(i) ML‑based LVF to capture moments and sigma at ULV with production‑viable runtime,
(ii) MIS‑aware characterization to model simultaneous input switching for accurate gate delays—particularly on hold‑critical paths, and
(iii) in‑flow EM reliability generation and validation.
Across combinational and sequential cells, our ML‑LVF correlates closely with MC (comparable accuracy at a fraction of runtime), and MIS modeling closes the GLS vs. standalone delay gap observed on short paths. The flow also delivers signoff‑quality Liberty views with PrimeTime‑consistent timing/power correlation and enables early reliability checks. Overall, the methodology accelerates library turnaround while improving accuracy and reducing downstream timing/reliability closure risk for advanced‑node designs.

People

Analyst Presentation

A View from Wall Street

10:15am - 11:00am PDT Monday, July 27 DAC Pavilion, Exhibit Floor

DescriptionWe will examine the financial performance and key business metrics of the EDA industry through 2025, the consolidation of Engineering Software, and the material technical and market trends and requirements that are affecting the industry's business performance and strategies- including our AI/ML Phenomenonology. Among the trends and catalysts, we will again examine the progression of semiconductor R&D spending and how the market values of Cadence-Synopsys have evolved. Lastly, we will provide our updated financial projections for the EDA industry for 2026.

People

Jay Vleeschhouwer

Managing Director at Griffin Securities

Research Manuscript

Acc-SpMV: Accelerating General-Purpose Sparse Matrix-Vector Multiplication with GPU CUDA Cores

1:42pm - 1:55pm PDT Wednesday, July 29 Mtg Room 101B

AI3-II. AI/ML Application and Infrastructure

DescriptionGeneral Sparse Matrix-Vector Multiplication (SpMV) is a fundamental kernel in scientific computing, graph analysis and deep learning. However, to fully unleash the power of CUDA cores performance, systematic optimization is required for SpMV. In this paper, we propose OmniSpMV, a high-performance SpMV library on CUDA cores, with multiple optimizations, including data-locality-aware reordering, memory-efficient tiling , sparsity-aware load balancing and highly optimized SpMV kernel. Extensive experimental results on various NVIDIA GPU architectures with 2715 matrices show that, OmniSpMV achieves significant performance improvements on average, 2.58x (up to 6.39x) speedup on RTX 4090, 1.91x (up to 4.92x) speedup on A800, and 1.78x (up to 8.21x) speedup on H100 over cuSPARSE designed for CUDA cores, and 1.93x (up to 15.67x) speedup on RTX 4090, 1.70x (up to 15.02x) speedup on A800, and 1.75x (up to 14.53x) speedup on H100 over DASP designed for Tensor cores.

People

Tang Lei

Xin Zhikuang

Wang Zijian

Zhou Chunbao

Wang Jue

Wang Yangang

AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning

Research Manuscript

5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionDesign Rule Checking (DRC) is a critical yet computation-intensive stage in modern very large scale integration design. As processes evolve, the high computational cost of DRC has become a significant bottleneck for design efficiency. Current acceleration approaches do not fully leverage the parallelism of DRC, resulting in limited performance gains. To address this challenge, we propose AccDRC, an FPGA-accelerated DRC based on software–hardware co-design. On the software, we design a cell-aware partitioning strategy with a data preparation and task encapsulation mechanism, which reorganize layouts into balanced task units tailored for FPGA processing. On the hardware, we implements an acceleration architecture consisting of a locality-preserving data-loading module, a unified and reconfigurable check core, and a sparse result writeback module. This architecture exploits DRC's locality, structural commonality across rules, and sparse violation outcomes, enabling high-throughput dataflow execution with multi-level parallelism. Experimental results show that AccDRC achieves 522.11x ~1071.03x speedup over the CPU-based DRC tool KLayout, and 9.62x ~ 26.07 x speedup over the state-of-the-art GPU-based DRC tool OpenDRC.

People

Research Manuscript

Accelcim: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator

1:42pm - 1:55pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionSRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators.

People

Anhui Polytechnic University

Work in Progress

Accelerated Dynamic Voltage Drop Prediction Using a Lightweight Machine Learning Model

5:21pm - 5:22pm PDT Monday, July 27 Exhibit Hall

DescriptionAccurate dynamic voltage drop (DVD) analysis is increasingly critical in advanced nodes, where higher densities, lower voltages, and complex packaging exacerbate power delivery challenges. Traditional simulations are computationally expensive and typically performed late in the design cycle, risking costly redesigns. We propose a lightweight ML-based DVD prediction model using multi-scale CNNs, fusion layers, and skip connections to capture spatial and hierarchical power grid features. The model uniquely incorporates package and grid inductance and supports both vectorless and vector-based inputs. Evaluated on a 16 nm RISC-V core, it achieves 80-86 % accuracy with 5 mV tolerance and over 25,000× faster runtime than commercial tools.

People

Itay Yonatanov

Ido Parchomovsky

Mohamad Omari

Freddy Gabbay

Accelerating AI+SAR Applications Through Enhanced Graph Optimization

Research Manuscript

2:21pm - 2:34pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionSynthetic Aperture Radar (SAR), benefiting from its all-weather, all-time, and high-resolution characteristics, has become a vital tool in earth observation.
A typical application of SAR first completes the imaging process of echo data and then conducts subsequent analysis.
As AI excels in image classification and recognition, integrating AI with SAR has garnered significant interest.
In order to leverage the acceleration capabilities of existing AI frameworks, particularly graph optimizations, while also reducing developing complexity, developers strive to streamline the entire SAR application within these frameworks.
However, a key performance challenge arises: SAR imaging differs greatly from typical AI tasks in both the requirements of data layouts and the composition of operators, causing graph optimizations to fail in effectively accelerating the SAR imaging process.
The fundamental reason is the failure of the two key graph optimizations: layout transformation and operator splitting.

In this paper, we first address the issue of significant transpose overhead introduced by the layout transformation strategy.
To this end, we propose a novel layout transformation strategy based on pseudo-transposition operators, which can completely eliminate transpose overhead while maintaining memory access efficiency.
Subsequently, we design a tailored splitting strategy based on movable reverse-order operators to compensate for existing frameworks' lack of capability in handling the core FFT operators.
The proposed strategies were implemented in PyTorch and LiteRT, yielding a significant speedup of 3.45x for SAR imaging process.

People

Yang Shi

Yaohua Wang

Zhe Li

Accelerating CPU Design in Advanced Nodes with AI-Powered Floor Planning and VT Optimization

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs technology nodes scale into the angstrom regime, design complexity has surged due to stringent performance, power, and area (PPA) targets and the need to manage diverse cell libraries across multiple PVT corners. Achieving optimal cell selection, macro placement, and layer distribution under these conditions is highly challenging, making manual tuning impractical given tight timing closure, power budgets, VT proliferation, and floorplan sensitivity. Automation is now essential to enable systematic design space exploration and maintain competitiveness.
This paper presents an AI-driven approach to automate floorplanning and VT optimization for macro-dominated, high-frequency CPU designs in sub-nanometer nodes. The proposed solution integrates VT-Optimizer (VT-Opt), which tunes multi-VT flows by generating adaptive VT recipes and validating them through full-flow runs, and FP-Opt, which explores alternative floorplans by adjusting bounding boxes, aspect ratios, and macro placements while targeting utilization, congestion, timing, and power. Optimal configurations are selected based on full-flow evaluations, followed by PPA optimization to achieve best-in-class results.
The methodology significantly reduces design turnaround time, mitigates risk, and improves PPA, demonstrating its effectiveness for next-generation CPU designs.

People

Lakshmidas K

Gowry Shanmugam

Accelerating DFT Verification and Enhancing Debuggability Using Veloce-Based Full Chip Gate-Level Emulation

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis paper describes the development of a full-chip gate-level emulation environment that enables DFT verification and the successful application of Debug STIL vectors generated by the Tessent DFT tool in the Veloce emulation environment, significantly improving debuggability and shortening the product verification time.

People

Engineering Presentation

Accelerating Formal Closure on Complex Hardware Designs via AI-Driven Helper Generation

4:30pm - 4:45pm PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionAs hardware designs grow in complexity, Formal Verification (FV) often hits scalability walls, resulting in "bounded" proofs rather than full closure.Deep state-space exploration is limited by computational resources. Overcoming this typically requires "helper" assertions (invariants), but manually identifying and writing these is labor-intensive and requires deep micro-architectural knowledge. In this presentation, we present our findings where we used AI/ML & GenFV to generate helpers to achieve full proofs and reduce the verification cycle time

People

Bindumadhava Singanamalli

Pandithurai Sangaiyah

Sean Safarpour

Sayandeep Sayandeep Sanyal

Engineering Poster

Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionHPC applications like Datacenter, Server, AI-Training and AI-Inference application chips are Multi Billion Big-Die Designs and requires huge compute and disk requirements for simulations. Depending on the type of design architecture logic subsystems are repeated 30 to 80% of full design. Full flat simulations on such designs take ~8k to 11k cores with a peak machine memory requirement of 200TB to 300TB. Disk space requirement would be ~50TB. Hence, running Full Flat simulations are not practical as they would be taking huge compute and disk space resources. Full chip EMIR checks are important to ensure Blocks and Subsystems are well connected with RDL/Bumps and to ensure signoff is within margin. This can be done at abstract level with blocks' and subsystems' current and parasitic modelled using Reduced Order Model (ROM).On using ROM, a significant reduction is observed in run-time and disk-space used while maintaining accuracy.

People

Work in Progress

Accelerating Functional Fault Grading for Flash and DRAM Designs

6:32pm - 6:33pm PDT Monday, July 27 Exhibit Hall

DescriptionFunctional fault grading is essential for post-silicon validation in scan-limited designs, but simulation cost grows with fault and pattern volume. We propose an optimization-driven methodology combining static fault optimization, fault clustering, design pruning, stimulus grading, dynamic fault optimization, and parallel fault simulation management. By leveraging both structural design information and stimulus behavior, the flow eliminates redundant computation by performing optimized simulations tailored to fault activation and propagation potential. Applied to a production-grade NAND Flash and DRAM designs, the approach achieved a 3.7x and 2x reduction in simulation time, respectively, while preserving test coverage. The methodology is broadly applicable to logic and SoC designs, offering scalable fault grading without reliance on scan structures.

People

Research Manuscript

Accelerating GPU Inference of Large Language Models with Moderately Unstructured Sparse Weight Matrices

3:30pm - 3:43pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionWith the growing deployment of large language models (LLMs), LLM inference cost has become a key challenge. Pruning techniques that introduce sparsity into weight matrices can accelerate inference. However, maintaining model quality typically limits pruning to moderate unstructured sparsity (around 50\%). At these sparsity levels, none of the existing GPU kernels for sparse matrix multiplication (SpMM) can outperform their dense counterparts. This paper proposes an efficient GPU inference method for LLMs with moderate sparsity. We propose a three-layer matrix storage format comprising: (i) a Sparse-TC layer enabling sparse tensor cores to accelerate SpMM; (ii) a Slot-Filling layer using parallel differential distance for matrix compression while supporting low-cost on-chip decoding; (iii) a lightweight Residual Layer ensuring correct SpMM computation. Building on this format, we design a SpMM kernel that jointly utilizes sparse tensor cores and CUDA cores. This design enables an efficient execution pipeline and overlaps on-chip computation with memory access. Evaluations show that our work is the first to outperform dense matrix multiplication on modern GPUs equipped with high-bandwidth memory (HBM). It achieves up to 1.64× kernel-level speedup over SpInfer (EuroSys'25, Best paper) and up to 1.41× end-to-end speedups over FlashLLM (VLDB'24). Our source code: https://anonymous.4open.science/r/spmm-32E1.

People

Tao Lu

National Univerisity of Singapore

Accelerating IR and Timing Convergence with Revolutionary IR-ECO

Wenzhi Chen

Zhejiang University

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionComplex applications (such as AI & HPC) and advanced tech nodes are driving a dramatic increase in design scale and complexity. It's currently impractical to construct a robust power delivery network (PDN) by consuming a large amount of design resources and the higher local cell density causes worse voltage drop(IR) violations than ever before. At the same time, the margin of the process is decreasing continuously, the influence of voltage drop on timing is becoming increasing prominent. Therefore, it becomes crucial to establish the correlation between IR and timing to avoid over-fixing.
In traditional flow,
§ We fix IR violations by fixing thousands of violation instances(victims). However, this approach has a low profit. It takes multiple manual iterations to resolve the violations, because the root cause of the violations(aggressors) is not identified.
§ The impact on timing cannot be considered during the manual IR violation fix cycles. Meanwhile, an instance with IR issue is usually also an instance that is sensitive to the timing. In this case, we finally need to perform a hard tradeoff between IR and timing.
§ Separated IR and Timing ECOs are very time consuming, costly and always posed significant challenges for design closure within tape-out timelines.
To minimize iteration counts and design changes, avoid timing degradation or chip failure, an automated late-stage timing-aware IR fix methodology is proposed here. The joint IR-ECO flow ensures seamless communication between the golden ECO tool PrimeClosure and golden IR/EM analysis tool RedHawk-SC, enables accurate identification of root cause aggressors, provides immediate feedback on the voltage impact of ECO operations proposed by PrimeClosure, and automatically fixes IR violations without timing hurt.
In our design, IR-ECO can fix over 60% of signoff-stage IR violations within a few hours, and introducing few/no negative impact on timing, which is very important for timing- critical blocks. Minimum number of instances changed by addressing aggressors. Fewer design change operations and minimum iterations can save several weeks of iteration period than traditional flow. This offering better PPA and significantly boosts the time to tape out.
keywords : IR-ECO, IR-timing closure, aggressor analytics, timing-aware IR fix

People

Engineering Poster

Accelerating Memory Cache Verification with AI-Powered Batch Flow Methodology

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAchieving rigorous 6-6.5σ yield targets in L1 caches and other memory IP components requires extensive high-sigma verification. However, traditional brute-force Monte Carlo simulations and manually piloted GUI-based analyses are too slow and inefficient to verify large numbers of cells within tight project timelines, limiting analysis scope and compromising critical worst-case corner identification.

This paper introduces an innovative AI-powered batch flow that automates and significantly accelerates high-sigma memory cache verification, ensuring accurate, full-coverage analysis across all cells and components. The proposed methodology leverages adaptive AI to rapidly identify worst-case corners and eliminates unnecessary high-sigma runs by only deploying brute-force accurate verification on the identified critical corners.

In an example testcase, this AI-powered batch flow achieved full-coverage verification across 726 netlists in 38 hours and 20 minutes, averaging 2,514 simulations per job, representing an average 3.25x runtime speedup and 2.4x simulation speedup per job over the previous GUI-based method. Enhanced modeling and yield solver algorithms also contributed to reducing per-job simulations, and the flow automation and parallelization reduced engineering effort and overall runtime, making full coverage verification feasible within production timelines and improving disk space management. This scalable, AI-driven flow provides a fast, accurate, and comprehensive solution for memory IP validation challenges.

People

Engineering Presentation

Accelerating RTL and Verification Development via Automated Visual-to-Executable Specification Generation

10:30am - 10:45am PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionThe accelerating scale and intricacy of system‑on‑chip (SoC) designs demand innovative methodologies for register‑transfer‑level (RTL) development and verification to sustain aggressive time‑to‑market objectives. Typical chip development starts with architectural planning and diagrammatical representations for visual reference (.vsdx). This is followed with generation of Block/Sub-System wise specifications to use it for RTL Development and Verification. However, conventional flow relies on manual abstraction of these downstream specifications, which is highly resource-intensive, error‑prone, and prone to inconsistencies with the canonical design intent. The proposed work introduces an automated utility that extracts structural information from high‑level architecture diagrams (.vsdm) and synthesizes a comprehensive JSON metadata repository. The generated metadata serves as a single source of truth for automatically deriving all downstream collaterals required for RTL coding and verification, thereby eliminating manual transcription errors and ensuring alignment with the golden architecture reference. The utility also incorporates a sanity checker that validates and corrects architecture diagrams to conform with design guidelines. Integration of the metadata with existing verification frameworks further streamlines test‑bench generation and compliance checking. Experimental deployment demonstrates a substantial reduction in specification‑related issue tickets and a measurable acceleration of RTL development and verification cycles, confirming the utility's effectiveness in mitigating human effort and error.

People

Engineering Presentation

Accelerating X-State Aware Power Simulation Using Advanced Hardware Emulation

1:30pm - 1:45pm PDT Wednesday, July 29 Seaside Ballroom A

EDA

Systems

DescriptionWith the advent of the A.I era, the amount of handling data of SOC has sky-rocketed and power consumption inevitably increased. To suppress this phenomenon, various low-power hardware architectures have been added to the SOC and consequently 1) "X" values that cause bugs at silicon level have appeared and 2) verification complexity and TAT have increased to detect "X". Emulator is a general solution for reducing verification time, but it degrades the quality of power verification since it can only express two logical states ("0" and "1"). In this study, we propose a high performance 4-state ("0", "1", "X", and "Z") RTL power-aware simulation methodology leveraging an emulator. This methodology focuses on the precise modeling of UPF (Unified Power Format) intents and 4-state logic, which are vital for capturing realistic power behavior. We demonstrate that the seamless verification of UPF-driven power scenarios at hardware speeds while maintaining the logic granularity of 4-state simulation. Finally, by applying to the latest SOC project, we confirm that there is a 35 times performance gain compared to conventional simulation.

People

Research Manuscript

Accshield: Operator-Aware Robust Scheduling for Fault-Tolerant AI Accelerators

1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 202C

EDA

EDA9. Test, Validation and Silicon Lifecycle Management

DescriptionTo meet the increasing computational demands of large language models (LLMs), multi-systolic-array architectures are widely adopted by AI accelerators. However, compared with single-array designs, hardware faults in multi-array accelerators propagate more complexly way and cause more severe reliability degradation. Directly deploying single-array fault-tolerant mechanisms to multi-array architectures will introduces significant overhead. To address this limitation, we propose a Reliability-Aware Scheduling framework that jointly considers hardware-level reliability variations, operator-level error sensitivity, and inter-operator data dependencies. The scheduler maps insensitive operators to faulty arrays and reserves reliable arrays for critical computations, significantly improving reliability with minimal performance loss.

People

Engineering Poster

Accurate Characterization Methodology for Combo-IO Design with Concurrent Switching Outputs for Precise Power Analysis at SoC

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs semiconductor technology scales to smaller nodes, achieving area-optimized and low-power integrated circuits require advanced design architecture ‘s coupled with precise power estimation. Accurate power analysis depends on NLPM data embedded in Liberty models, which guide critical architectural trade-offs.

This paper investigates internal power modelling challenges in modern System-on-Chip designs employing Combo-IO architectures, where multiple communication standards such as GPIO, I2C, and I3C are integrated within a single physical block. The absence of dedicated control signals causes multiple receiver outputs to switch simultaneously, leading to significant inaccuracies in conventional internal energy characterization.

A comparative study of two characterization methodologies, path-based vs design-based, is presented for Combo-IO, with experiments driven by Siemens Characterizer. Liberty models generated by these methods are validated through power analysis.

Results demonstrate that path-based characterization leads to a scalable overestimation of internal power, with errors ranging from 2X to 4X for designs containing two to four active outputs. The proposed design-based methodology accurately distributes energy dissipation across concurrently switching outputs, enabling reliable power estimation for advanced low-power ICs.

People

Engineering Poster Gladiator

Accurate Full-Custom Thermal and EM Analysis for Advanced Nodes

5:45pm - 5:52pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAnalyzing circuits for susceptibility to electro-migration has been a requirement for integrated circuit design since the 1960's. In fact, one of the basic equations for electro-migration, Black's Equation, was formalized in 1969 and is still in use today. In related work, Statistical Electro-migration budgeting (SEB) was developed by DEC in the 1980's. Both these equations are the foundation of the electro-migration analyses used in modern EMIR tools. One very important feature of these equations is that they are exponentially dependent upon the wire temperature and failures start to occur with increasing probability at higher temperatures. This fact is important because with the introduction of new device structures such as FINFET, GAA, and possibly CFET, the power per unit area and resulting heating generated by these structures has been increasing dramatically. In addition, the power dissipated by high resistance wires and vias is also increasing as these wires need to carry higher RMS currents to support higher frequency operation of the circuits. Therefore, it is becoming increasingly critical to model the temperature very accurately for small device structures to avoid EM failures associated with high device and wire heating. By utilizing the latest Finite Element solvers (FEM) available from various CAD vendors, accurate wire temperatures can be computed by solving the heat conduction equations at the device and wire nanoscale thereby providing very useful feedback to designers regarding thermal and EM SEB FIT reliability risk for unusual corner cases that require additional validation using these more accurate simulations.

People

David Newmark

Accurate Impact Modeling for Threshold Voltage Mismatch of Transistors in Same Chip

Engineering Presentation

1:45pm - 2:00pm PDT Tuesday, July 28 Seaside RM 7

Design

EDA

DescriptionIt has been observed for several years that transistors of different threshold voltage types (VT) in one chip may contain different silicon to SPICE gap (S2S). This gap may result in risk of yield loss when industry uses SS (all VTs at SS) and FF (all VTs at FF) in signoff because of omitting risk when one VT is fast but the other VT is slow. This risk on timing is called as VT skew. Currently, there is no efficient approach that can accurately quantize VT skew risk. To solve this issue, this study introduces an analytical metric and an Monte-Carlo (MC)-based solution to accurately model Vt skew impact. The analytical metric can help give early quick assessment and the MC-based solution has been developed inside EDA tool.

People

Research Manuscript

ACE-NAS: A Zero-Cost NAS Framework for Co-Design of Architecture and Encoding in Spiking Neural Networks

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionSpiking Neural Networks (SNNs) promise exceptional energy efficiency for neuromorphic computing through event-driven processing. However, unlocking their full potential requires navigating a
complex, strongly coupled design space of network topology and
temporal neural encoding. Existing SNN Neural Architecture Search
(NAS) frameworks typically decouple these dimensions, focusing
exclusively on topology search while relying on manual, fixed encoding schemes. This limitation leaves a vast portion of the design
space unexplored, resulting in sub-optimal energy-accuracy trade-offs. To bridge this gap, we present ACE-NAS, the first zero-cost
NAS framework that automates the co-design of SNN architecture
and encoding mechanisms. Addressing the challenge of "encoding-blind" proxies, we introduce Jacob_cov, a novel Jacobian-based
spectral metric that efficiently quantifies the temporal discriminability of different encoding schemes without training. ACE-NAS
integrates Jacob_cov with structural proxies (ZiCo) into a hardware-aware, multi-objective evolutionary search strategy. On CIFAR-10,
ACE-NAS achieves 92.95% accuracy, effectively identifying Pareto-optimal designs that balance high performance with minimal spike
activity. By automating the joint optimization of structure and
dynamics, ACE-NAS delivers an orders-of-magnitude reduction
compared to standard training-based NAS and a 7× speedup over
state-of-the-art efficient SNN-NAS methods (e.g., AutoSNN).

People

Mingyu Qin

Sun Yat-Sen University

Liangming Fang

Wei Liu

Jinghai Wang

shanlin xiao

Achieving "zero Defect" Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & Verification

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAutomotive Ethernet ICs require robust design and extensive high-sigma verification to meet stringent "zero defect" quality standards, with every device parameter required to yield at least 5σ. Robustness by design is time-consuming and introduces PPA and EMI tradeoffs that must be mitigated by parameter optimization. Traditional brute-force Monte Carlo simulations are impractical for high-sigma verification, and manually trimming and optimizing parameters is time-intensive.

This paper presents an innovative AI-powered methodology that significantly accelerates high-sigma verification, trimming, and optimization for automotive ethernet solutions. This approach integrates adaptive AI for efficient parameter robustness screening and ML-based sensitivity analysis for identifying parameters that most contribute to variation, while intelligent, built-in trimming and optimization in-the-loop automatically mitigate sensitive parameters to bring critical measurements back into spec.

In the example Bandgap Reference to Low-Dropout (LDO) circuit, the proposed methodology achieves strong correlation with silicon production data, while providing >64,000x speedup over brute-force methods. This solution accurately predicts high-sigma failures, automatically determines trim codes, and automatically optimizes targets with minimal simulations, leading to substantial speedups, reduced resource requirements, and faster time-to-market.

People

Krishanu Dey

NXP

Ganesha Moorthy Krishnasamy

Engineering Poster

Achieving High-Integrity Safety for 360-Degree Automotive Display Soc's RETIME-IP: A Static Analysis Approach to ASIL-D Compliance

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe RETIME-IP is a critical component in OMNIVISION's image sensor SoC, used in automotive, 360-degree surround-view systems. This IP is responsible for receiving raw data from upstream image sources, processing it, and storing it into SRAM for consumption by downstream modules. Given that this SoC is classified as ISO-26262 ASIL-D, the RETIME-IP must also adhere to ASIL-D requirements, in accordance with the ASIL decomposition guidelines set forth in ISO 26262-10:2018, Clause 11. While the RETIME-IP was initially designed with several safety-mechanisms (SMs) to meet the necessary fault coverage, subsequent fault injection analysis identified the need for additional SMs to reach the ASIL-D targets.
This paper outlines a novel methodology using a Certified tool as per ISO26262-8:11. Using Static Analysis fault classification to find the safety gaps and thereby add SMs only in the areas required without the increase in the hardware. An intuitive way of fault classification to ISO26262 classification is employed. Also to reduce the faults that need to be simulated, Constant-Analysis, is employed to mark blocked faults as safe. The result was not only achieving the ASIL-D SPFM target of 99% but also achieving it in much less iterations, thereby saving project time compared to similar SoC projects.

People

Jerry (Chaojie) Chen

Omnivision Technologies (Shanghai) Co. Ltd

Niko (Bicheng) Guo

Omnivision Technologies (Shanghai) Co. Ltd

Sesha Sai Kumar C V

Optima Design Automation Ltd

Jamil R Mazzawi

Optima Design Automation Ltd

Research Manuscript

Achieving Intra- and Inter-Operator Communication Lower Bounds in Near-Memory Processing

10:56am - 11:10am PDT Tuesday, July 28 Mtg Room 203AB

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionNear-memory processing (NMP) is a promising way to overcome the memory wall in large language models (LLMs). However, dataflow optimization in NMP is fundamentally constrained, as existing analyses cannot efficiently handle the new distributed vault/channel organization. We propose the Remote-Access-Free (RAF) dataflow, which uses tensor rotation to abstract this distributed organization and eliminate all intra-operator remote access. On top of RAF, we apply analytical optimization to minimize intra-operator local access, thereby achieving the intra-operator communication lower bound. We then introduce data partitioning that removes inter-operator remote access and enable operator fusion to minimize inter-operator local access, so that the inter-operator communication lower bound is also reached. Experimental results show that RAF reduces energy by 50.4%, 39.0%, and 37.8%, and delivers speedups of 3.98×, 1.72×, and 1.57× over IANUS, H^2LLM, and OptiPIM, respectively.

People

Lei Xu

Chen Yin

Zelong Yuan

Weiguang Sheng

Jianfei Jiang

Qin Wang

Naifeng Jing

ACM SIGDA/IEEE CEDA University Demonstration

Student

10:00am - 7:00pm PDT Monday, July 27 Exhibit Hall

Student

Research Manuscript

Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge

1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS1. Autonomous Systems (Automotive, Robotics, Drones)

DescriptionVision-Language-Action (VLA) models have emerged as a unified paradigm for robotic perception and control, enabling emergent generalization and long-horizon task execution. However, their deployment in dynamic, real-world environments is severely hindered by high inference latency. While smooth robotic interaction requires control frequencies of 20--30 Hz, current VLA models typically operate at only 3--5 Hz on edge devices due to the memory-bound nature of autoregressive decoding. Existing optimizations often require extensive retraining or compromise model accuracy.

To bridge this gap, we introduce ActionFlow, a system-level inference framework tailored for resource-constrained edge platforms. At the core of ActionFlow is a Cross-Request Pipelining strategy, a novel scheduler that redefines VLA inference as a macro-pipeline of micro-requests. The strategy intelligently batches memory-bound Decode phases with compute-bound Prefill phases across continuous time steps to maximize hardware utilization. Furthermore, to support this scheduling, we propose a \textbf{Cross-Request State Packed Forward} operator and a Unified KV Ring Buffer, which fuse fragmented memory operations into efficient dense computations. Experimental results demonstrate that ActionFlow achieves a 2.55 times improvement in FPS on the OpenVLA-7B model without retraining, enabling real-time dynamic manipulation on edge hardware.
Our work is available at https://anonymous.4open.science/r/ActionFlow-1D47.

People

Yuntao Dai

Hang Gu

Qianyu Cheng

Yifei Zheng

zhiyong qiu

IEIT Systems Co., Ltd.

Active Imitation Learning for Thermal- and Kernel-Aware LFM Inference on 3D S-NUCA Many-Cores

Research Manuscript

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionLarge Foundation Model (LFM) inference is both memory- and compute-intensive, traditionally relying on GPUs. However, their limited availability and high cost have driven growing interest in high-performance general-purpose CPUs, particularly emerging 3D-stacked Static Non-Uniform Cache Architecture (3D S-NUCA) systems. While these architectures improve bandwidth and data locality, they introduce severe thermal constraints and non-uniform cache latencies caused by 3D Networks-on-Chip (NoC). Efficient management of thread migration and V/f scaling remains challenging due to diverse LFM kernels and hardware heterogeneity. We propose AILFM, an Active Imitation Learning (AIL)–based scheduling framework that learns near-optimal thermal-aware policies from Oracle demonstrations with minimal runtime overhead. AILFM captures both core-level performance variations and kernel-specific behavior, maintaining thermal safety while maximizing inference efficiency. Extensive experiments demonstrate that AILFM outperforms state-of-the-art baselines and generalizes across diverse LFM workloads.

People

Yixian Shen

Chaoyao Shen

Jan Deen

George Floros

Andy Pimentel

Anuj Pathania

Activity Reloaded: Joules Flash Replay - A Methodology for Accurate, Delay-Based Activity Generation for Driving Optimization and Power Sign-off

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAccurate switching activity is essential for effective low‑power optimization in modern digital flows, however, activity fidelity rapidly degrades as RTL progresses through synthesis, mapping, and physical implementation. This loss of annotation forces downstream tools to depend on incomplete or vectorless estimates, diminishing the quality of power optimization. Glitch power, which can account for 20-30% of total dynamic power at advanced nodes, typically requires costly delay‑based Gate Level Simulation (GLS), resulting in prohibitive runtime and compute overhead. Conventional activity regeneration further relies on RTL or GLS teams, creating schedule bottlenecks and widening PPA gaps.

The proposed Flash Replay flow methodology eliminates these limitations by enabling rapid, on‑demand activity refresh using the Joules RTL Power tool, with minimal turnaround‑time impact on the full digital flow. It generates glitch‑aware power data significantly faster than GLS and reconstructs complete switching activity for vectorless or partially stimulated designs using lightweight seed vectors or prior RTL activity of the same design. Seamless integration with Genus and Innovus enables consistent, delay‑based activity generation throughout the RTL‑to‑signoff flow.

Results demonstrate up to 10% total power reduction when Flash Replay is incorporated into existing implementation flows, along with up to 25X speedup versus simulation‑based replay. These improvements establish Flash Replay as a practical, scalable solution for restoring activity accuracy and enhancing low‑power implementation efficiency.

People

Nimish Agashiwala

Activity-Aware Partitioning for Effective Multi-Threaded Event-Driven RTL Simulation

Research Manuscript

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionRegister-transfer-level (RTL) simulation is commonly accelerated through multi-threading and event-driven technique.
However, when these techniques are combined, severe load imbalance arises: in event-driven execution, circuit regions exhibit highly uneven activity, leaving many threads idle with very low utilization.
Existing multi-threaded RTL partitioning models often optimize full-cycle execution and ignore the dynamic activity variation that dominates event-driven workloads.

We present PGSIM, a multi-threaded event-driven RTL simulator that incorporates runtime activity information into its partitioning model.
Our model augments hypergraph weights with measured activity frequency and inter-block activation correlation, which is efficiently estimated through a lightweight MinHash profiler.
By aligning thread assignment with true activity patterns, PGSIM substantially reduces idle time and improves utilization.
Across experiments on large benchmarks, PGSIM achieves 20–30% higher performance than its activity-unaware version, delivers a simulation speed of 200-400 kHz and up to 8.9× speedup over Verilator.
These results demonstrate that runtime activity modeling is essential for scalable multi-threaded event-driven simulation.

People

Pengpeng Ren

Yun (Eric) Liang

Adagscale: Viewpoint-Adaptive Gaussian Scaling in 3D Gaussian Splatting to Reduce Gaussian-Tile Pairs

Research Manuscript

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionReducing the number of Gaussian-tile pairs is one of the most promising approaches to improve 3D Gaussian Splatting (3D-GS) rendering speed on GPUs. However, the importance difference existing among Gaussian-tile pairs has never been considered in the previous works. In this paper, we propose AdaGScale, a novel viewpoint-adaptive Gaussian scaling technique for reducing the number of Gaussian-tile pairs. AdaGScale is based on the observation that the peripheral tiles located far from Gaussian center contribute negligibly to pixel color accumulation. This suggests an opportunity for reducing the number of Gaussian-tile pairs based on color contribution. AdaGScale efficiently estimates the color contribution in the peripheral region of each Gaussian during a preprocessing stage and adaptively scales its size based on the peripheral score. As a result, Gaussians with lower importance intersect with fewer tiles during the intersection test, which improves rendering speed while maintaining image quality. The adjusted size is used only for tile intersection test, and the original size is retained during color accumulation to preserve visual fidelity. Experimental results show that AdaGScale achieves up to 9.47× speedup over the original 3D-GS on a GPU, with only about 0.2 dB degradation in PSNR.

People

Research Manuscript

Adahuff-GNN: A Convergency-Aware Adaptive Huffman Compression for Communication Reduction in Distributed GNN Training

11:23am - 11:36am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionDistributed training of Graph Neural Networks (GNNs) is hindered by communication overhead from exchanging embeddings and gradients. Existing quantization methods mitigate this cost by using shared bit widths at the layer or group level, followed by node-level uniform quantization, but such coarse granularity cannot fully exploit redundancy in long-tailed communication distributions. Entropy compression is well suited to these distributions, but static entropy compression schemes become less effective when training induces untracked distribution shifts. To address this issue, AdaHuff-GNN, a convergency-aware adaptive Huffman compression framework, is proposed to apply entropy compression to reduce communication cost in distributed GNN training. Within AdaHuff-GNN, loss-triggered codebook reconstruction and coarse-to-fine adaptive selection of codebook sizes jointly produce stage-wise codebooks that track distribution shifts. Binning-assisted clustering and conflict-free decoding reduce codec overhead on the communication critical path. Experiments show that AdaHuff-GNN reduces communication volume by 2.87× and shortens training epoch time by 37.5% over state-of-the-art methods without degrading model accuracy.

People

Zhiyu Sun

Jihe Wang

zhaohui jia

Yuanhua Xiao

Linying Wu

Adana: Accelerating Large Language Models via Adaptive Nonuniform Asymmetric Quantization

Danghui Wang

NPU

Research Manuscript

4:36pm - 4:50pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionWe propose \texttt{Adana}, a hardware-software co-design that enables efficient low-bit group-wise quantization for LLMs based on the adaptive nonuniform asymmetric numeric type. First, \texttt{Adana} introduces a novel numeric type that precisely captures the nonuniformity and asymmetry of data within small groups. In addition, an approximate metric for quantization error is proposed to facilitate efficient implementation of online adaptive activation quantization. Finally, a dedicated LLM acceleration microarchitecture is developed for \texttt{Adana}. Compared to state-of-the-art designs, \texttt{Adana} achieves 1.42$\times$--2.10$\times$ speedups and 18.9\%--48.5\% power savings on LLMs, while maintaining superior accuracy.

People

Xinkuang Geng

Siting Liu

Hui Wang

Leibo Liu

Jie Han

University of Alberta

Honglan Jiang

ADAPT: An Algorithm-Hardware Co-Design for Spiking Transformer with Training-Free Adaptive Token Pruning and Hierarchical Sparsity

Research Manuscript

1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionSpiking neural networks (SNNs) represent a promising solution for emerging architectures due to high sparsity and low power consumption. Spiking Transformers extend these advantages to attention-based modeling and show strong potential for energy-efficient applications. However, their practical deployment remains difficult. Spiking transformers demand substantial computation and memory access because of long token sequences and heavy workloads in feed-forward networks. Moreover, existing sparse optimization methods provide limited benefit for spiking transformers since they either focus only on unstructured bit-level sparsity or require model retraining. This work presents ADAPT, an algorithm–hardware co-design that exploits the hierarchical sparsity of spiking transformers. At the algorithm level, we propose Adaptive Token Pruning (ATP), a training-free method that evaluates token diversity and spike activity to remove redundant tokens. At the hardware level, we design a hierarchical-sparse accelerator that introduces a block-sparsity compression format and a pattern processing unit to leverage repeated bit patterns inside non-zero blocks. Experiments on multiple spiking transformer models demonstrate that ATP prunes 50\% of tokens with negligible accuracy loss. The ADAPT accelerator achieves average speedups of 3.1x and 4.2x over state-of-the-art SNN accelerators Prosperity and GPU, while reducing energy by 1.9x and 149.4x. These results show that exploiting hierarchical sparsity with algorithm–hardware co-design enables efficient deployment of spiking transformers.

People

Pinfeng Jiang

Yilong Fang

Letian Wang

Yi Wang

Mingde Zhu

Xiangshui Miao

Xingsheng Wang

Adaptive AI and Additive AI Techniques for High-Sigma Standard Cell Verification

Engineering Presentation

1:45pm - 2:00pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionAs chip complexity reaches tens of billions of transistors, standard cells are duplicated millions of times, making fast and accurate high‑sigma verification essential. Fixed‑sigma approaches are no longer viable. Each cell requires a flexible sigma target to avoid redesign and to enable yield‑based repurposing rather than discarding.
We present a fully automated, AI‑driven methodology that verifies an entire standard cell library in a single pass. Adaptive AI tailors verification jobs to individual cells, while Additive AI iteratively refines models across multiple PVT and input‑vector conditions, delivering brute‑force‑level accuracy without additional simulations.
The Worst‑Case Yield Solver (WCYS) identifies near‑target and worst‑case samples in the Solido PVTMC Verifier, builds predictive models, and triggers a reinforcement‑learning‑based High‑Sigma Verifier only when sign‑off criteria demand. Dynamic Constraint Yield Sign‑off (DCYS) automatically sweeps failing‑cell constraints until they pass, reducing the number of failed cells by 2.4×.
Compared with traditional scaled Monte‑Carlo methods, the proposed flow achieves a ten‑fold speedup, a tighter confidence interval (6.000 [5.900–6.098] vs 6.180 [5.067–7.146]), and a 60 % reduction in cells failing between 0.5 V and 0.6 V. This AI‑enabled verification provides 6‑sigma‑level confidence across massive libraries while substantially reducing verification time and resource consumption.

People

Engineering Poster

Adaptive Multi-Agent Framework for Automated Constraint Generation

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern semiconductor design demands managing diverse constraints-- timing, power, CDC, RDC, UPF-- across multiple EDA flows. Manual writing, scripting and validation of these constraints is slow, error-prone, and inconsistent.

We propose a multi-agent, debate-driven system--orchestrated by GitHub Copilot-- to transform this process into intelligent automation. The system orchestrates constraint generation and validation through a structured refinement loop: Generate, Critique, Debate, Human-Feedback and Evolution. The system becomes an expert that understands our silicon context by integrating human expertise into an adaptive feedback loop-- rapidly prioritizing corrective actions based on real-time violations. Advanced context engineering methodologies like RAG, RLHF, and MCP ensure consistent context management for the agents and effective constraint generation across diverse tool environments.

This approach accelerates signoff, reduces errors, and scales seamlessly across heterogeneous constraint domains-- paving the way for intent-driven, intelligent design methodologies.

People

Research Manuscript

Adaptive Multiply-Accumulate Unit with Scalable Critical Path for Aggressive Voltage Underscaling DNN Accelerators

3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionDeep neural network (DNN) accelerators have been investigated for efficient inference. Underscaling the supply voltage of MACs can effectively reduce the power dissipation. In this paper, we propose a bit-width adjustment circuit (denoted as ADA) for arbitrary MAC unit under aggressive voltage underscaling. Incurring 16% area overhead, the proposed ADA enables a MAC array to achieve zero accuracy loss. While preserving accuracy, the MAC array equipped with ADA achieves up to 48% power reduction compared to that without ADA. Furthermore, we propose ADA-Plus to optimize the MACs in output stationary systolic arrays, which reduces the area of ADA by 23%.

People

Tongjing Wu

Siting Liu

Tong Li

Hui Wang

Zhigang Mao

Jie Han

University of Alberta

Honglan Jiang

Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks

Engineering Presentation

11:00am - 11:15am PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionThis work presents a reinforcement learning (RL) approach to optimize System-on-Chip (SoC) performance by automatically tuning Quality of Service (QoS) knobs. As SoC complexity increases, manual optimization of diverse QoS parameters across varying scenarios becomes intractable. To address this, we develop a simulation environment mimicking the SoC, where an RL agent explores the design space to identify optimal knob settings. We employ Deep Q-Networks (DQN) and enhancements (e.g., Double DQN, Dueling Networks) within a Markov Decision Process (MDP) framework, defining states, actions, and reward systems based on key metrics like throughput, latency, and power. Techniques such as Temporal Difference (TD) learning and Prioritized Experience Replay (PER) improve sample efficiency and convergence. Our framework rapidly evaluates configurations under different SoC architectures. Experimental results demonstrate the RL model's ability to discover high-performance, power-efficient QoS settings through training, significantly improving over manual methods. This work highlights RL's potential in automating SoC design optimization, offering a scalable solution for complex multi-master systems and paving the way for future design automation research.

People

Research Manuscript

Adaptive Read Retry Table Extension for Enhanced Data Reliability in 3D NAND Flash Memory

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

Description3D NAND flash is widely used from PCs to data centers, but its major weakness is data reliability. As data is retained, charge leakage causes read errors. Vendors mitigate this using the read retry mechanism, which iteratively applies predefined read reference voltage combinations, called read retry parameters (RRPs), stored in a read retry table (RRT). However, the limited number of RRPs can lead to RRP burnout, a condition where all read retry parameter entries have been exhausted without successful data recovery.
In such cases, the data becomes undecodable and the corresponding block is marked as bad, degrading both capacity and lifetime of the NAND flash. Experiment showed that even a small portion of recovey failures may lead to significant capacity loss. We propose an Adaptive RRT Extension framework, integrating two key mechanisms: WL-Aware Interpolated Retry (WIR) and Multi-Dimensional Guided Retry (MDGR), to expand recovery capability. Experiments show that our method recovers up to 99\% of failed pages and preserves up to 99\% and 84\% of usable capacity under 12- and 30-month retention, respectively—where the baseline retains only 90\% or reaches end-of-life.

People

Han-Yu Liao

National Taiwan University and Innodisk Corporation

Chen-Xing Chang

Innodisk Corporation

Jen-Wei Hsieh

National Taiwan University of Science and Technology

Hung-Pin Chen

Innodisk Corporation

Yuan-Hao Chang

Adaptive Spiking Neural Networks for Real-Time Multi-Object Detection Tasks

Research Manuscript

2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionProviding deterministic timing guarantees, beyond merely optimizing the accuracy-latency trade-off, is a mandatory yet unaddressed challenge for ultra-low-power spiking neural networks (SNNs) in resource-limited, safety-critical systems. In this paper, we propose RT-SNN, a novel adaptive SNN methods that integrates a system-level scheduling framework for SNN-based multi-object detection that, for the first time, co-optimizes inference accuracy while providing these strict timing guarantees. RT-SNN orchestrates SNN inference at both frame and timestep levels, introducing flexible timestep control and a novel membrane potential reuse mechanism to enhance accuracy without increasing latency. Evaluations on the KITTI dataset show that RT-SNN significantly improves the accuracy and energy efficiency compared to both state-of-the-art SNNs and traditional ANNs. Furthermore, a case study on a ROS-based F1/10 autonomous vehicle testbed demonstrates its real-time efficacy, validating its practical deployment in safety-critical systems.

People

Donghwa Kang

Korea Advanced Institute of Science and Technology (KAIST)

Woojin Shin

University of Seoul (UOS)

Cheol-Ho Hong

Chung-Ang University

Byunghoon Kang

Korea Advanced Institute of Science and Technology (KAIST)

Jinkyu Lee

Yonsei University

Hyeongboo Baek

Department of Artificial Intelligence, University of Seoul (UOS)

Additional Meeting

Additional Meeting - Accellera Luncheon: Embracing AI for Advanced Design and Verification

12:30pm - 1:45pm PDT Tuesday, July 28 Mtg Room 104C

DescriptionJoin Accellera for a dynamic luncheon exploring how artificial intelligence is reshaping the standards landscape for design and verification. As AI and machine learning are increasingly integrated into EDA workflows—from design generation to verification and system-level optimization—new challenges are emerging around interoperability, data exchange, trust, and reproducibility.

This session will highlight key areas where standards can enable scalable innovation, including AI-driven methodologies, training data availability, safety and security considerations. Attendees will gain forward-looking insights from industry experts and have the opportunity to share perspectives on where standardization is most needed across industry and academia.

Seating is limited and will be offered on a first-come, first-served basis.

People

Additional Meeting

Additional Meeting - CEDA Lunch: The Role of Open-Source Hardware in AI for EDA

12:00pm - 1:30pm PDT Tuesday, July 28 Mtg Room 104B

DescriptionSemiconductors have enabled today’s AI, and continued progress in AI will remain tightly coupled to advances in semiconductor hardware. This hardware is becoming increasingly specialized and heterogeneous, from accelerator-rich system-on-chip (SoC) devices to chiplet-based systems in advanced packages. At the same time, growing design complexity threatens this progress, as engineering and verification effort continues to rise and the semiconductor industry faces a persistent workforce gap. Agentic AI is expected to help address this challenge by boosting design productivity through a new class of EDA tools. Yet major obstacles remain. Hardware design is intrinsically different from software development, and many of the high-quality design artifacts, datasets, and workflows needed to train, evaluate, and validate AI-based methods are proprietary. Building on my experience developing ESP, an open-source platform for heterogeneous SoC design, this talk makes the case that open-source hardware is a key enabler for effective AI for EDA. By providing shareable artifacts, reproducible evaluation, and collaboration at scale across universities, government labs, and industry, open-source hardware can accelerate the development and validation of agentic AI workflows, while fostering curriculum innovation to train the next generation of hardware engineers and EDA tool developers.

People

Luca Carloni

Columbia University

Engineering Poster

Advanced Automation for DC Die Generation and Verification

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionA Daisy Chain (DC) die replicates the final package design mechanically to evaluate Board Level Reliability (BLR) and die-package interface. Typically the daisy chain die is created manually with some automation enabled for signal or ground routes. In case of package iterations, this causes rework especially depending on the ground bump pattern.

The paper looks at a semi-automated method to make the daisy chain connections thereby reducing manual effort and an automated way to confirm the integrity of the package-die connection. Using the proposed method the daisy chain die creation has been reduced from a couple of days to a couple of hours. The integrated checks also help catch real shorts if present on the package removing the need for manual review.

People

Engineering Presentation

Advanced Automation Framework for Clock and Reset Management in SoC Designs – Bridging Design Intent, Verification, Test and Implementation

10:30am - 10:45am PDT Wednesday, July 29 Seaside Ballroom A

EDA

Security

DescriptionAbstract
• Modern SOCs typically have dozens of clock domains, multi‑phase clock‑generation structures and dividers, complex reset-architecture and numerous exception constraints. This information must be handled consistently from RTL design to verification (DV) testbenches, DFT clock/reset architecture and finally to the timing constraints used for physical‑design implementation. Current practices rely on manual extraction of clocking, constraints and reset data from multiple documents, leading to long turnaround times, human error, and fragmented management of inconsistent data.
• This paper presents an advanced automation framework that is built on a Template Clock & Reset Management (CRM) document defined for a given family of devices. It generates timing constraints as well as the verification testcases from the CRM document, leveraging a lightweight parsing engine. The framework automatically generates UVM‑compatible DV testbench components (clock drivers, reset sequencers) and timing constraint files (source and generated clock definitions, case analysis, exceptions like multicycle path, false path, clock groups, etc.), ensuring strict traceability between design intent, verification, test and implementation. The automation framework also generates the DFT clock planner directly from the functional clock planner, which derives test frequency, test clock domains, shaping ICG creation and DFT overrides test structures ensuring error-free DFT RTL for higher quality, fewer iterations, and faster pre-silicon verification.

Motivation
• Increase productivity and reduce human error – By consolidating all clock, reset and exception related metadata (clock definitions, MCP entries, exception rules, reset ordering) into a single, version‑controlled document, the same data can be consumed automatically by scripts that generate DV test‑bench components, DFT clocking planner and PD constraint files. This eliminates repetitive iterations and ensures that any change is reflected everywhere instantly.
• Establish a single source of truth – A centrally maintained document provides traceability and auditability. Designers can track who modified a clock parameter, when it was changed, and what downstream artefacts were regenerated, supporting robust change‑impact analysis. It also enforces strict alignment between functional and DFT clock domain plans by streamlining DFT clocking to ensure DFT clocks follow related functional clocks. This in-turn helps in reducing any DFT timing overheads.
• Accelerate timing closure – Automated generation of SDC constraints, DFT case analysis and exception scripts shorten the PD flow, while automatically produced UVM‑compatible clock drivers and reset sequencers speed up verification. Early detection of mismatches between design intent and implementation reduces the risk of late‑stage bugs.
• Demonstrated maturity and extensibility – The tool has already evolved through multiple releases (e.g., addition of clock‑mode columns, MCP value fields, reset‑polarity handling, and auto‑generation flags), highlighting continuous improvement and real‑world applicability of template. Once the updates are made, all downstream collaterals can be updated using scripts which saves a huge chunk of effort across all domains, while maintaining high quality standards.
• Facilitate collaboration across domains – Because the document template is editable by both verification and physical‑design engineers, it encourages cross‑team communication and aligns expectations early in the design cycle.
• Create a foundation for future enhancements – With the data model in place, extensions such as power‑aware clock gating, dynamic frequency scaling, or integration with a broader "SOC timing data hub" can be added with minimal effort.

People

Suganthi VadivelMurugan

Engineering Poster

Advanced Hard IP Integration Requirement Extraction and Checker

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionMotivation: In SoCs 3rd party and TI internal hard IPs such as PHY, PLL, Dividers, etc are often required and integrated. An integration and specification document is often shared which contains the intricacies to be taken care during implementation. However, the integration requirements are often scattered across multiple pages, embedded on figures/tables, etc. The current manual approach of extracting, reviewing, and translating these requirements into actionable checklists is time-consuming and error-prone. The requirements can be scattered across different documents too. Eg ODP and efuse controller are expected to be in the same power domain but, the requirement is present in the fusefarm document and not in the ODP document. These need to be clubbed together and might be missed unless the user has read all documents.

Solution: An AI based automated approach in two phases. Phase 1 leverages AI-based document parsing to intelligently extract and categorize integration requirements into multiple categories - floorplan, IR, timing, placement etc. with automatically correlating cross-document dependencies. Phase 2 employs AI to translate these requirements into automated TCL-based checkers and where feasible, provide TCL based fix coding scripts.

Impact: The Physical Design (PD) team emerges as the most significant beneficiary of this AI-powered solution, as they are directly responsible for implementing majority of integration requirements extracted from specification documents. Experimental validation across various design integration documents have shown significant time saving up to 2 weeks and zero requirement omission rates, making it a scalable solution.

Future scope: While the current system requires prompt refinement and domain expertise for evolving IP types and documentation formats, future enhancements will incorporate automated prompt optimization to minimize specialist dependencies.

People

Mili K Johnson

Ben Thomas

Kavithaa Rajagopalan

Digital Verification Manager

Pankaj Talwar

Engineering Presentation

Advanced Hard IP Integration Requirement Extraction and Checker

2:15pm - 2:30pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

People

Mili Johnson

Ben Thomas

Kavithaa Rajagopalan

Pankaj Talwar

Advanced Packaging: From Concept to Deployment

Research Special Session

1:30pm - 2:00pm PDT Monday, July 27 Mtg Room 201A

Systems

DescriptionAdvanced packaging is deployed with increasing frequency to support heterogenous integration, chiplet design strategies, and enablement of large SOCs. For AI applications in particular, it is the only way to integrate the large compute silicon area and high memory capacity and bandwidth required for competitive products. This talk will review the usage of advanced packaging technologies in AMD products across various families, with an emphasis on AI products such as the AMD Instinct™ MI300, which blends 3D hybrid bond logic die stacking, 2.5D interposers, and HBM into a single SOC. Trends observed in AI products are then used to project the evolution of advanced packaging technologies, including finer pitch scaling, continued growth in module size, and increasing power delivery and thermal demands. These trends will finally be connected to design and test strategies. As cost and complexity grow, creating manufacturing flows that allow accurate screening at multiple steps in the process to ensure good yield and quality are an essential part of 'Design-Technology Co-optimiziation' (DTCO). Successful products will require careful consideration of test methods in every chiplet and at every step of the manufacturing flow.

People

Bill Lambert

Advancements in Heterogeneous Integration and 3D Packaging for Next-Generation Scalable Photonic Integrated Systems

Research Special Session

2:30pm - 3:00pm PDT Wednesday, July 29 Mtg Room 201A

EDA

DescriptionIn this talk, AIM Photonics presents advances in heterogeneous integration and 3D packaging within 300 mm silicon photonics at the Albany Nanotech Complex. We highlight results from laser integration on PICs using 2.5D and monolithic bonding, offering dense integration capabilities. The talk also covers 3D co-packaged optics (CPO) architectures that lead to large gains in optical interconnect efficiency and bandwidth. Finally, we discuss unique features of our design automation offerings, including feature-rich photonic PDKs and Assembly Design Kit, enabling efficient, accurate circuit design and packaging. These innovations address key challenges in manufacturability, scalability, and yield for next-generation photonic AI systems.

People

David Harame

AIM Photonics

Research Special Session

Advances in AI-Driven Hardware Code Generation: Insights from the Comprehensive Verilog Design Problems Benchmark

3:30pm - 4:00pm PDT Monday, July 27 Mtg Room 201A

DescriptionAI-driven hardware code generation, across both frontier LLMs and emerging agentic workflows, is advancing rapidly, yet it still trails the maturity of AI-driven software development. High-quality benchmarks are essential for catalyzing progress, revealing capability gaps, and guiding the development of new methodologies. The Comprehensive Verilog Design Problems (CVDP) benchmark, now adopted by the Silicon Integration Initiative's LLM Benchmarking Coalition, provides a foundation for evaluating these capabilities within the broader silicon design community. We survey the evolving landscape of language models and agentic systems for hardware design, examining their performance on RTL generation, testbench creation, debugging, and related tasks through the lens of CVDP. We highlight emerging trends, persistent challenges, and key opportunities for advancing trustworthy and automation-ready hardware design flows.

People

Nathaniel Pinckney

Advancing CDC Formal Verification in Low-Power SoCs Using Power Intent and Smart Waiver Techniques

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIncorrect clock domain synchronization can cause critical functional bugs in SoCs, potentially requiring costly fixes. When low-power requirements with multiple switchable power domains are involved, CDC verification becomes more complex. In UPF-based low-power designs, isolation cells at power domain boundaries preserve signal integrity but may cause resynchronization issues if their enable signals are improperly synchronized, leading to metastability or failures. The presence of isolation cells, retention registers, and their enable signals increases the number of asynchronous paths to analyze.
This paper proposes a new flow based on formally proven' smart waiver CDC jointly with LPV that drastically reduces the number of CDC and RDC violations to analyze in a typical ultra-low-power SoC. Normally, the number of violations can be several hundred, but this flow safely waives those proved true through formal verification. The remaining violations can then be analyzed to uncover real resynchronization bugs.
In the presented test case, the number of violations to analyze was reduced by about 35%, enabling the discovery of bugs that might have been lost among the initial hundreds of violation reports. Formal verification remains the optimal method for CDC checking, and Jasper CDC with LPV enables power-aware CDC verification using UPF

People

David Vincenzoni

Erik Seligman

Greg Milano

Ran Zhao

Advancing Macro Placement: Integrating Proven Design Practices with Reinforcement Learning

Research Manuscript

5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionMacro placement is a critical stage in physical design, directly impacting the quality and performance of VLSI circuits. We propose a reinforcement learning (RL)-based macro placement framework that integrates proven design practices through a design-practice-embedded action mask, including peripheral placement, dead space avoidance, and proximal placement for macros with shared design hierarchy and physical footprint. Unlike previous RL based methods, our method uses macro clusters-formed according to design hierarchy and physical footprint-as the basic placement units, which reduces placement steps and consequently accelerates convergence and improves runtime. The proposed framework also introduces a novel compaction method to minimize wasted area caused by grid granularity, and jointly optimizes macro cluster location and tiling pattern for more effective exploration. Experimental results show that our approach achieves expert level placement quality and consistently outperforms three leading commercial macro placers on industrial designs, with reduced turnaround time. On public benchmarks, our method achieves up to 25.37% and 39.51% improvements in worst negative slack (WNS) and total negative slack (TNS), respectively, over five state of the art (SOTA) placers. These results demonstrate the effectiveness and real-world applicability of our RL based framework, paving the way for further advancements in physical design automation.

People

Engineering Presentation

Advancing Silicon Lifecycle Management with Embedded Trace

4:00pm - 4:15pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionSilicon Lifecycle Monitoring (SLM) addresses the lifetime silicon health and reliability challenges from early life to end of life. While ATPG based structural tests are very effective at detecting manufacturing defects there are many other complex failure mechanisms that manifest during operational lifetime and require in-field debug and continuous monitoring. The root cause of such failures are latent manufacturing defects, IR Drop, leakage currents, thermal effects, soft errors, and aging – many of which fall into the category of silent data corruption (SDC). Functional failures often manifest as program misbehavior that impact large scale deployment of highly connected systems such as web servers, 5G base stations, automotives and AI/ML processors.
We describe an SLM solution that uses an embedded trace system as its foundation. This collects time stamped data to analyze the trajectory of the transactions involving the CPU, memory, I/Os, peripherals, and other sub-systems. Trace data is highly compressible (up to 700 X) and can be easily stored in system or offloaded for analysis that executes in less than 165 milliseconds for these programs. Results on an industrial benchmark (for RISC-V CPUs) and an AI Inference engine silicon case study demonstrate the value and effectiveness of this approach.

People

Research Manuscript

Agent-Per-Qubit: Automated Qubit Placement for Fault-Tolerant Quantum Computing

2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionQuantum computing holds the potential to revolutionize numerous fields, yet the practical execution of quantum circuits depends on an efficient compilation process, including the placement of logical qubits on a quantum chip. This placement is a hard combinatorial problem that often defeats traditional heuristics and manual optimization. We present QAgent, a novel multi-agent reinforcement learning (RL) framework that autonomously optimizes logical qubit layouts on quantum processor. In QAgent, one agent is assigned to each logical qubit, and agents jointly learn placement policies that minimize circuit execution cost. To address the challenges of sparse rewards and credit assignment, we propose the Breakthrough Return Bonus (BRB), a dynamic reward shaping mechanism that encourages meaningful layout improvements and accelerates convergence. Extensive experiments on diverse quantum circuit benchmarks show that QAgent reduces execution costs by up to 53.9% compared to leading approaches, and significantly enhances circuit success rates. Ablation studies confirm that BRB is essential for stable training and effective policy optimization. These results demonstrate the promise of AI-driven, workload-aware placement for advancing fault-tolerant quantum computation.

People

Tian Li

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Yang Wang

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Tan Li

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Wan-Su Bao

Henan Key Laboratory of Quantum infommation and Cryptography Zhengzhou

Work in Progress

Agentic AI for Chip Design and Verification: Results and Limitations from CVDP

5:13pm - 5:14pm PDT Monday, July 27 Exhibit Hall

DescriptionWe benchmark a new agentic AI approach for chip design and verification on the CVDP dataset. Our results show that multi-agent orchestration, custom system prompts, and improved tool-use guidance enable our agent to debug and complete substantially more complex hardware verification problems. On relevant CVDP problems, our agent demonstrates a relative advantage of 11.6% vs. CVDP state of the art performance and 15.3% vs. Claude Code. Beyond aggregate metrics, we analyze execution traces and find evidence of enhanced reasoning and debugging capabilities, as well as important limitations of under- and over-specified test harnesses.

People

DAC Pavilion Panel

Agentic AI in EDA: Who's in Control?

4:00pm - 4:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

DescriptionAbstract: EDA is on the brink of its most disruptive transformation yet. Agentic AI—multi-agent systems capable of autonomous, goal-driven decision-making—promises to move beyond assistive point solutions toward orchestrating entire design flows. From synthesis and verification to physical design and system optimization, these agents could redefine productivity and complexity management. Yet as autonomy grows, critical questions emerge: Who—or what—is really in control?

This panel will explore the technical, organizational, and ethical tensions surrounding agentic AI adoption. We’ll examine infrastructure and governance: securing sensitive IP and maintaining compliance when autonomous agents operate across hybrid environments. We’ll discuss interoperability and standards: for example, Si2’s AI/ML EDA ontology provides a standardized representation of design terminology and relationships, bridging graph representations, ML datasets, and tool semantics to enable agents to reason about workflows. Such efforts highlight both the promise and the challenge of enabling multi-vendor collaboration without fragmenting the ecosystem. Finally, we’ll confront trust and accountability: how do we reason about correctness, explainability, and oversight when design decisions emerge from interacting agents rather than deterministic scripts?

The discussion will surface points of disagreement across the ecosystem, including how much autonomy is desirable, which risks are acceptable, and whether current infrastructures and standards are sufficient. Attendees will leave with a clearer understanding of the readiness of agentic AI, practical tensions it raises, and open questions shaping its future adoption.
Watch for Si2 DAC updates!

Moderator:
Leigh Anne Clevenger | VP Technology | Si2

Speakers:
Natesan Venkateswaran | Program Director, EDA Analysis | IBM
Lindsey Kostas | Principal/Manager ML Research | Qualcomm
Ivan Kissiov | Principal Engineer | Siemens EDA
Srinivas Bodapati | Technical Leader-Pre-Silicon Design Risk Mitigation | Nvidia
Da Yang | Senior Director | Nvidia

People

Natesan Venkateswaran

Engineering Poster

Agentic AI Partition And Floorplan Assistance For PCIe/CXL Subsystem Physical Design

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe deployment of advanced high-speed protocols (e.g., PCIe Gen6/CXL) in multi-billion-gate designs creates a severe "Logical-Physical Gap," where traditional implementation flows suffer from unmanageable runtimes and convergence volatility. This work introduces a novel Cognitive Agentic Framework that orchestrates multi-objective partitioning and semantic-driven floorplanning to bridge this divide. Unlike conventional methodologies relying on blind min-cut algorithms or static placement rules, our approach utilizes HGNN to predict physical feasibility during logical partitioning, optimizing for size balance, boundary timing, and data stream integrity. Furthermore, we propose Dataflow-Driven Vision-Language Reinforced Semantic Floorplanning, where a Large Multimodal Model functions as a "visual perception sensor" within a physics-based force field. This allows the agent to iteratively "see" congestion hotspots and dynamically adjust repulsion forces to enforce semantic consistency. By embedding physical awareness into the architectural phase, our framework reduces the design iteration cycle, achieving superior PPA metrics and deterministic timing closure compared to standard industrial flows.

People

yuwenyuan gao

Agentic Time-Travel Debugging for HLS Code

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionHigh-Level Synthesis (HLS) code is often developed using a subset of C/C++, along with specialized libraries. This allows HLS engineers to make use of standard software engineering tools and techniques during the development and debug phase of their project. This talk introduces the topic of time-travel debugging, whereby the state of a design can be examined by going backwards and forwards in time. This approach saves huge amounts of effort, allowing the root cause of bugs, including challenging concurrency bugs, to be found with ease and a new codebase to be understood rapidly.
Beyond this, we will look at how you can connect the latest AI models to the time-travel debugging tools to enable Agentic Time-Travel Debugging capabilities to verify hypotheses and predictions against authoritative records of what did happen during execution, closing the loop to allow the AI Agents to iterate and improve their diagnosis of behaviour until they get a verified root cause diagnosis of issues during development and simulation. It is also possible to generate waveforms from the recordings and report detailed root cause explanations, using waveforms and language that potentially explains complex software issues to hardware developers generating or using the HLS models.

People

Jonathan Bonsor-Matthews

LightBlue Logic

Research Manuscript

Agenticdse: A Multi-Agent Design Space Exploration Framework with Multi-Phase Bayesian Optimization for Chiplet Accelerators

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionChiplet accelerators offer a scalable solution for LLM inference with reduced manufacturing costs. However, the design space exploration (DSE) of chiplet accelerators is challenging due to the complex design space. Prior black-box Bayesian optimization (BO) solutions lack domain knowledge, limiting their effectiveness. In this work, we propose AgenticDSE, a multi-agent DSE framework that incorporates the collaboration of three LLM agents, i.e., exploration orchestrator, architecture analyst, and optimization engineer. This multi-agent framework enhances exploration efficiency through analysis-driven design space refinement and phase-wise design exploration using ensemble surrogate modeling. Over the same number of explorations, AgenticDSE achieves up to 36.9% reduction of average distance to the real Pareto front, and 66% increase in diversity of explored Pareto front compared to state-of-the-art DSE solutions. Additionally, it offers scalable performance with 46x and 18x reduction in input and output token consumption compared to prior LLM-based solutions.

People

Engineering Poster Gladiator

Agile Silicon: A Gitops-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts

2:33pm - 2:45pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionCo-packaged optics (CPO) presents unique physical design challenges: numerous small blocks with irregular shapes to accommodate photonics and analog integration, combined with frequent RTL changes extending close to tapeout due to evolving system architectures of cutting-edge silicon photonics design. Traditional manual PD flows widely used in the industry cannot sustain rapid iteration requirements while maintaining team scalability. We present a production-grade GitOps-based PD orchestration framework that treats PD recipes as version-controlled code, enabling automated synthesis through signoff with CI/CD integration. Our framework leverages YAML/Jinja configuration templates, parallel multi-block execution, commercial LLM APIs enabled with EDA tool docs, and human-in-the-loop validation via automated QoR regression and Slack notifications. Deployed at Lighmatter, a fabless CPO company, this system enabled a team of fewer than 10 PD engineers to successfully deliver multiple test chips and product tapeouts with boosted productivity compared to industry baselines, while seamlessly absorbing RTL changes in the final two months before tapeout. Beyond immediate productivity gains, this infrastructure establishes the data collection and execution framework necessary for AI-agent-assisted PD optimization, providing auditable run histories and structured metrics that serve as training data for autonomous design exploration.

People

Research Manuscript

AHASD: Asynchronous Heterogeneous Architecture for LLM Adaptive Drafting Speculative Decoding on Mobile Devices

11:23am - 11:36am PDT Wednesday, July 29 Mtg Room 101A

AI4-I. AI/ML Architecture Design

DescriptionSpeculative decoding enhances the inference efficiency of large language models (LLMs) by generating drafts using a small draft language model (DLM) and verifying them in batches with a large target language model (TLM). However, adaptive drafting inference on a mobile single-NPU-PIM system faces idle overhead in traditional operator-level synchronous execution and wasted computation in asynchronous execution due to fluctuations in draft length. This paper introduces AHASD, a task-level asynchronous mobile NPU-PIM heterogeneous architecture for speculative decoding. Notably, AHASD achieves parallel drafting on the PIM and verification on a single NPU through task-level DLM-TLM decoupling and specifically, it incorporates Entropy-History-Aware Drafting Control and Time-Aware Pre-Verification Control to dynamically manage adaptive drafting algorithm execution and pre-verification timing, suppressing invalid drafting based on low-confidence drafts. Additionally, AHASD integrates Attention Algorithm Units and Gated Task Scheduling Units within LPDDR5-PIM to enable attention link localization and sub-microsecond task switching on the PIM side. Experimental results for different LLMs and adaptive drafting algorithms show that AHASD achieves up to 4.2× in throughput and 5.6× in energy efficiency improvements over a GPU-only baseline, and 1.5× in throughput and 1.24× in energy efficiency gains over the state-of-the-art GPU+PIM baseline, with hardware overhead below 3% of the DRAM area.

People

Zirui Ma

zhihua fan

Institute of Computing Technology, Chinese Academy of Sciences

Wenxing Li

Haibin Wu

State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences

Engineering Special Session

AI and Multi‑die: A Reinforcing Cycle

10:30am - 12:00pm PDT Wednesday, July 29 Seaside RM 7

Chiplet

Design

EDA

DescriptionThe convergence of AI and multi‑die architectures is reshaping the fundamentals of compute efficiency. Near‑memory and in‑memory processing—enabled by advanced non‑volatile memory technologies—reduces data movement and latency, accelerating AI workloads at their source. Cost‑effective multi‑die integration unlocks scalable performance without escalating silicon expense, fueling innovation from edge devices to hyperscale cloud.

Automotive‑grade AI raises the bar further, requiring multi‑die reliability that meets rigorous functional‑safety demands. Sustainability pressures drive advances in interconnect efficiency, power‑aware partitioning, and intelligent storage hierarchies across AI–multi‑die systems. Collectively, these trends point toward a future where heterogeneous integration and intelligent compute evolve in tandem, delivering new levels of performance, robustness, and environmental efficiency.

People

Engineering Special Session

AI for Specifications Across the Stack: Formalization, Alignment, Reconstruction, and Handoff

3:30pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionSpecifications remain the foundation of silicon development, yet they suffer from systemic problems that compound across the stack. This talk addresses four critical challenges: (1) Formal vs. Informal Specs: Natural language specs create ambiguity, contradiction, and drift. AI enables incremental formalization - translating high-value sections into machine-readable formats while keeping specs accessible. (2) Living Documents vs. Snapshots: Specs diverge from implementation almost immediately. AI-powered drift detection and spec-as-code practices can keep specs aligned with reality throughout the development lifecycle. (3) Spec Archaeology: Legacy IP, acquisitions, and lost documentation create integration risk. AI can reconstruct specs from RTL/firmware and surface undocumented assumptions from tribal knowledge sources. (4) Cross-Company Interfaces: Specs crossing organizational boundaries become contractual documents where ambiguity has legal and financial consequences. Structured, AI-validated specs reduce handoff risk with IP vendors, OSATs, and customers.

People

Erfan Rostami

Co-Founder and CTO of Voltai

Welcome Address

AI Supercomputing Meets EDA: Accelerating the Future of Chip and System Design

5:00pm - 5:45pm PDT Sunday, July 26 Mtg Room 104B

EDA

DescriptionA new era is emerging where AI supercomputing and EDA come together to redefine what is possible in chip and system design. Accelerated computing, foundation models, and intelligent design flows are transforming every stage of the journey, from architecture and verification to deployment in complex, secure systems. As AI, Design, EDA, Security, and Systems converge, design cycles can shrink, chiplet-based and future quantum-ready platforms can become practical, and human creativity can be amplified. This keynote explores how collaborating with AI at scale can unlock breakthrough performance, faster innovation, and a new generation of chips and systems that power the world’s most ambitious ideas.

People

Timothy Costa

AI‑Assisted Formal Verification: Improving Practical Adoption and Scalability

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs chip complexity continues to grow, shift-left verification has become critical for improving verification efficiency and design quality. Formal Verification is a key enabler of shift-left adoption, as it provides exhaustive analysis and exposes corner case bugs early in the design cycle. Despite these advantages, many design verification (DV) teams struggle to adopt formal methods due to expertise gaps, scalability limitations, and the perceived difficulty of manual property authoring.

This presentation introduces a practical, AI-assisted roadmap for scaling formal verification across IP, subsystem, and SoC level designs. The approach combines early "quick win" formal applications (linting, UNR, connectivity) with scalable intermediate techniques (CSR, CDC/RDC, safety and security), and extends to advanced Formal Property Verification (FPV). Recent advancements in AI-assisted assertion generation, leveraging natural-language-to-property workflows, context-aware reasoning, and automated constraint derivation significantly reduce the manual effort required for FPV setup.

The methodology has been field tested across real design teams, demonstrating improved scalability, faster proof convergence, reduced assertion authoring effort, and higher overall adoption. Key complexity management techniques, including modularization, abstraction, and constraint strategies, are also discussed as essential enablers for deploying formal verification at scale in modern front-end verification flows.

People

Muhammed Luqman Jukaku

Ai&cell Based Analog Circuit Topology Generator(ctgen)

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis provides the new analog design methodology which will generates schematic topology for practical usage.
The abstract concept of topology generation is following.
Decompose the many circuits schematic resources to small cells or blocks.
Then construct for the best combination topology to meet the each specific target under spice simulation base optimization for block level architecture schematic. This design could be existing schematic but partially structured as blocks which internally build by connected between selectable libraries' cells or blocks.
Each cell and block are already validated and parametric , the final schematic is acceptable by designers.
This tool is independent from circuit categories and any process. The evaluations are from spice simulation under PDK from testbenches.
This may produce better combined circuit topology than depending on designers experiences or skill.
The key technologies of this tool are
1. AI searching method in huge combinatorial space which is used like Alpha-GO
2. Recent Machine learning algorithm for circuit parameter optimization
3. Dived the stage as learning and inference which scalable by machine resources
This will improve the reusability and improve migration efficiency equipped with topology changing.
The final design sign off could be done in current customers design environments.

People

Kyoto Institute of Technology

Nobukazu TAKAI

Kyoto Institute of Technology

Shigetoshi NAKATAKE

University of Kitakyushu

Tetsuya IIZUKA

The University of Tokyo

Engineering Poster

AI-Accelerated Optimization Flow for Robust Analog and Mixed-Signal Circuit Design Against Process Variation

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionEkepower is committed to developing chips for advanced printing technology. A key feature of these innovative chips is their integration of diverse circuit block functionalities into a single device. These include high-voltage motor and printhead drivers, precise timing references essential for the entire system, and RF sensor integration capable of detecting signals with extremely low voltage. Finding a universal simulation and verification platform that efficiently accommodates the unique requirements of different circuit blocks remains a significant challenge.

By leveraging integration with the Solido Simulation Suite and Solido Design Environment, users gain access to comprehensive analysis and accelerated performance compared to traditional workflows, without compromising accuracy. Additionally, AI-driven variation-aware feature enable thorough verification and identification of circuit distributions, facilitating the efficient creation of trimming plans to optimize both analysis and circuit performance.

Ekepower leverages this design flow to efficiently verify and optimize circuit blocks with varying properties simultaneously through transient, RF, and mixed-signal analysis, achieving speed improvements of up to 7.6x over conventional methods. Additionally, the AI-powered and automated trimming flow effectively optimizes circuit blocks, resulting in an overall reduction in top-level voltage variation.

People

Engineering Poster

AI-Accelerated Signoff Verification and Glitch Analysis for Single and Multibit Level Shifters

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionLevel shifters are critical for reliable cross-voltage domain communication: their failure risks the integrity of the circuit, excessive power dissipation, and damage to components. Extensive verification is required to mitigate their susceptibility to device variability and multiple failure mechanisms. Traditional brute-force Monte Carlo analysis is infeasible for evaluating all failure modes across large corner sets at advanced nodes, making accurate, timely verification challenging.

This paper introduces an AI-powered, high-throughput batch flow for fast, accurate signoff verification of single and multibit level shifter cells. Adaptive AI performs rapid identification of worst-case corners, which are then verified with AI-powered, brute-force accurate high-sigma technology. This precision deployment optimizes runtime and resources by running high-sigma verification only when necessary.

The proposed methodology demonstrates significant improvements over previous methods. 3σ single-cell validation was 3x faster than traditional brute-force Monte Carlo, and high-sigma verification precision deployment reduced overall runtime by 10x across 256 cells at 6σ. Targeted analysis validated glitch heights in multibit level shifters at 3σ and 6σ, with precision deployment reducing overall runtime by >14x. This AI-driven solution optimizes compute and engineering resources to provide timely, accurate guidance on reduced verification timelines, ensuring full-coverage functional robustness, improved silicon quality, and faster time-to-market.

People

Engineering Presentation

AI-Assisted EDA Tools Development

10:30am - 10:45am PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionEDA tool development often suffers from redundant effort and complexity due to repeated implementation of common HDL parsing and construction tasks. This work introduces an AI-assisted framework that leverages MCP modular building blocks and an Agentic AI approach to automate tool generation, eliminating the need for deep parser expertise. The proposed methodology collects user specifications and synthesizes EDA tools using reusable components. Applied to IBM structural verification tools, the framework demonstrated significant productivity gains - reducing development time from an estimated four person-weeks to under 30 minutes. The generated implementation required 1,110 lines of code, with approximately 90% reused across checks, ensuring scalability and maintainability. By automating repetitive tasks and enabling rapid deployment of new checks, this approach accelerates design workflows, improves reusability, and shortens time-to-market for EDA tools. The results highlight a transformative shift from manual coding to AI-driven synthesis, addressing inefficiencies and empowering design teams to focus on innovation.

People

Engineering Poster

AI-Driven Co-Optimization of Power Delivery Network for High-Power Cores in 2.5D Advanced Packaging

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe increasing adoption of chiplet-based 2.5D advanced packaging has introduced formidable power integrity (PI) challenges, requiring the simultaneous optimization of static DC performance and dynamic AC response—a complex, multi-variable task traditionally reliant on manual expertise. This paper presents an integrated, AI-driven workflow that fully automates the PI co-optimization process. For DC performance, the methodology automates the design of the interposer Power-Ground (PG) mesh. It leverages AI-based multi-objective optimization within Redhawk-SC to intelligently adjust metal patterns, directly minimizing IR drop while adhering to process design rules. For system-level AC performance, the workflow automates the selection and configuration of the hierarchical decoupling network. By combining HSPICE simulation with optimizers (optiSLang/ASO.ai), it co-optimizes components from die MIMCAP and interposer Deep-Trench Capacitors (DTC) to package decaps and PCB MLCCs, targeting impedance and noise reduction under constraints of cost, area, and assembly rules. This automated approach achieves a 26% reduction in DC IR drop and a 12% improvement in AC noise margin. Ultimately, it consolidates fragmented manual procedures into a unified flow, reducing the total PI optimization timeline from over three weeks to approximately one week, thereby enhancing design robustness and significantly accelerating time-to-market.

People

Exhibitor Forum

AI-Driven Design Automation for Analog and Mixed-Signal Circuit Design

4:00pm - 5:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionMove Silicon presents Spaceman, an AI-driven design automation toolchain developed to accelerate and optimize analog and mixed-signal circuit design. Seamlessly integrated with leading EDA environments, Spaceman automates sizing, optimization, and design-space exploration, dramatically reducing both time-to-market and engineering effort for IP and ASIC development. The goal is not to replace analog designers, but to augment their capabilities, enabling faster, smarter, and more scalable design methodologies for the next generation of semiconductors.
At the core of these results lies Move Silicon’s proprietary AI modeling technology, capable of autonomously training neural network models directly from a circuit schematic and its testbench. This approach enables highly efficient and virtually unlimited IP reuse, significantly improving design productivity and portability across projects and PDKs. Spaceman goes beyond simply identifying the correct sizing for a given specification. It shifts the paradigm from traditional SPICE-driven iterative workflows toward AI-driven predictive models, enabling immediate exploration, analysis, and forecasting of the entire design solution space for any IP.

People

Ferdinando Frediani

MoveSilicon

Engineering Presentation

AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design

11:45am - 12:00pm PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionAs semiconductor designs scale to billions of transistors, compute demands for electronic design automation (EDA) increasingly exceed the capacity of traditional on-premises infrastructure. Migrating workloads to hybrid or cloud environments offers scalability, but many organizations face inefficiencies in job provisioning, resource utilization, and scheduling accuracy. This work introduces AI Assist for EDA Cloud Optimization, a framework leveraging graph neural networks (GNNs) and reinforcement learning (RL) to forecast compute requirements and optimize workload execution across heterogeneous environments.

By analyzing job metadata from synthesis, placement, and verification stages, AI Assist predicts runtime and resource needs prior to submission—reducing overprovisioning by 60–80% and improving runtime completion speed by 20–40% in test deployments. The adaptive scheduling layer learns policies that balance cost, performance, and licensing constraints across hybrid compute environments.

Complementary modules—such as placement optimization and hotspot prediction—apply similar AI paradigms to design optimization and verification, demonstrating measurable improvements in PPA efficiency and iteration time. Together, these solutions illustrate how AI Assist enables semiconductor firms to modernize their EDA workflows securely and efficiently while accelerating design convergence in the transition to cloud-scale engineering.

People

Engineering Poster

AI-Enabled Flow for Silicon Area Reduction and Design Closure

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAbstract—Artificial Intelligence (AI) has emerged as a transfor-
mative technology in electronic design automation (EDA) flows,
enabling significant improvements in power, performance, and
area (PPA) metrics. This paper explores the critical role of AI-
driven techniques in optimizing semiconductor design processes,
highlighting how intelligent algorithms can automate decision-
making, predict optimal design parameters, and effectively re-
duce silicon area. By integrating AI into the design flow, users can
achieve enhanced PPA trade-offs, minimize manual intervention,
and accelerate time-to-market. The study demonstrates practical
methodologies and case studies illustrating how AI empowers
designers to optimize chip layouts, improve resource utilization,
and achieve superior silicon efficiency.

Index Terms—EDA, PPA, Artificial Intelligence, Floorplanning,
Silicon Area Reduction

People

Engineering Poster

AI-Enabled High-Fidelity Power Amplifier Behavioral Modeling with Commercial EDA Tools

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis paper presents an advanced AI methodology for building a high-fidelity power amplifier behavioral model using Keysight commercial EDA tools SystemVue and Advanced Design System (ADS), in conjunction with AI-enabled modeling techniques. The example device is a power amplifier circuit modeled within ADS, which a corresponding behavioral model is developed in form of a neural network. Training data for the neural network model is generated through co-simulation between SystemVue and ADS, ensuring consistency and accuracy. The resulting behavioral model not only achieves high modeling accuracy but also enables the characterization of transient circuit behavior and supports operation within a broad power range. Once developed, the model can be seamlessly imported into system-level simulation for performance verification and subsequent system-level design.

People

Lei Li

Yanhua Cui

Tong Li

Ziquan Bai

Fei Cao

AI-Enhanced Early Thermal Aware Module Placement for 3DIC PPA Optimization

Engineering Presentation

11:45am - 12:00pm PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionWhile 3D disaggregated chiplets are viewed as the future of chip design, the approach inherently has drawbacks in thermal performance. This is because some of the chiplets in a given 3D stack may not be in contact with a good heat sink. In traditional 2D design methodology, a good heat sink is usually assumed to exist, which allows thermal analysis to be deferred to the end of design cycle. In 3D disaggregate designs, however, we may not have the luxury of deferring thermal analysis, as thermal violations may not be fixable without contact to sufficient heat sink. Therefore, it is imperative to optimize for thermal behavior along with traditional performance, power, and area (PPA) metrics early in the design flow. In this work, we propose an AI-driven methodology to incorporate thermal-aware module placement that simultaneously optimizes for thermal and other PPA targets. This methodology automatically experiments with hundreds of thermal-constrained scenarios in heterogenous 3D chiplet stacks using AI-assisted analysis to achieve the best possible thermal and PPA results, while requiring minimal user guidance and intervention.

People

Xiaohu Xu

Sonia Beghum

Keshava Manimunda

AI-Native Workflows from Architecture to Production Readiness

Exhibitor Forum

4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionCustom ASIC development remains out of reach for many hardware companies. Traditional design services are expensive, timelines are long, and off-the-shelf chips often leave major cost, power, and performance on the table. Visibl is building AI-native workflows that automate large portions of chip development, from architecture and design through verification and production readiness. In this presentation, we will show how a software platform can help engineering teams move faster by reducing repetitive work, improving regression triage, and accelerating the path from product requirements to manufacturable silicon. The goal is not just better internal productivity, but making custom chip development accessible to robotics, drones, industrial, IoT, and edge hardware companies that have historically been priced out of the market.

People

Jordon Kashanchi

Visibl Semiconductors

Research Manuscript

Akirarust: Re-Thinking LLM-Aided Rust Repair Using a Feedback-Guided Thinking Switch

12:15pm - 12:30pm PDT Wednesday, July 29 Mtg Room 202C

Systems

SYS3. Embedded Software

DescriptionEliminating undefined behaviors (UBs) in Rust programs requires a deep semantic understanding to enable accurate and reliable repair. While existing studies have demonstrated the potential of LLMs to support Rust code analysis and repair, most frameworks remain constrained by inflexible templates or lack grounding in executable semantics, resulting in limited contextual awareness and semantic incorrectness. Here, we present AkiraRust, an LLM-driven repair and verification framework that incorporates a finite-state machine to dynamically adapt its detection and repair flow to runtime semantic conditions. AkiraRust introduces a dual-mode reasoning strategy that coordinates fast and slow thinking across multiple agents. Each agent is mapped to an FSM state, and a waveform-driven transition controller manages state switching, rollback decisions, and semantic checkpointing, enabling context-aware and runtime-adaptive repair. Experimental results show that AkiraRust achieves about 92% semantic correctness and delivers a 2.15× average speedup compared to SOTA.

People

Renshuang Jiang

Yichong Wang

Pan Dong

National University of Defence Technology

Xiaoxiang Fang

Zhenling Duan

Zhe Jiang

Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation

Research Manuscript

1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES3. Emerging Models of Computation

DescriptionComplex-Valued Neural Networks (CVNNs) have significant advantages in handling tasks that involve complex numbers. However, existing CVNNs are unable to quantify predictive uncertainty. We propose, for the first time, dropout-based Bayesian Complex-Valued Neural Networks (BayesCVNNs) to enable uncertainty quantification for complex-valued applications, exhibiting broad applicability and efficiency for hardware implementation due to modularity. Furthermore, as the dual-part nature of complex values significantly broadens the design space and enables novel configurations based on layer-mixing and part-mixing, we introduce an automated search approach to effectively identify optimal configurations for both real and imaginary components. To facilitate deployment, we present a framework that generates customized FPGA-based accelerators for BayesCVNNs, leveraging a set of optimized building blocks. Experiments demonstrate the best configuration can be effectively found via the automated search, attaining higher performance with lower hardware costs compared with manually crafted models. The optimized accelerators achieve approximately 4.5× and 13× speedups on different models with less than 10% power consumption compared to GPU implementations, and outperform existing work in both algorithm and hardware aspects. The code will be open-source after acceptance.

People

Zehuan Zhang

Imperial College London

Hao (Mark) Chen

Imperial College London

Research Manuscript

ALOHA: Area-Efficient and Low-Power Stochastic Computing with Hammersley Sequences

4:42pm - 4:54pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionCounter-based stochastic computing (CBSC) utilizes simple counting logic to realize multiplication. Inspired by CBSC, this paper proposes the ALOHA architecture that significantly reduces the computing latency and stochastic number generation (SNG) overhead. Specifically, ALOHA incorporates three key innovations, including input scaling, bit-reversal counter-based SNG, and sequence-aware optimization schemes. Experimental results show that the ALOHA multiplier significantly outperforms state-of-the-art CBSC designs in terms of accuracy, area and power consumption with reduced sequence length. In CNN and Transformer inference, ALOHA matches the accuracy of prior FSM-based multipliers while reducing area and energy.

People

Zhaojun Ni

Yutao Gong

Honglan Jiang

Siting Liu

Alphaplacer: Analog Placement Enhanced by Monte Carlo Tree Search

Research Manuscript

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionAnalog layout design remains heavily dependent on manual expertise, with placement being the most critical stage that requires significant development time and domain knowledge. Current automated placement techniques face challenges in capturing expert design practices and fall short of practical deployment. To address this limitation, we present AlphaPlacer, a novel MCTS-based analog placement framework that learns from historical layouts to provide expert-guided placement optimization.
Our approach formulates analog placement as a hierarchical sequence pair search with a two level MCTS structure, embedding a pretrain learning framework that captures sequence pair distributions from expert layouts to guide the search toward high quality solutions.
Experimental results demonstrate that our method significantly outperforms existing baselines across multiple key metrics including area, wirelength, and post-layout performance.

People

Yapeng Li

Peng Xu

Mingzi Wang

Tinghuan Chen

AMBER: A Unified Accelerator for Multi-Precision LLM Inference Exploiting Bit-Level Redundancy and Reconfigurability

Research Manuscript

11:36am - 11:50am PDT Monday, July 27 Mtg Room 101B

AI4-I. AI/ML Architecture Design

DescriptionModern LLMs use diverse integer, floating-point, and microscaling (MX) precisions, but most accelerators are optimized for only a few formats. We propose AMBER, a general-purpose LLM accelerator for plug-and-play multi-precision deployment and compression of weights and KV caches in cloud and edge. AMBER introduces bit-transposed encoding that exploits bit-level statistical concentration for lossless compression across all of INT, FP, and MX formats. A precision-agnostic, stage-pipelined bit-serial PE further reuses bit-level redundancy for efficient versatile precision computation. Evaluated on 8 LLMs and 10 formats, AMBER boosts memory efficiency 1.17× and compute 3.16×, surpassing Olive and Tender in throughput and energy.

People

Research Manuscript

Amoeba: Runtime Tensor Parallel Transformation for LLM Inference Services

4:06pm - 4:18pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionIn Large Language Model (LLM) inference services, it is challenging to make a parallelism strategy configuration, to efficiently process the requests of variance context lengths. Requests of long context require high degree of parallelism to provide more memory for Key-Value (KV) Cache, while requests of short context prefer low degree of parallelism to increase concurrency, thus improving throughput.

To maintain high throughput while supporting large context lengths on demand, we propose Amoeba, a runtime Tensor Parallel (TP) transformation for online LLM inference services, which adaptively adjusts the TP of running instances to align with the dynamics of incoming requests. Evaluations using real-world traces show that Amoeba improves throughput by 1.75×-6.57× compared to state-of-the-art solutions.

People

Research Manuscript

AMS Layout Automation Using Circuit-Level Analog Standard Cells and Self-Biasing Techniques in Digital PnR Tools.

3:54pm - 4:06pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionThis work presents a silicon-verified analog–mixed-signal (AMS) layout-automation framework integrating a circuit-level analog standard-cell (CLAS) library with self-biasing circuits in a digital place-and-route (PnR) environment. Unlike transistor-level stem-cell approaches, the CLAS library standardizes matched circuit-level blocks, including self-biased amplifiers, current mirrors, and delay cells. Fabricated 180-nm and 65-nm CMOS chips validate fully automated, DRC/LVS-clean layouts for a current source, adaptive-bandwidth PLL, and probabilistic computer. All benchmarks show strong pre-/post-layout and silicon correlation, with the PLL exhibiting 0.98–1.50 ps simulated and 4.1 ps measured jitter. The framework achieves ≥96 % area utilization, 14.4–69.5 % DCAP density, and <1 min–1 hr runtime, demonstrating scalable, silicon-consistent AMS automation.

People

Wonsik Oh

University of California, Santa Barbara

Luke Theogarajan

University of California, Santa Barbara

Engineering Poster

An Adaptive Dynamic Power Reduction Technique for Digital Filters

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionDigital FIR filters are typically designed for worst-case full-scale input precision, resulting in unnecessary dynamic power dissipation when processing low-amplitude signals. This paper introduces an adaptive technique that tracks real-time signal dynamic range and selectively disables toggling of sign-extended bits in datapath registers. By gating both data and clock for these redundant bits, the approach significantly reduces switching activity without impacting filter functionality or performance. Demonstrated on a 20-tap FIR filter in 28nm FDSOI technology, the proposed architecture achieved over 7% total power savings for a wideband OFDM signal with -24 dB input amplitude. The solution is fully digital, incurs minimal hardware overhead, and is easily deployable across existing filter architectures and technologies. Furthermore, it is scalable to other shift-register-based structures such as delay chains and FIFOs, making it a practical and efficient method for dynamic power reduction in contemporary signal processing systems.

People

Research Manuscript

An Adaptive Prediction of Tokens Fluctuation for Decoupled Prefetching to Accelerate Long-Context LLM Decoding

3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionThe prohibitively slow speed of long-context LLM decoding is a critical bottleneck, caused by massive Key-Value (KV) access that saturates memory bandwidth. Existing solutions fail due to a fundamental trade-off: static predictors cannot handle the Tokens Fluctuation, leading to permanent accuracy loss from irreversible eviction, while an on-the-fly scoring method creates a synchronous bottleneck that stalls the entire pipeline. This paper presents a co-designed system that breaks this trade-off by leveraging an Adaptive Prediction algorithm to enable a fully Decoupled Prefetching architecture. The proposed Adaptive Prediction model first mirrors the nature of Tokens Fluctuation, enabling a lightweight, reuse-based recovery mechanism that solves irreversible eviction. This high-fidelity prediction then unlocks the Decoupled Prefetching system, which completely hides data transfer latency and eliminates the synchronous bottleneck. On long-context LLM decoding tasks, the proposed system matches the accuracy of a full KV cache with just 256 tokens, while achieving an average 2.50x end-to-end speedup.

People

Yuanhua Xiao

Jihe Wang

Zhiyu Sun

Linying Wu

An Adjustable Length Compression Method for MBIST Repair Information

Danghui Wang

NPU

Engineering Presentation

11:30am - 11:45am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionEmbedded memories occupy the largest part of modern SoCs. As memories are high-density physical structure, they are more prone to failures than other circuits and concentrate the large majority of fabrication faults, affecting yield adversely. Hence, memory Built-In Self-Repair(BISR) is mandatory for maintaining acceptable fabrication yield. And the repair information will be burned into the electrically programmable fuse (efuse). As the chip scale increases and the number of memories increases, the required efuse resources also increase dramatically.
Therefore, researchers have proposed a series of methods to efficiently compress memory repair information and save efuse space. In the traditional compression method, there is a repair segment consists of zero compress and repair chain, to handle the worst case, the zero compress will be calculated with the whole chain length and the repair chain data will use the longest Bisr register.
This paper proposes an adjustable length compression method to effectively save the storage space of repair information. As the probability of memory faults is very low, and the fault location, number, and memory repair chain length vary. Therefore there is no need to store the longest bisr register and compress the whole repair chain. And the more fault points in the memory, the greater the benefit of the adjustable length compression method.

People

Research Manuscript

An Agile and Accurate Energy Estimation Methodology for CGRA-Mapped Algorithms: The Synchoros Approach

2:21pm - 2:34pm PDT Tuesday, July 28 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionCoarse-Grained Reconfigurable Arrays (CGRAs) are promising as
accelerators for energy and performance benefits. Agile and accu-
rate energy estimates are essential to explore the CGRA design
space and guide algorithm mapping decisions. Existing estimations
are agile but inaccurate since they do not factor in the impact
of wires in the design. This paper presents synchoros energy es-
timation methodology for post-route accurate estimations. The
methodology leverages the properties of synchoros VLSI design
style to incorporate the impact of interconnects in the design. Over-
all, our methodology achieves 98% estimation accuracy relative
to post-route results for algorithms irrespective of variations in
functionality, dimensions, and parallelism.

People

Ritika Ratnu

KTH Royal Institute of Technology

Dimitrios Stathis

KTH Royal Institute of Technology

Ahmed Hemani

KTH - Royal Institute of Technology

Engineering Poster Gladiator

An AI-Enhanced Web-Based Real-Time Analytics & Prediction Platform for ASIC Physical Design (PD) Flows

5:15pm - 5:22pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAn AI-enhanced real-time analytics and prediction platform designed to bring comprehensive intelligence to complex ASIC Physical Design (PD) flows. This tool automatically captures PD runs, parses massive volumes of logs and reports, and unifies timing, congestion, CTS, IR/EM, DRC/LVS, runtime, and resource metrics into centralized dashboards. By integrating AI-driven pre-run prediction, runtime anomaly detection, and post-run learning, the platform enables early identification of QoR regressions, resource bottlenecks, and failure risks before costly iterations are executed. The solution transforms PD workflows from reactive debugging to proactive, data-driven optimization, significantly reducing manual effort, improving resource utilization, accelerating convergence, and enhancing confidence in physical design closure.

People

Work in Progress

An Autonomous Design Agent of Parallel Feedforward Equalizer for Advanced Wireline Receivers

5:07pm - 5:08pm PDT Monday, July 27 Exhibit Hall

DescriptionFeedforward equalizers (FFEs) are critical digital signal processing (DSP) components in ultra-high speed wireline receivers, frequently limiting power and area efficiency while requiring extensive design effort. This work introduces an autonomous design agent that automatically generates FFEs from system specifications to Verilog implementation. The framework employs a computational data-flow graph model combining unfolding and fast FIR algorithm, along with nonlinear programming for architecture to circuit level optimization. A 128-parallel, 24-tap FFE for a 112-Gbps PAM-4 receiver is successfully synthesized in TSMC 28-nm CMOS within 6 hours using the design agent, achieving 14 % power and 25 % area savings.

People

Research Manuscript

An Efficient Heterogeneous Co-Design for Fine-Tuning on a Single GPU

12:03pm - 12:16pm PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionFine-tuning Large Language Models (LLMs) has become essential for domain adaptation, but its memory-intensive property exceeds the capabilities of most GPUs. To address this challenge and democratize LLM fine-tuning, we present SlideFormer, a novel system designed for single-GPU environments. Our innovations are: (1) A lightweight asynchronous engine that treats the GPU as a sliding window and overlaps GPU computation with CPU updates and multi-tier I/O. (2) A highly efficient heterogeneous memory management scheme significantly reduces peak memory usage. (3) Optimized Triton kernels to solve key bottlenecks and integrated advanced I/O. This collaborative design enables fine-tuning of the latest 123B+ models on a single RTX 4090, supporting up to 8× larger batch sizes and 6× larger models. In evaluations, SlideFormer achieves 1.40× to 6.27× higher throughput while roughly halving CPU/GPU memory usage compared to baselines, sustaining >95% peak performance on both NVIDIA and AMD GPUs.

People

Ruijia Yang

The Hong Kong University of Science and Technology (Guangzhou)

Zeyi Wen

Hong Kong University of Science and Technology (HKUST)

Work in Progress

An Energy-Efficient Automated Hardware Generator for Edge BCI Systems

6:42pm - 6:42pm PDT Monday, July 27 Exhibit Hall

DescriptionElectroencephalography (EEG) enables non-invasive monitoring of brain activity, but its high channel count and computationally intensive neural models pose major challenges to realizing energy-efficient edge accelerator hardware for real-time brain–computer interface (BCI) systems. This work presents EEGDeep, an energy-efficient and fully automated hardware generator that bridges neural network model development and deep-learning hardware accelerators for brain–computer interface (BCI) applications. The framework integrates three core modules: an EEG channel reduction module, which prunes non-informative channels to minimize model size and computational load, enabling practical deployment in wearable applications; an EEGDeep architecture evaluator, which performs constraint-aware neural architecture and hardware exploration through model optimization, a layer-reordering algorithm, and predefined deep-learning configurations to balance accuracy, area, latency, energy, and memory bandwidth; and an EEGDeep RTL generator, which converts optimized models into synthesizable RTL using a parameterized IP template. Using this automated framework, an EEGDeep design implemented in TSMC 90-nm CMOS technology achieves a 91.67% reduction in EEG channels, a processing latency of 1.43 ms per trial, and an energy consumption of 5.51 µJ per trial. These results correspond to a 65.9% reduction in area, a 98.49% improvement in latency, a 98.6% reduction in energy consumption, and a 93.19% improvement in memory bandwidth compared with conventional implementations, demonstrating its potential for practical, low-energy, and real-time BCI applications.

People

Research Manuscript

An Energy-Efficient Dataflow Architecture for Efficient MoE Model Inference

10:54am - 11:06am PDT Tuesday, July 28 Mtg Room 101A

AI4-II. AI/ML Architecture Design

DescriptionThe Mixture-of-Experts (MoE) model sparsely activates a subset of experts for each token, causing each expert to process a varying number of tokens during inference. However, existing GPU-based MoE inference frameworks adopt a fixed tensor size for the inputs to each expert, requiring padding when an expert receives fewer tokens, which leads to substantial redundant computation.
In response, we propose a token-stationary dataflow that uniformly abstracts the multiplication between an expert's parameters and input tensors with varying token counts. Based on this dataflow, we design a reconfigurable systolic array that eliminates padding-incurred redundant computation. Evaluation demonstrates that our design outperforms the state-of-the-art GPU-based MoE inference frameworks significantly.

People

Kexin Li

Qinggang Wang

Chuanhui Qi

Shaoxian Xu

Wenkan Huang

Xiangzheng Yang

Zhengzhou University

ruoshi li

Bo Liu

Zhengzhou University

Long Zheng

An Engineering Case Study of Autonomous AI PCB Layout Under Real Manufacturing and System Integration Constraints

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAn engineering case study examining the practical implications of autonomous PCB layout in a real hardware development workflow. The automation used in this study is domain-specific and constraint-driven, not an LLM. The case study system is a Linux-capable computer comprising a SOM and baseboard with over 800 components and more than 5,000 pins, designed under realistic electrical, manufacturing, and assembly constraints.

Starting from completed schematics and a defined board outline, the design progressed through automated layout generation, human review and cleanup, fabrication, assembly, and system bring-up using standard advanced manufacturing processes. The system booted Linux and ran real workloads on the first spin.

This outcome required non-trivial human correction of automated results. These intervention points illustrate why experienced PCB designers remain essential, particularly for identifying and correcting failures that are not locally observable prior to system integration and bring-up.

Rather than focusing on tools or algorithms, this talk analyzes what was required for success at each stage of the workflow, where automation was effective, where expert intervention remained necessary, and which assumptions did not hold in practice. It examines how autonomous layout reallocates expert effort—from manual routing toward constraint definition, review, and exception handling—within a broader trajectory of system design.

People

Darin ten Bruggencate

Quilter

Engineering Poster

An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Systems

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionMicrochip FPGAs feature multiple I/O banks, each configurable independently for diverse standards such as SSTL, LVSTL etc., enabling designers to mix and match signaling protocols across the same device while covering a wide frequency range. I/O banks support voltages from 0.5V to 3.3 V, including high-speed DDR PHY interfaces for LPDDR4/5 up to 3.2Gbps. Robust signal integrity across wide frequency-voltage spectrum is achieved through on die IO PVT calibration which dynamically compensates for variations in silicon process, supply voltage, temperature ensuring consistent electrical characteristics like output drive strength and termination impedance. A SAR-based digital block and analog block collaboratively manage reference currents and voltages resulting in complex mixed-signal system.

Verification of this subsystem is paramount to prevent chip-level failures. Full-chip verification challenges include multiple IO banks distributed across chip periphery and CPU-individual bank connections. Validating signal paths from CPU to farthest IO bank necessitates analyzing significant portion of the chip, leading to increased simulation runtime and memory usage.

This presentation covers PVT calibration architecture and verification strategies. It highlights how Siemens Symphony Pro optimizes debugging, reduces simulation time by ~3x, improves memory usage by ~2-3x, and streamlines regressions ensuring reliable calibration verification across diverse I/O standards and extreme PVT conditions.

People

Engineering Presentation

ANA-MODELGEN: Automating Analog IP Model Generation and Validation for Efficient Mixed-Signal Verification

11:00am - 11:15am PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionAnalog IP verification remains a bottleneck in modern mixed-signal SoC development due to lengthy SPICE simulation times and integration challenges. This paper introduces ANA-MODELGEN, a comprehensive hierarchical modeling methodology that transforms analog IP verification through automated model generation and validation. Our approach enables rapid development and validation of behavioral models for any analog IP type, featuring direct integration capabilities with industry-standard verification environments. The methodology includes automated testbench generation for rigorous model validation and equivalence checking against SPICE references. Deployment in production SoC verification flows demonstrates substantial gains in functional coverage and execution speed, enabling earlier bug detection and faster time-to-market.

People

Aadhar Sharma

Analog Intelligence: Physics-Aware AI for Faster, More Accurate Verification

Srijan Soni

Texas Instruments

Engineering Special Session

2:30pm - 3:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

DescriptionThis talk explores the intersection of physics-aware AI and electronic design automation, focusing on how modern neural network architectures can transform analog and mixed-signal verification. We review the evolution of neural networks—from convolutional models to attention-based transformers—and discuss why purely data-driven approaches fall short for engineering problems governed by differential equations. Physics-aware AI embeds domain constraints directly into learning architectures, enabling models that respect conservation laws, device behavior, and circuit dynamics. This approach gives rise to “analog intelligence”: AI systems that reason over continuous-time, multi-physics behavior rather than discrete abstractions. By accelerating core analysis tasks such as transient and frequency-domain verification, physics-aware AI can significantly reduce verification turnaround time, improve design confidence, and enable faster time-to-market with higher first-silicon success rates.

People

Bijan Kiani

Mach42

Research Special Session

Analog Quantum Simulation on Google’s Willow Processor

10:30am - 11:00am PDT Wednesday, July 29 Mtg Room 201A

EDA

DescriptionGoogle's quantum chips have been designed to be ideal for running digital quantum circuits, particularly for performing quantum error correction with the surface code. However, starting in 2024, we have demonstrated that these chips can also be repurposed to run extremely high-fidelity analog quantum simulations. Furthermore, the two capabilities can be combined, mixing digital gates with analog evolution. In this talk, I will discuss several recent experiments that leverage our hybrid analog-digital simulation platform, including adiabatic preparation of low-energy states both within the qubit subspace and incorporating higher energy levels beyond |0⟩ and |1⟩, as well as an analog counterpart to random circuit sampling.

People

Aaron Szasz

Analysis of Power Delivery Network (PDN) in 12-High HBM 3DIC for Heterogeneous Integration

Engineering Presentation

4:45pm - 5:00pm PDT Monday, July 27 Seaside Ballroom A

EDA

Systems

DescriptionAs high-speed, highly integrated systems-on-chip (SoCs) advance, the design of robust power delivery networks (PDNs) becomes critical to ensure reliable operation. In 3D-stacked high bandwidth memory (HBM), the vertical stacking of multiple core dies (Cdie) on a base die (Bdie) introduces significant challenges, including increased PDN impedance and cross-die current interactions, necessitating full-stack 3D-IC IR-drop analysis. However, conventional EMIR tools face scalability bottlenecks due to the massive transistor count and terabyte-scale input in HBM Bdie designs, often leading to excessive runtime or tool failure. This study presents a scalable methodology using Synopsys Totem-SC to enable full-chip 3D-IC EMIR analysis for HBM. We introduce a (1) the DSPF-only flow with parallel parsing, eliminate redundant processes, (2) cell‑based decoupling capacitor method that cuts transistor count in DSPF files by up to 70% and (3) current copy methodology. Further enhancements include (4) improve runtime (up to 78.3%) and capacity (up to 2 billion transistors), in parasitic/current extraction, GDS-to-DEF conversion, and partitioned database generation stage. Successful 3D-IC analysis reveals a 442% increase in maximum IR-drop device point (from 0.5 to 2.21) compared to single-die analysis, highlighting the necessity of full-stack simulation. The proposed method enables efficient, high-capacity EMIR analysis for next-generation 3D-IC designs.

People

Research Manuscript

Analytically-Derived Hybrid Net–pin Weighting for Timing-Driven Global Placement

4:42pm - 4:54pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionTiming-driven global placement is critical in modern VLSI physical design for achieving timing closure. Among existing approaches, weighting is a mainstream technique, but traditional weights are often manually designed based on heuristics, which can lead to suboptimal timing performance. To address this, we present an analytically-derived model of interconnect and cell-delay contributions of pin pairs along critical paths, from which we obtain explicit and differentiable formulations approximating Total Negative Slack (TNS) and Worst Negative Slack (WNS). The formulations include three wirelength components: net wirelength, linear pin-to-pin wirelength, and quadratic pin-to-pin wirelength, where net and linear pin-to-pin wirelength are smoothed via the weighted-average (WA) model. Based on these formulations, we derive a hybrid net-and-pin weighting scheme and propose a novel timing-driven global placement framework that directly optimizes TNS and WNS. The weighting scheme features dynamic and cumulative updates, ensuring that consistently critical paths are prioritized throughout optimization. Experimental results on the ICCAD'15 benchmark demonstrate that our method achieves average improvements of 39% in TNS and 6% in WNS compared with state-of-the-art timing-driven placers, while maintaining competitive wirelength and runtime, validating the effectiveness of the analytically-derived weighting framework.

People

Engineering Special Session

Applying AI to Transform Specification-Driven Development and Engineering Productivity

3:30pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionSandisk will present how a leading semiconductor company applies AI to transform specification-driven development and engineering productivity. The session will showcase practical workflows that improve specification quality, accelerate downstream documentation, and help engineers ramp faster on complex systems. Examples include using AI to detect ambiguities, inconsistencies, and missing requirements in specifications, while recommending fixes and useful extensions. We will also cover multimodal capabilities for analyzing existing diagrams and generating new visual content directly from specification inputs. The presentation will demonstrate an AI-powered knowledge assistant integrated into engineers’ daily development environment, enabling fast access to trusted design information. In addition, AI-generated outputs such as verification plans, coverage plans, sign-off documentation, and structured work-item breakdowns from high-level requirements will be shown. This talk highlights practical ways AI can modernize semiconductor engineering workflows today.

People

Mariana Shenker

Sandisk

Research Manuscript

AQR-HNSW: Accelerating Approximate Nearest Neighbor Search via Density-Aware Quantization and Multi-Stage Re-Ranking

2:47pm - 3:00pm PDT Wednesday, July 29 Mtg Room 101B

AI3-II. AI/ML Application and Infrastructure

DescriptionApproximate Nearest Neighbor (ANN) search has become fundamental to modern AI infrastructure, powering recommendation systems, search engines, and large language models across industry leaders from Google to OpenAI. Hierarchical Navigable Small World (HNSW) graphs have emerged as the dominant ANN algorithm, widely adopted in production systems due to their superior recall vs. latency balance. However, as vector databases scale to billions of embeddings, HNSW faces critical bottlenecks: memory consumption expands, distance computation overhead dominates query latency, and it suffers suboptimal performance on heterogeneous data distributions. This paper presents Adaptive Quantization and Rerank HNSW (AQR-HNSW), a novel framework that synergistically integrates three strategies to enhance HNSW's scalability. AQR-HNSW introduces (1) density-aware adaptive quantization, achieving 4× compression while preserving distance relationships; (2) multi-state re-ranking that reduces unnecessary computations by 35%; and (4) quantization-optimized SIMD implementations delivering 16-64 operations per cycle across architectures. Evaluation on standard benchmarks demonstrates 2.5-3.3× higher QPS than state-of-the-art HNSW implementations while maintaining 98%+ recall, with 75% memory reduction for the index graph and 5× faster index construction.

People

Ganap Tewary

Nrusinga Charan Gantayat

Jeff Zhang

ARC-SRAM: A Memory Subarray with Local Addressing and Reduced Access Energy

Research Manuscript

4:30pm - 4:42pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionConventional SRAMs are designed for random access, resulting in significant energy waste under regular access patterns common in image processing, computer vision, deep learning, and dense linear algebra to name a few. We propose an energy-efficient ARC-SRAM subarray architecture that integrates three synergetic energy reduction schemes: (1) Address decoding energy reduction by relocating the address generation to the memory periphery; (2) Read energy reduction by reducing wordline activity to one pulse per row and minimizing precharge activity to suppress half-selection energy; (3) Write energy reduction by reusing the bitline charge across consecutive rows, and by minimizing wordline activation.
We implement a 64KB instance of our ARC-SRAM using an advanced gate all around nanosheet 1.4 nm research process design kit. At the cell-array level, the design achieves a 63–76\% energy reduction for reads and 68–72\% for writes in loop-nest dominated applications, with only 4\% area overhead.

People

Ismail Bourhaeil

Geerten Verweij

Mahmood Naderan-Tahan

National Technical University of Athens

Francky Catthoor

Said Hamdioui

ARCHITECT LABS: Ada: A Self-Improving AI System for HW-SW co-Design and Verification

Exhibitor Forum

3:15pm - 3:45pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

DescriptionAI-agentic flows for chip design have emerged with the potential to create a paradigm shift in the EDA industry. At Architect Labs, we are building the first generation of AI-native design methodology for chip development. In this presentation, we share details on our AI-based automation flow for fast and verifiable generation of frontend design-collaterals, including architectural exploration, software-modeling, RTL, and verification. Our methodology enables capturing the design intent of the architecture based on design specifications, while the human-in-the-loop iterates on the specs as the “architect”. At the core of this methodology, an agentic harness combined with ML methods including reinforcement learning and test-time-scaling achieves fully end-to-end autonomous HW design and verification capability, all while using SOTA EDA tools and proven chip design methods. As a demonstration vehicle, we further present how
our AI system autonomously designed a specialized AI hardware accelerator targeting FPGA deployment for running inference on a SOTA LLM model. In this end-to-end demo, we share details on how our harness performs architectural exploration under memory vs. compute bound workloads to generate performance models, firmware, RTL, AI kernels, and more. We will bring the FPGA for an in-person demo, and share quantitative results on both the methodology and the design results, such as number of engineers, time-to-design, and achieved performance numbers.

People

Ekin Sumbul

Architect Labs

Engineering Presentation

Architectural Coverage Analysis and ML-Based Automated-Test Generation

11:30am - 11:45am PDT Monday, July 27 Seaside Ballroom A

EDA

DescriptionVerification coverage analysis evaluates the effectiveness of verification stimulus on design verification. Significant computational resources are spent toward coverage closure. Robust infrastructure and tools are available to analyze large coverage data to efficiently allocate resources to the most effective testcases. While we have correlation of testcases to coverage events they are likely to discover, little is known about why.

Further investigation into components that comprise the testcases, both from a stimulus-completeness and coverage correlation perspectives, is necessary. In this work, we augment coverage data with instrumentation to collect testcase components. Our analysis in the POWER simulation environment guided resolution of undesirable biases in stimulus generation and inefficient tests previously unknown. Furthermore, using ML and statistical techniques, we establish correlation between test components and coverage events, allowing composition of new testcases from components highly correlated with desired event scenarios. Coverage analysis shows these super-tests are most likely to achieve hard-to-hit scenarios and therefore make up 86% of recommended testcases. Increasing likelihood of such unlikely events and tuning environment inefficiencies lead to savings in computational resources in the verification environment.

People

Engineering Presentation

Architectural Formal Verification of Configurable Address Translation Logic for Early Bug Exposers

4:45pm - 5:00pm PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionHighly configurable, hash‑based address translation logic is central to modern memory subsystems, enabling scalability, parallelism, and load balancing(fairness) across multiple clients and lanes. However, the resulting configuration and address spaces grow far beyond what simulation can feasibly explore. Even subtle specification‑level errors in hashing or decoding semantics can silently propagate into RTL and system software, leading to persistent data corruption and costly late‑stage debug. This paper presents an architectural‑level formal verification methodology that shifts correctness assurance left, before RTL development. The intended hash and decoder behaviour is captured using an executable architectural reference model, independent of RTL implementation. Architectural intent is expressed as global invariants—such as no aliasing, load balancing(fairness), address safety, lane conflict avoidance, and controlled error propagation—and proven symbolically across all legal configurations and the full address space. The same reference model and proven invariants are then reused directly at the RTL level to perform invariant‑guided equivalence checking. By integrating these already verified block‑level properties as assumptions in the existing end‑to‑end RTL formal environment, system‑level correctness is validated without building a new formal setup or re‑verifying internal blocks. This approach uncovers mis‑integration bugs while avoiding over‑constraint. Applying this methodology exposed multiple critical specification bugs prior to RTL. The results demonstrate a scalable, reusable, and production‑ready formal flow for complex memory systems.

People

Research Manuscript

Are They All Safe? Practical Fault Injection Attacks on FPGA Logic Synthesis Tools

4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 202C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionFPGAs are widely deployed in critical systems, but flaws in EDA toolchains can enable malicious HDL injection, leading to severe hardware vulnerabilities. We propose DefVul-Risk, an automated framework for assessing fault-injection risks in FPGA synthesis tools. It constructs a defect knowledge base, generates triggerable vulnerability samples via large language models, and fine-tunes risk-assessment models to prioritize high-risk defects. DefVul-Risk enhances toolchain security evaluation and vulnerability remediation efficiency. We submitted 26 CVE reports, with 9 officially confirmed.

People

Jiaxin Li

Dalian Maritime University

Shikai Guo

Dalian Maritime University

Zhihao Xu

Dalian Maritime University

Qian Ma

Xiaochen Li

Dalian University of Technology

He Jiang

Dalian University of Technology

Research Manuscript

Area-Optimal and Routability-Driven Layout Synthesis for Multi-Row Complementary-FET Standard Cells

3:30pm - 3:42pm PDT Tuesday, July 28 Mtg Room 203AB

EDA

EDA7-II. Physical Design and Verification

DescriptionAs conventional FinFET architectures encounter severe scaling limitations, Complementary-FET (CFET) technology with vertically stacked PMOS and NMOS transistors has emerged as a promising solution for continued standard cell density scaling. However, aggressive area compaction in CFET standard cells drastically limits intra-cell routing resources, leading to routing congestion and design rule challenges. To mitigate this issue, multi-row CFET standard cell architectures have been introduced to improve intra-cell routability and alleviate block-level congestion. Nevertheless, these multi-row configurations introduce new placement-routing coupling and design rule complexities, making it challenging to achieve compact, DRC-clean, and routable layouts. Therefore, this work proposes an area-optimal and routability-driven layout synthesis framework for multi-row CFET cells, which effectively addresses the challenges of area efficiency, constrained pin accessibility, and DRC compliance under multi-row CFET architectures. Therefore, this work proposes an area-optimal and routability-driven layout synthesis framework for multi-row CFET cells, which effectively addresses the challenges of area efficiency, constrained pin accessibility, and DRC compliance under multi-row CFET architectures. and (3) a two-stage Satisfiability Modulo Theories (SMT)-based routing flow consisting of a Multi-Commodity Flow (MCF)-based routability-guaranteed pin-access selection and an Integer Linear Programming (ILP)-enhanced hierarchical routing to ensure DRC/LVS closure. Compared with state-of-the-art multi-row CFET cell generators, experimental results show that our algorithm consistently achieves the optimal layout area, while delivering significant improvements in solution quality and efficiency.

People

Research Manuscript

ARTEMIS: Adaptive RL Test-Time Ensemble for Model Inference in SSD Testing

3:54pm - 4:06pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionSolid-State Drives (SSDs) now power data centers, high-performance computing, and artifical intelligence workloads, but the increasing complexity of modern SSD controllers has surpassed the capabilities of traditional rule-based verification, necessitating scalable, data-driven testing methods. In this paper, we present ARTEMIS, a reinforcement‑learning (RL)‑based framework for automatic SSD test case (TC) generation that operates directly on commercial devices. Our contributions are threefold. First, we formulate a novel RL problem, enabling seamless deployment across heterogeneous commercial products without requiring any device-specific customization. Second, to cope with the highly dynamic and non‑stationary operating environments of SSDs, we introduce an ensemble‑based inference mechanism that aggregates policies learned under diverse workload distributions, thereby improving generalization and robustness. Third, we validate the approach on two representative stress‑testing tasks: Meta and User Garbage Collection. We show that the RL‑driven tester discovers high-impact TCs that trigger critical blocking garbage collection events more frequently than conventional methods in diverse tasks.

People

Engineering Poster

ARTEMIS: Agentic AI for EDA

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionFront-end RTL verification workflows consume significant compute resources and engineer time, with Verilog simulations often failing due to syntax errors, testbench issues, or configuration problems detected only after resource consumption. Traditional workflow management lacks predictive intelligence to prevent this waste.
This presentation introduces ARTEMIS (Automated RTL Testing & Error Management Intelligent System), a production-deployed multi-agent AI architecture that optimizes front-end verification workflows through intelligent error detection. ARTEMIS employs four specialized agents working collaboratively: Debug Agent (error identification), Supervisor Agent (resource orchestration), Scheduler Agent (regression test sequencing), and Job Analysis Agent (real-time monitoring). The system integrates with Verilog and industry-standard schedulers through Model Context Protocol servers.

The intelligent error detection system analyzes iverilog output patterns to identify syntax errors, module instantiation issues, and testbench problems before they consume compute resources. When failures are predicted, the system automatically terminates jobs and releases resources.
Production deployment metrics demonstrate 15-25% reduction in compute costs and 45% reduction in debugging time. This presentation chronicles the journey from award-winning prototype to production MLP with actionable implementation guidance for EDA workflows

People

Research Manuscript

ASG-MOENN: Adaptive Sparsely-Gated Mixture of Experts Neural Network for Digital Predistortion in Quadrature Switched-Capacitor Power Amplifiers

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionFor the first time, this paper introduces an adaptive sparsely-gated mixture of experts neural network (ASG-MOENN) as a novel digital predistortion (DPD) framework for wide dynamic power range quadrature switched-capacitor power amplifiers (SCPAs). State-of-the-art (SOTA) DPD models suffer from fixed, high computational complexity, leading to inefficiency at lower power levels. To overcome this limitation, the proposed ASG-MOENN employs a dual-stage adaptive mechanism. First, it embeds the underlying physical principles of SCPA power variation to condition the input signal. Second, it incorporates an adaptive sparse gating mechanism that dynamically determines both which experts to activate and how many are required based on a cumulative confidence criterion, allowing the model to flexibly scale its run-time complexity according to the PA's operating state. Experimental results demonstrate that, compared with the SOTA baseline, the proposed model achieves superior linearization performance while reducing the average computational load by up to 50% across a 30-dB dynamic power range.

People

Research Manuscript

Asymcheck: Asymmetric Partitioned Checkpointing for Efficient Large Language Model Training

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionDistributed large language model (LLM) training faces prevalent failures and requires efficient checkpointing. State-of-the-art approaches employ partition-based pipelined checkpointing, splitting checkpoints into partitions for concurrent processing. However, existing solutions rely on a fixed partition size, which our analysis reveals is suboptimal for LLM training: large partitions cause bandwidth stalls during forward passes, while small partitions incur substantial startup overhead during backward passes. We propose AsymCheck, which employs asymmetric partitioning: small partitions for forward passes and large partitions for backward passes, plus selective partition compression and batched flushing optimizations. Evaluation on 64 GPUs shows AsymCheck reduces training time by 20.1%-48.2% over state-of-the-art methods, approaching no-checkpointing efficiency.

People

Zhangqiang Ming

Yuchong Hu

Zhiyuan Luo

Patrick P. C. Lee

Innovation Research Institute of Cethik Group Co., Ltd.

Yuanhao Shu

Xinjue Zheng

Wenxiang Zhou

Dan Feng

Athena: Analytical Timing-Aware Pre-Silicon Estimation of Side-Channel Leakage

Research Manuscript

3:42pm - 3:54pm PDT Wednesday, July 29 Mtg Room 202C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionWe present Athena, a scalable analytical framework for pre-silicon side-channel leakage evaluation that avoids simulation entirely. Athena integrates static timing information with signal-probability propagation to model time-dependent circuit behavior, capturing leakage arising from input-arrival skew, glitches, and other timing-induced effects. The fine-grained leakage estimates produced, precisely identify vulnerable signals and time intervals, and supports evaluation of diverse countermeasures including masking, gate resizing, and differential logic. We evaluate Athena across a broad set of countermeasures on S-boxes and full ciphers, comparing both correctness and performance against state-of-the-art tools. Across all benchmarks, Athena delivers over 400x speedup over existing methods.

People

Janakiraman Viraraghavan

IIT Madras

Chester Rebeiro

IIT Madras

Research Manuscript

ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification

5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 202C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionThis work presents ATLAS, an LLM-driven framework that bridges standardized threat modeling and property-based formal verification for System-on-Chip (SoC) security. Starting from vulnerability knowledge bases such as Common Weakness Enumeration (CWE), the framework identifies SoC-specific assets, maps relevant weaknesses, and generates assertion-based security properties and JasperGold scripts for verification. By combining asset-centric analysis with standardized threat model templates, it automates the transformation from vulnerability reasoning to formal proof. Evaluated on three HACK@DAC benchmarks, ATLAS detected 39/48 CWEs and, out of that 39, ATLAS was able to generate correct properties for 33 of the bugs, advancing automated, knowledge-driven SoC security verification toward a secure-by-design paradigm.

People

Ishraq Tashdid

Kimia Tasnia

Alexander Garcia

Jonathan Valamehr

Sazadur Rahman

ATLAS: Asynchronous Topological Learning for Accurate FIT Prediction via Decoupled Graph Neural Networks

Research Manuscript

5:18pm - 5:30pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionSafety-critical integrated circuits targeting ISO 26262 ASIL-D require a failure-in-time (FIT) $<10$. These physics-based tools for FIT prediction, such as BFIT, are accurate but slow, while ML baselines suffer collapse under long-tailed FIT distributions. We propose \textbf{ATLAS}, a decoupled GNN framework that combines a bidirectional asynchronous topological message passing backbone, aligned with BFIT's forward and backward propagation, with RankNet and CalibNet synergistic heads. RankNet uses a gap-aware pairwise ranking loss with log-gap weighting $\Delta\log(t)$ and explicit emphasis on head samples to identify top-$k\%$ high-risk gates. CalibNet employs a dual-domain loss in log and linear spaces, incorporating importance weighting, for accurate calibration. The proposed design achieves $O(|V|+|E|)$ complexity, delivering up to 220$\times$ speedup over BFIT while reducing selective hardening area overhead by 53\% compared to DeepGate2 on ITC'99 benchmarks, thereby enabling the rapid reliability-aware design of large-scale circuits. We plan to open-source our data and model code after acceptance.

People

Yicheng Liu

Mingjun Wang

Songwei Pei

Yuntao Lu

Zizhen Liu

Institute of Computing Technology, Chinese Academy of Sciences

Boyu Han

Stanford University

Huawei Li

Shangguang Wang

ATOM-3D: Analytical Three-Dimensional Orientation-Aware Mixed-Size Placer

Research Manuscript

4:54pm - 5:06pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionIn this paper, we propose an analytical method for 3D mixed-size placement that incorporates macro-orientation awareness in face-to-face (F2F) terminal-bonded heterogeneous 3D ICs. This work introduces a novel one-pass placement framework that bypasses the conventional 2.5D co-optimization, effectively narrowing the gap between partitioning and placement and achieving significant time savings. Our method constructs a differentiable distributed macro-rotation system that unifies partitioning, placement, and macro-orientation within 3D global placement. To compensate for deviations arising from wirelength estimation in 3D placement, we further apply an FM-based post-partitioner. Experimental results on the ICCAD 2023 contest benchmark show that our approach achieves an 8% higher quality than the first-place contest entry and a 2% improvement against the best published method with 1.6× runtime speedup.

People

Yutao Wang

Liang Xiao

Bangqi Fu

Lixin Liu

Evangeline Young

Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment

Engineering Presentation

11:00am - 11:15am PDT Wednesday, July 29 Seaside Ballroom B

Design

EDA

Security

Systems

DescriptionThis work presents a pre-silicon side-channel leakage assessment of an open-source AES-XTS hardware implementation at the RTL level. The complete encryption flow is functionally verified, and switching activity is captured and converted into high-resolution waveform data for power reconstruction. A Test Vector Leakage Assessment (TVLA) and Correlation Power Analysis (CPA) are applied to identify statistically significant leakage across encryption cycles and the key byte disclosures. Results reveal dominant leakage during early intermediate datapath operations, motivating targeted security refinement. The study demonstrates the effectiveness of integrating vector-based power reconstruction with systematic leakage evaluation to expose vulnerabilities prior to fabrication, enabling cost-effective mitigation and improved hardware security robustness.

People

Harikrishnan Balagopal

Emrah Karagoz

Ferhat Yaman

Sourabh Goyal

Attackonctf: Defending Hardware Security Competition Benchmarks in the Age of LLMs

Research Manuscript

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionHardware security competitions such as HackTheSilicon serve as benchmarking platforms for evaluating vulnerability detection methods and training human and AI. However, our study reveals that LLMs threaten their validity. Instead of genuine security reasoning, detectors exploit a diff-style syntactic comparison, achieving an 83% detection rate, undermining fair evaluation. To mitigate this, we propose the first LLM-oriented, semantics-preserving obfuscation framework for these benchmarks. Unlike IP-protection approaches, it applies human-readable transformations and controlled diff-noise while preserving functionality. On HackTheSilicon, the framework reduces LLM-based detection accuracy by 50% with only 10% obfuscation and by 78.6% under complete obfuscation, restoring benchmark reliability.

People

Mohamadreza Rostami

Technical University of Darmstadt

Nikhilesh Singh

Technische Universität Darmstadt

Stephen Muttathil

Texas A&M University

Lichao Wu

Technical University of Darmstadt

Chen Chen

Texas A&M University

Huimin Li

Technical University of Darmstadt

Jeyavijayan Rajendran

Texas A&M University

Ahmad-Reza Sadeghi

Technische Universitaet Darmstadt

Research Manuscript

Attentioncap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction

1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionAs capacitance extraction accuracy of rule-based pattern matching becomes difficult to sustain at advanced nodes, a growing trend emerges to develop deep-learning-based 2D capacitance models. However, existing MLP- and CNN-based methods constrain their input to fixed metal-layer combinations in a specific process node, limiting their usability in practice. Recognizing the inherent similarity between capacitance matrix and the prevailing attention mechanism, we propose AttentionCap, a customized Transformer for capacitance matrix learning, with a Gram representation framework, a physics-aligned symmetric-attention output layer, and a novel normalized Laplacian loss. We also introduce a process-node embedding to enable multi-node learning. Trained on synthetic data, AttentionCap attains 0.67%/3.99% self/coupling-capacitance error on unseen real designs under a multi-layer and multi-node setting, surpassing the CNN-Cap baseline with 4.6x/5.7x lower self/coupling error and 192x faster inference speed. A pretrained AttentionCap accurately transfers to an unseen node with only 5K samples and 4K finetuning steps. With sufficient accuracy on unseen real designs and strong transferability to new process nodes, AttentionCap offers highly practical value for modern EDA workflows. Code and data are available at https://anonymous.4open.science/r/AttentionCap-release-F698.

People

Research Manuscript

Attestllm: Efficient Attestation Framework for Billion-Scale On-Device LLMs

1:30pm - 1:42pm PDT Wednesday, July 29 Mtg Room 202AB

Security

SEC1. AI/ML Security/Privacy

DescriptionThis paper presents AttestLLM, the first attestation framework to protect device vendors' hardware-level intellectual property by ensuring that only authorized large language models (LLMs) can execute on target platforms. To overcome the scalability and efficiency limitations of prior work, AttestLLM leverages an algorithm/software/hardware co-design approach to embed robust watermarks onto the activation of LLM layers. In addition, it optimizes the attestation protocol within the trusted execution environment, providing efficient ownership verification without compromising inference throughput. Evaluations on various on-device LLMs demonstrate AttestLLM's attestation reliability, fidelity preservation, and efficiency. Furthermore, AttestLLM exhibits resilience against forgery, replacement, and system attacks.

People

Ruisi Zhang

Yifei Zhao

Neusha Javidnia

Mengxin Zheng

Farinaz Koushanfar

ATTINA: Spatial Acceleration of Additive Number Theoretic Transform for Energy-Efficient zkSNARKs at the Edge

Research Manuscript

4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionModern zero-knowledge proof (ZKP) schemes are moving from costly elliptic curve-based systems towards algebraic proof systems. This transition is ushering in a new era of broad adoption of hardware-friendly ZKPs, implementable even on resource-constrained edge devices. Algebraic structures, such as towers of binary fields, are core components of such schemes, and they require hardware and algorithmic innovation to realize advanced ZKPs, such as Binius and Binius-FRI, efficiently.

Hence, this paper introduces the ATTINA framework, a high-throughput additive number theoretic transform (ANTT) accelerator operating over extended binary fields. ANTT is the most computationally intensive task for realizing Binius. ATTINA partitions ANTT tasks into multiple subtasks and strategically allocates them to processing elements (PEs) and hardware programmable logic (PL) kernels in an interleaved computing pattern. ATTINA features a scalable architecture that enables dynamic parameter changes for different cryptographic applications. To understand its applicability, this paper implements ATTINA on an edge-deployable heterogeneous Versal adaptive system-on-chip (ASoC) platform. ATTINA on Versal ASoC maintains a throughput of 10 Gb/s. ATTINA outperforms a benchmark CPU implementation of ANTT on a high-end processor (i9-14900K) by \textbf{139$\times$} and a PE-only implementation by \textbf{38$\times$} in terms of latency while operating at $\ leq$5W for a 4096-point ANTT. ATTINA's code is published at \url{https://anonymous.4open.science/r/ATTINA} for evaluation and reproducible research.

People

Yanze Wu

George Mason University

Devin Park

George Mason University

Md Tanvir Arafin

George Mason University

Work in Progress

Atto-Spinformer: An Energy-Efficient Magneto Electric Spin Orbit Logic-Based Compute-in-Memory Transformer Architecture

6:56pm - 6:56pm PDT Monday, July 27 Exhibit Hall

DescriptionTransformers form the foundation of modern natural language processing, but their performance is limited by GPU memory bandwidth and high energy consumption. In-memory computing (IMC) architectures mitigate data transfer overhead, yet remain constrained by power-hungry interfaces. We present a novel ultra-low-power Magneto-Electric Spin Orbit (MESO)-based IMC architecture optimized for dot product operation acceleration within transformers. By exploiting device non-volatility and a custom transmission-gate-based pulse application scheme, our design eliminates DACs at the CMOS-MESO interface and reduce interface power by 20.3x. We propose a custom computation scheme that significantly lowers the floating-point operations required by IMC architectures to compute outputs. Combined with the low-power MESO devices, these techniques enable our accelerator to boost computational efficiency by 4.4x relative to conventional IMC designs and 2.6x relative to the NVIDIA A100 GPU.

People

Hasita Veluri

Lawrence Berkeley National Laboratory

Dilip Vasudevan

Lawrence Berkeley National Laboratory

Engineering Presentation

Auto-Chk: Closing the Last-Mile Interpretation Gap in Digital Sign-off via a Neuro-Symbolic Compiler Framework

10:30am - 10:45am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionRecent RCA studies show that failures in digital sign-off rarely stem from EDA execution itself, but from the last-mile interpretation layer. Script-based automation, built on rigid syntax matching, breaks under tool/version drift and cannot enforce cross-stage causality, leading to silent misses. Human-centric checklists, introduced as a safety net, collapse under massive unstructured reports and schedule pressure, causing cognitive overload and false sign-off escapes.

We present Auto-Chk, a neuro-symbolic compiler framework that closes this interpretation gap. Instead of hard-coding scripts, Auto-Chk compiles natural-language verification intent into a deterministic intermediate representation, ItemSpec, which decouples intent from implementation. Generated checkers are stress-tested using adversarial, metamorphic validation without requiring golden data, and executed inside a secure sandbox with runtime monitoring. A cross-layer self-healing loop automatically adapts to log or tool changes. On top, an evidence-driven dashboard and role-based copilots transform raw logs into confidence-aware decisions and organizational knowledge.

Auto-Chk has been deployed at production scale, covering over 120 checklist items across multiple IPs, EDA tool versions, and process nodes. Results demonstrate a 20× reduction in checker development time, 100% semantic consistency, and sub-30-minute time to recovery, with full project convergence achieved within 15 hours. Outputs are delivered through a project-level dashboard and a role-based copilot, providing executable, resilient sign-off intelligence.

People

Wentao Dai

Auto-Formalization to Bridge Design Specifications Into Verifiable Hardware Logic

Exhibitor Forum

4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionAI can already help individual engineers write code faster, but generating the complex, interdependent artifacts that silicon design needs - like testbenches, reference models, checkers and RTL - requires intelligent harnesses and agent orchestration layers that understand how these artifacts relate and how they're validated.
Existing applications of AI for silicon design fall into two patterns: general-purpose coding agents that lack native understanding of silicon workflows, and LLM wrappers around legacy tool suites that reach baseline quality on isolated tasks but degrade as workflows chain across steps. Both generate artifacts in isolation, and each step can introduce errors that compound downstream. A holistic approach to generation requires continuous feedback among specifications, simulation results, downstream design metrics, and the engineers themselves.
Normal Computing addresses these limitations by building AI systems that learn from every artifact generated, every human edit, every simulation run, and every downstream signal about power, performance, and area. Generation and validation agents, trained on silicon engineering trajectories and simulation feedback, with native access to the toolchains, are the foundation. We treat continual learning as the architecture, and each interaction strengthens a shared knowledge base that grounds future generations in the design intent of the team, and the physics. Auto-formalization is one mechanism within this system, used to construct structured intermediate representations that keep complex artifacts coherent as they scale. Closing the loop with our own synthesis and analysis tools lets the system reason about quantitative design tradeoffs while it generates RTL and verification artifacts that are aware of the constraints they'll be measured against.
This talk presents the architecture behind these learning loops, benchmarks against general-purpose approaches on production-representative tasks, and results from deployments with top semiconductor partners globally

People

Johann George

Normal Computing

Engineering Poster

Automated 3Dblox File Generation: Enabling Extremely Rapid Solution Exploration by Streamlining Thermal and IR Analysis of 3D SOICs

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe rapid evolution of 3DIC stacking technologies has unlocked new opportunities for scaling and system technology co-optimization. However, these technologies also bring increased power density and thermal impedance while simultaneously expanding the design space. In this environment, the consequences of early architectural decisions are magnified, the information available to make them is sparce, and speed is of the essence.

We present an automated 3Dblox-based solution that streamlines the generation and evaluation of multi-die architectures, enabling architects to rapidly prototype, analyze, and optimize complex 3D Multi-Chip Modules for thermal and IR performance. Our work builds upon an existing GUI-driven prototyping system which supports flexible floor planning and power density specifications without requiring RTL or netlist data. Here we integrate the generation of industry standard 3dbv, 3dbx, and 3dbf files for analysis with EDA tools.

By leveraging a combined internal and EDA tool flow, we reduce simulation turnaround time for thermal and IR feasibility from days to minutes. This approach identifies thermal and IR hotspots, facilitating better-informed design decisions early in the process. We demonstrate a scalable and practical methodology for early-stage 3DIC design, shifting critical analysis left in the development cycle and enabling broader, more rigorous exploration of next-generation system architectures.

People

Late Breaking Results

Automated Design of Device Fingerprinting Circuits for FPGAs

5:09pm - 5:12pm PDT Monday, July 27 Exhibit Hall

DescriptionDesigning device fingerprinting circuits for FPGAs is challenging due to limited knowledge about device layout and manufacturinginduced biases, often resulting in poor uniqueness and biased responses. Existing mitigation techniques are typically device-specific, time-consuming, and difficult to generalize. We propose an automated EDA tool, that analyses the target FPGA to optimize circuit layout to maximise extracted entropy and mitigate systematic bias.
Across 100-device testbed, the tool outperformed comparable manual designs, achieving near-ideal uniqueness and bias. These results demonstrate that automated device-aware design can reliably estimate and approach the best achievable performance on a given
FPGA.

People

James Moore

Queen's University Belfast

Maire O'Neill

Queen's University Belfast

CHONGYAN GU

Queen's University Belfast

Research Manuscript

Automated Discovery, Classification, and Systematic Security Verification Methodology for Undocumented Instructions

11:23am - 11:36am PDT Tuesday, July 28 Mtg Room 203C

Security

SEC3-II. Hardware Security: Attack and Defense

DescriptionUndocumented instructions pose a growing security threat, yet current research is limited.
Existing work focuses on discovery with constrained techniques, while semantic analysis is manual and ad-hoc. Moreover, a significant gap exists in methodologies for systematic security verification. This paper presents a comprehensive framework for the automated discovery, systematic classification, and security verification of undocumented instructions. Our evaluation discovered 23 new instructions and classified 29 using a classifier with 99.8357% accuracy. Most importantly, we verified that 5 instructions have tangible security implications, demonstrating our approach's efficacy in addressing threats at the processor instruction level.

People

Yooseok Lee

Kangwon National University

Junho Jo

Kangwon National University

Hanjoon Kim

Furiosa AI

Wonjun Song

Kangwon National University

Engineering Presentation

Automated System for FPGA-Based SoC Prototyping

2:15pm - 2:30pm PDT Wednesday, July 29 Seaside Ballroom A

EDA

Systems

DescriptionDesigning System-on-Chips (SoCs) requires a well-organized development process. Pre-silicon validation/verification plays a crucial role; it can be performed in various ways. Here, simulation and prototyping are addressed. This presentation focuses on digital devices. Therefore, FPGA-based prototyping fits perfectly. SoC development requires significant time for RTL coding and IP integration. The design evolves daily. Continuous simulations are launched, and prototyping must keep pace. Hence, constant realignment between the two environments is necessary. The FPGA scenario differs slightly from the simulation one: some blocks must be replaced (memories, PLLs and others) when switching from one domain to another. This replacement essentially involves managing and modifying lists of source code files (Verilog, SystemVerilog and VHDL) used for simulation and FPGA synthesis. Given the complexity of modern designs, manual handling could lead to human mistakes. This presentation describes a system, based on Python scripts, for the automatic transition from simulation to prototyping (and back).

People

Engineering Presentation

Automated Validation of Liberty Models

2:45pm - 3:00pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

DescriptionSignoff-quality standard cell libraries are critical for successful SoC tape-outs. Even minor inaccuracies in Liberty (.lib) models can lead to late-stage failures in timing, power, IR drop, and noise analysis. Manual QA of Liberty files are error-prone due to their complexity, especially with statistical LVF and CCS waveform data for advanced nodes.

Traditional validation methods are slow, resource-intensive, and often miss subtle inconsistencies. The need for a scalable, automated, and SPICE-accurate validation framework was driven by:
• Increasing complexity of Liberty views
• Growing number of PVT corners and cells
• Demand for early detection of outliers to reduce debug cycles

We present an automated validation framework methodology covering
• Moments-based LVF validation: Reduces false positives from traditional sigma checks.
• STA-like LVF comparison: Uses effective delay/transition metrics for realistic analysis.
• Automated SPICE setup: Supports all arcs, slew/load conditions, and parasitic.
• Insight-driven debug: Visual trend plots accelerate root cause analysis.

Applied to over 1000 cells across 30+ PVT corners, the methodology enables early outlier detection, improves SPICE level correlation, and delivers up to 2× productivity gains in validation and revision analysis. The results demonstrate a scalable approach to achieving consistent, signoff ready Liberty libraries with reduced silicon risk.

People

Merin Meyn

Gaurav Dhawan

Automated Verification and Performance Analysis for Chiplets

Engineering Presentation

10:45am - 11:00am PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionChiplets allow flexibility of design, enabling higher yields and faster turnaround times compared to monolithic SoCs. As part of creating the Cadence chiplet development solution, various areas for automation were identified to speed up the emulation and performance processes, thereby reducing the time required to bring chiplet designs to market.

Provision of emulation platforms early in the design cycle allow real hardware to be used by stakeholders such as system architects and software developers, allowing them to kick-off their activities significantly earlier, and reducing inter-team dependencies by creating a cohesive flow between all departments.

The verification flow uses outputs from design automation to generate the simulation & emulation platforms, the verification environment and tests. Tests are written using the Accellera Portable Test and Stimulus Standard (PSS) to allow C code to be generated for different target platforms, reducing duplication and saving effort and time.

The flow further generates the performance testing suite allowing metrics to be automatically retrieved between any defined source and end point using the Cadence System Performance Analyser. Availability of performance metrics early in the design cycle results in earlier design closure, reducing late architectural changes and increasing confidence in functionality and performance.

People

Joshua Lam

Batu Bayram

Automated Workload Analysis for Dynamic Voltage Drop Optimization and Faster Power Integrity Signoff in Complex SoC Designs

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAs power integrity margins continue to tighten in advanced nodes and 3DIC designs, identifying the true worst-case PDN stress scenarios across multiple compute tiles has become increasingly complex and time-consuming. Traditional manual exploration of block workloads and vector combinations often requires expert intervention, exhaustive simulations, and significant runtime. To address this challenge, we present an automated RedHawk-SC framework that intelligently explores Reduced Order Models(ROM)-based block workload combinations to uncover high-stress PDN conditions with minimal runtime overhead.

The proposed flow introduces a novel scenario optimization algorithm that automatically generates, ranks, and prunes workload mixes for each compute tile, capturing die-package co-analysis through integrated RedHawk-SC simulations. The framework incorporates workload intelligence to learn per-block power impact, adaptive optimization to select optimal workload pairings using a greedy exploration algorithm, and scalability across multiple domains and workload vectors. Implemented as a Python wrapper, it delivers a plug-and-play architecture supporting automation and rapid integration within existing analysis environments.

This automated flow replaces expert-driven manual analysis with a data-guided methodology that ensures accurate prediction of voltage stress regions, early detection of grid vulnerabilities, and stronger silicon correlation. The approach simplifies scenario complexity, enhances reliability coverage, and accelerates sign-off for chiplet and 3DIC architectures.

People

Mohammed Yousuff Shariff

ARM

Engineering Poster

Automatic SDC Creation for Static Timing Analysis

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionTiming constraints are written to specify the design intent. SDC constraints are needed to properly: specify clocks in a design, instantiate on the correct pins/ports, compute uncertainty for clocks, and assert behavior/interaction of clocks in a design.

Timing constraints are typically manually written by the designer. The work can be tedious, time-consuming, prone to missing an interaction, or prone to calculation errors – leading to lengthy iterations, and the risk of hardware fails or excessive power.

We present a novel tool, ClockACE, to automatically create and apply all necessary timing constraints.
This saves significant amount of work for the designer. This prevents human error in computation or missing constraints. Any change to a clock spec is automatically re-computed within the timing run.
In this paper we present ClockACE for automatic constraint generation. We highlight a specific example using generated clocks, and the challenges with implementation of this clocking paradigm. We show how ClockACE handles this scenario automatically.

People

Engineering Presentation

Automating DFT Intelligence: Addressing TCPF Hotspots at Source Through Design Aware Test Points in Systemrdl-to-RTL Generators

11:15am - 11:30am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionAs SoC complexity scales, the resulting explosion in Automatic Test Pattern Generation (ATPG) pattern counts has become a primary driver of escalating manufacturing test costs. A critical bottleneck in this process is the emergence of "TCPF (Test cost Per Fault) Hotspots" across designs such as highly complex, auto-generated blocks such as Control and Status Registers (CSRs) that exhibit disproportionately high pattern counts due to deep combinational logic and structural bottlenecks like shared address buses. Traditional structural test point insertion often fails to address these architectural constraints effectively, as it operates on a late-stage netlist without design-specific context.

This paper proposes an "Extreme Left-Shift" methodology that moves DFT intelligence directly into the specification-to-RTL generation phase. By integrating Design-Aware Test Points (DATP) natively within a SystemRDL-to-RTL generator, we introduce architectural enhancements—including address parallelism, local protocol control, and optimized OR-reduction logic—that are structurally impossible to implement efficiently at the netlist level. This automated approach utilizes intelligent algorithms to analyze input RDL specifications and fine-tune DATP parameters at scale.

We demonstrate the efficacy of this methodology on a production-grade Tensor SoC. Experimental results show that while maintaining a minimal area overhead (~0.1%), the proposed DATP solution achieves a 4x improvement in TCPF at the IP level and a 50% overall reduction in ATPG pattern count at the top level compared to reference designs. By solving DFT bottlenecks at the source, this scalable framework provides a robust path for significantly reducing SoC test costs across the industry

People

Engineering Poster

Automotive Logic Test Power Management

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionTest coverage, test time, and test power are tradeoff on automotive system logic test. Unlike test coverage and test time, power is critical factor which is hard to be predicted and evaluated when implementation. Logic test usually has large amount of registers toggled at the same time and results in scan shift IR drop which might fail the test. Reducing pattern toggle would result in longer test time. Time consuming iterations for months are required to validate and fine tune scan structure with lower peak current until IR analysis is completed
Automotive System Logic Test Power management includes two parts: Pseudo-CPM Analyzer for test current prediction, and ASKA + POWA for shift power reduction. It helps user to fine tune design during design phase and IR drops reduce 3.2% with add-on clock skew on real product. The product also met design spec on logic test's coverage/test time/power and got silicon proven.

People

Research Manuscript

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 101A

AI2-I. AI/ML Algorithms and Models

DescriptionThis paper presents the first self-evolved logic synthesis framework, which leverages Large Language Models (LLMs) in a multi-agent setup to autonomously improve the source code of ABC. Our approach builds upon recent work in LLM-driven code evolution and extends the idea to the substantially more complex monolithic ABC codebase. We bootstrap the process with established human-designed optimizations and external research code. And in each iteration, the agents propose and implement code modifications which are then validated for correctness and evaluated on standard benchmark circuits to provide quality-of-result (QoR) feedback. Over time, the framework organically discovers improvements beyond the initial heuristics and complete the coding evolution autonomously in the whole ABC repository, effectively learning-to-progress better synthesis tool.

People

Cunxi Yu

University of Maryland/NVIDIA

Haoxing Ren

Autonomously Handling of Digital Blocks From Initial Concept to Timing Constraints

Exhibitor Forum

4:00pm - 5:00pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionHu-mind.ai VLSI Teammate autonomously handles the full design cycle of a digital block, from initial concept to timing constraints. The Teammate execute these key phases: (1) Architecture: Transforming definitions into formal architecture documents. (2) RTL Design: Generating high-quality RTL code from architectural specs. (3) Test Planning: Drafting comprehensive test plans for robust verification. (4) Verification: Building SystemVerilog environments and test cases based on the test plan. (5) Debug: Running simulations and resolving design issues. (5) Timing: Composing SDC (Synopsys Design Constraints) for synthesis. Whether you're an RTL designer, a verification lead, or a physical design engineer, this shows how the VLSI Teammate augments your workflow to hit tape-out faster. With VLSI Teammates, every engineer steps into the role of a team leader. Communication with your virtual team is facilitated through a command-line interface, a web interface, or via your preferred instant messaging application on any device.

People

Gadi Laufer

Hu-mind

Research Manuscript

B-Flex: Exploration of Broader Flip-Flop Design Space Based on FSM Exhaustive Search

12:03pm - 12:16pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionFlip-flops (FFs) are a critical component affecting system-level power, performance, and area (PPA). Many logic-based FF design methods have been introduced to expand the scope of topology exploration beyond intuition. However, their exploration scope is still limited to 2-bit finite state machines (FSMs) because of inefficient search space representation. We present B-Flex, an automated FF FSM search that integrates a complete, graph-based behavioral equivalence check into a pruning-based generative search. This efficient and scalable approach vastly expands the design space and allows exhaustive exploration of 3-bit-state FSMs. B-Flex has identified over 568 million valid FF mechanisms, including many novel 3-bit-state FF designs. Topology synthesis on 20 sampled FSMs has produced several high-performance FF circuits that outperforms conventional FFs. For instance, FF1, achieves a 2.53× speedup over a transmission-gate FF (TGFF) and improved metastability window at 0.9 V.

People

Hyunsung Jeong

UNIST

Kyounghun Kang

Korea Advanced Institute of Science and Technology (KAIST)

Wanyeong Jung

KAIST

Jongeun Lee

Ulsan National Institute of Science and Technology (UNIST)

Research Manuscript

Beyond Exact: Tight WCET Analysis of GPU Kernels with Branch Divergence

11:50am - 12:03pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS6. Time-Critical and Fault-Tolerant System Design

DescriptionThe increasing adoption of GPUs in real-time systems necessitates precise timing analysis for GPU thread blocks to ensure overall system predictability. However, the uncertainties of branch executions within GPU warps impose significant barriers for predicting the worst-case execution time (WCET) of the thread block. Existing WCET analysis for thread blocks typically assumes deterministic warp execution paths, which is unrealistic given the dynamic control flows of threads within the warps. Moreover, as the warp scheduler operates as a black box, the analysis must rely on relaxed scheduling assumptions, resulting in overly-pessimistic bounds in order to cover edge scenarios. This paper first establishes the need for static analysis by showing how branch divergence can trigger timing anomalies and influence block WCETs. We then develop an exact WCET analysis for a GPU thread block under the same scheduling constraints as prior work while not imposing any warp execution path assumptions. Furthermore, by enforcing a practical constraint on warp executions, we present a tighter analysis that enhances system predictability. Experiments show that the proposed analysis under warp execution constraints significantly reduces the WCET estimations of GPU thread blocks (by 19.13% on average and up to 39.39%).

People

Shuai Zhao

Chen Jie

Yaowei Liang

Mingyue Cui

Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

Research Manuscript

10:43am - 10:56am PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionCircuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness. Our code is avaiable at https://anonymous.4open.science/r/DeepSeq3-6760

People

Jingyi Zhou

Zhengyuan Shi

Jiaying Zhu

Ziyang Zheng

Qiang Xu

Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination

Research Manuscript

3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionDespite recent progress, every CPU fuzzer explores only a narrow slice of the vast micro-architectural state space due to its fixed mutation and feedback biases. While different fuzzers thus excel in disjoint regions, naïve combination fails because of conflicting strategies, seed pollution, and early saturation.
LiFU introduces micro-architecture-aware orchestration that dynamically profiles heterogeneous fuzzers, detects complementary strengths, decreases harmful interactions, and steers each fuzzer in real time using coverage and bug feedback, augmented by semantic seed triage.
Evaluated on the BOOM core, LiFU achieves 93.4% line, 43.6% FSM, and 95.7% condition coverage (90.1%, 75.0%, 78.3% on Rocket) with around 40% fewer tests than the best standalone fuzzer, consistently closing long-standing verification gaps in modern CPU.

People

Ning Wang

Zhe Jiang

Beyond Hierarchical Static Verification: Smart Stubbing for Next-Gen AI Accelerators

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern AI accelerators, such as Meta's MTIA, rely on massive arrays of Processing Elements (PEs) to maximize compute density. This architecture creates a design structure known as MIMs (Multiple Instantiated Modules). While these repetitive structures are essential for physical design optimization, they create a verification nightmare when doing flat analysis. Most modern flows rely on hierarchical verification using abstract models of smaller blocks at top level. However, in massive AI chips even this approach falls short due to the sheer volume of redundant Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) checks generated when large subsystems are instantiated repeatedly, causing chip-level flow runtimes to become unmanageable.

This paper presents a static verification methodology designed to overcome these scalability challenges in reticle-limit AI chips. While standard hierarchical flows utilizing Block Abstract Models attempt to manage complexity, the physical repetition of MIMs results in top analysis runs exceeds 26 hours and consuming up to 12x more memory due to redundant reporting.

To address this, we propose an RTL-based "stubbing" technique that selectively isolates unique instances of large blocks, such as Processing Elements, while neutralizing redundant copies via parameterized RTL defines. By shifting signoff to the block level and reducing the scope of top-level analysis, this methodology reduces the number of flat instances from 14.4 billion to 1.1 billion. Consequently, this approach eliminates redundant crossings, slashing verification runtime by 90% (down to 3.5 hours) and significantly reducing storage requirements, thereby enabling faster design convergence and feedback loops

People

Engineering Poster

Beyond Scripting: API Based HDL Generation

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionLooking at the block diagram of any modern SoC – whether a standalone device or a chiplet – and you will see that most of the blocks, and die area, consists of generated logic. From regular structures like RAMs and ROMs, to semi-regular structures like control/status register and NoCs, to entire processors, the HDL source and other input files for these blocks is produced by tooling from a higher-level specification, not typed by designers or output by AI. My work revolves around raising the level of abstraction used when writing HDL generators beyond scripts that output text. I propose that generators should not generate HDL text directly as with a "script", rather generators should be written with an API to assemble the HDL for output. This assures that the generator can only output syntactically valid HDL, and that errors are reported in the context of user input. This is especially important when an HDL generator is product, where failures and poor error reporting result in higher support costs for vendors, and poor outcomes for customers.

People

Jack Greenbaum

INTEGRITY Security Services

Work in Progress

Beyond Static Policies: Dynamic-PRAC for Balanced and Efficient Rowhammer Mitigation

6:46pm - 6:47pm PDT Monday, July 27 Exhibit Hall

DescriptionRowhammer attacks repeatedly activate DRAM rows and cause bit flips in adjacent rows. DDR5 introduced Per-Row Activation Counting (PRAC) to address this, but static thresholds and unnecessary distant-row refreshes limit its efficiency. This paper proposes Dynamic-PRAC, which adapts mitigation thresholds based on service-queue utilization and refines refresh actions by row distance. Experiments show that Dynamic-PRAC improves performance over PRAC, MOAT, and QPRAC while lowering overhead. Security results further demonstrate the lowest unmitigated activation count and up to 73% reduced energy use, offering an efficient and balanced Rowhammer mitigation mechanism.

People

POSTECH (Pohang University of Science and Technology)

Jinkyu Jeong

Yonsei University

Research Manuscript

BiBNN: 88.6% Computation Reduction in Bayesian Neural Networks via Post-Training Bernoullization

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionDeep neural networks tend to make overconfident predictions on unseen data, potentially raising risk in safety critical domains. Bayesian neural networks (BayesNNs) can estimate the uncertainty of prediction results, by modeling the uncertainty of model weights. However, BayesNNs have expensive
computing costs due to repeated sampling while evaluating uncertainty, which makes them inapplicable in practice. This work proposes a binarization framework for BayesNN, named Binarized Bayesian Neural Network (BiBNN), thus unlocking the potential for applications on embedded devices. We train real latent weight with Gaussian prior distribution by Variational Inference and use binary weight with Bernoulli distribution to perform inference. Experiment results show that the BiBNN retains similar uncertainty evaluation capability but with only 11.4% computing cost when compared to BayesNN. And BiBNN outperforms binary neural network by 1.5% on the CIFAR-10 dataset in terms of inference accuracy.

People

Research Manuscript

Bident: Optical Logic Synthesis via Optimal Configuration of Binary-Combiner Trees

5:03pm - 5:16pm PDT Tuesday, July 28 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionDespite decades of success, CMOS technology is increasingly constrained by power dissipation and propagation delay, thus motivating the exploration of photonic integrated circuits as an alternative for high-speed, energy-efficient computing. However, existing optical logic synthesis frameworks rely on an oversimplified efficiency factor model that fails to accurately capture physical attenuation and the hierarchical nature of signal degradation. This work presents Bident, a comprehensive optical logic synthesis framework that provides a physically accurate loss model and achieves optimal combiner configuration. We introduce the binary aggregate model, which explicitly reflects the binary-tree topology and input ordering in multi-input combiners. Based on this model, the Huffman tree optimization guarantees optimal Y-branch combiner configuration without requiring additional hardware resources. Meanwhile, a greedy algorithm optimally employs directional couplers at the leaf layer of a binarycombiner tree to achieve harmonic-mean efficiency at minimal hardware cost. Experimental results demonstrate that Bident achieves superior signal-attenuation reduction and lower switch cost than state-of-the-art methods, using both the conventional efficiency factor model and our binary aggregate model. A schematic-level optical circuit simulation further validates the feasibility and effectiveness of our binary-combiner configurations.

People

Jun-Wei Liang

Iris Hui-Ru Jiang

Kai-Hsiang Chiu

BIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Reasoning for RTL Synthesis and Summarization

Engineering Presentation

11:00am - 11:15am PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionAutomating Register-Transfer Level (RTL) code generation and summarization is critical for improving hardware design productivity and reducing time-to-market. However, existing approaches struggle due to limited Verilog and VHDL training data and the structural concurrency inherent in hardware description languages (HDLs). We propose BiMem-RAG, a dual-memory retrieval and bidirectional reasoning framework for HDL synthesis and documentation. BiMem-RAG combines (i) an exemplar memory of specification-to-code and code-to-summary pairs indexed using joint code and abstract syntax tree embeddings, and (ii) an analogical memory capturing reusable hardware design patterns such as sequential and combinational logic. The system employs modular decomposition, reinforcement-guided retrieval, and backward verification to improve semantic fidelity and reduce hallucinations. Experiments on Verilog and VHDL benchmarks demonstrate up to 19 percentage-point improvements in Pass@1 and 9-point gains in ROUGE-L over strong baselines. These results show that structured retrieval and verification significantly improve RTL generation and summarization, enabling more reliable hardware design automation.

People

Prashanth Vijayaraghavan

Research Manuscript

BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis

3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionIn advanced packages, large power/ground (P/G) planes are essential for power integrity but prone to warpage. While a uniform metal-density constraint combats warpage, mandatory degassing holes complicate adherence and degrade IR-drop. We propose BLADE, the first P/G plane synthesis methodology that enforces this constraint while optimizing power integrity. BLADE expands P/G planes from skeletons under metal density control to ensure connectivity, naturally leaving holes for degassing. Guided by a fast IR-drop evaluator, our bi-level Bayesian optimization framework efficiently navigates the design space. Experiments on six SiP cases demonstrate that BLADE satisfies the metal-density constraint and achieves superior IR-drop performance.

People

Siyuan Liang

Shanyi Li

Leilei Jin

Yuan Pu

Technical University of Munich

Yushen Zhang

Zhen Zhuang

Technical University of Munich

Kai-Yuan Chao

Siemens

Ulf Schlichtmann

Tsung-Yi Ho

Boosting IP Quality and Productivity Through Ipdelta Profile-Driven Change Detection

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAbstract:
Incremental changes are common during IP delivery, with approximately half of IP releases involving limited updates such as view additions, PVT updates, cell fixes, or layout modifications. While expected, these changes significantly complicate IP qualification, as conventional version-to-version validation often produces excessive false positives, increasing debug effort and slowing delivery cycles. Efficiently distinguishing intended modifications from unintended regressions is therefore critical to maintaining IP quality at scale.

This paper presents a profile-driven IP validation framework deployed at STMicroelectronics using Solido IPDelta and integrated within the internal IP QA infrastructure. The approach introduces predefined validation profiles that explicitly model expected changes between IP versions, such as layout-only updates, layout-plus-abstract changes, netlist updates, or liberty model revisions. By waiving known, intentional differences through profile definitions, the framework isolates unexpected inconsistencies for focused analysis across CAD views including GDS, OA, LEF, DEF, netlists, and liberty formats.

Applied across diverse IP types and technology nodes, the profile-based methodology significantly reduces validation noise and improves debugging efficiency. Measured results demonstrate up to a 60% reduction in manual QA effort per IP delivery, while provide a scalable and consistent validation solution for evolving IP ecosystems. This work shows that profile-driven change detection enables robust, efficient IP qualification in incremental delivery environments.

People

Research Manuscript

Brain-Like Hyper-Dimensional Graph Learning System with Hardware-Efficient Adaptive Sparsity

1:30pm - 1:42pm PDT Monday, July 27 Mtg Room 203AB

Design

DES3. Emerging Models of Computation

DescriptionGraph neural networks (GNNs) are crucial for numerous applications, yet their huge computational demands often lead to suboptimal performance.
Hyper-Dimensional Computing (HDC) is a brain-inspired learning approach for efficient and robust learning.
HDC-based Graph Learning (HDGL) shows significant improved computational efficiency and accuracy by learning graph representations in a high-dimensional space. Despite these advantages, general-purpose computing platforms such as CPUs and GPUs are insufficient for efficiently handling HDGL tasks.
In this paper we propose an accelerator called HDGAS through algorithm and hardware co-design for HDGL.
Based on the insight that not all node features in a graph are equally important, we propose to jointly optimize a lightweight filter with the HDGL model to dynamically identify and eliminate less significant node features during runtime.
Moreover, we design a specialized system architecture for end-to-end HDGL acceleration, harnessing the proposed dynamic sparsification technique in tandem with the inherent SpMM operations within HDGL.
Extensive experiments demonstrate that HDGAS achieves $6.76\times$ ($69.31\times$) speedup and $7.58\times$ ($80.12\times$) energy-efficiency improvements over GNN accelerators (GPU).

People

Haomin Li

Fangxin Liu

Zongwu Wang

Shiyuan Huang

Shanghai University

Ning Yang

Chenyang Guan

United Imaging Intelligence Co., Ltd.

Tao Yang

Huawei

Xinran Liang

Haibing Guan

Breaking Sequential Depth Barriers: An FSM-Driven Bridge for the Formal Verification of Virtually Address-Mapped Hardware Registers

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis paper presents the formal verification of a subsystem with indirect read mechanisms and a nonstandard access protocol. Verifying registers using the control and status register (CSR) protocol typically requires a proof accelerator to convert a standard bus into the CSR protocol. However, this secure design uses a custom protocol, creating unique formal verification challenges. In this design, writing to an IP register through the subsystem is straightforward and followed by polling a status register to check the write data status. The read data is available at a different address within the subsystem register map.
To address this, a protocol-to-protocol AMBA bridge is developed. The bridge converts write commands from the verification intellectual property (VIP) into writes for the device under test (DUT) and reads data from the DUT, returning it to the corresponding VIP address. Because the DUT does not return data at the same address, address conversion logic with several finite state machines (FSMs) is implemented. This approach allows the VIP to perform checks as expected, despite the indirect read mechanism.
Counter value abstraction is used to manage delays and simplify verification, ensuring efficient completion. This approach enables robust and efficient register verification for complex subsystems and saves significant time compared with the UVM register model.

People

Erik Seligman

Breaking the EDA Bottleneck for Agentic Chip Design

Exhibitor Forum

4:00pm - 5:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionOboe is accelerating the future of silicon development with next-generation Emulation and Waveform platforms purpose-built to unlock true agentic chip design. While AI has yielded remarkable productivity gains in software, hardware engineering lags behind as agents are severely bottlenecked by legacy EDA infrastructure. During frontend verification, both human engineers and autonomous agents waste critical time waiting for traditional simulation engines to return results, stalling the iterative loop and limiting agentic effectiveness. As agents drop the cost of forming hypotheses and generating tests, the burden of data generation, evaluation, and retrieval only become more acute. In this presentation, we discuss Oboe’s solutions for accelerating simulation, bringing the digital verification workflow to the speed of agents and ultimately enabling rapid and accurate root cause analysis.

People

Jonathan Birjiniuk

Oboe

Engineering Poster

Breaking the O(N^2) Barrier: AI-Assisted Linear-Time Formal Verification of Deep Pipeline Buffers

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAchieving full formal sign-off for deep hardware tracking structures—critical components in high-bandwidth networking and AI accelerators—often stalls against a 'Complexity Wall' as pipeline depths increase. Standard Bounded Model Checking (BMC) requires sequential unrolling proportional to latency, leading to an exponential state-space explosion that typically renders proofs inconclusive beyond 32-stages. For an N-stage buffer with W-bit identifiers, the total unrolled state complexity grows by O(N^2×W), quadrupling the verification effort with every depth doubling.

This paper introduces a scalable formal verification methodology that shifts the verification paradigm from deep sequential searching to single-cycle inductive transitions, effectively achieving linear scalability (O(N×W)) . Approach uses LLM-driven "Impact Grading" framework that automates the discovery of high-impact inductive invariants. By categorizing candidate properties into a tiered hierarchy (S/A/B), we isolate a 'Golden Triangle' of invariants—State Mapping, Ingress Consistency, and Control-Path Sync—that bridge the reference model and hardware state.

Experimental results demonstrate a paradigm shift: while standard BMC remains inconclusive at 64 stages, our methodology achieves 100% mathematical convergence in ~50 minutes . Furthermore, we demonstrate deterministic scalability up to 256 stages in approximately 7 hours. This work establishes a repeatable, automated framework for the formal sign-off of high-latency structures previously deemed unreachable.

People

Nitin Ahuja

Breaking the Simulation Wall – Practical Acceleration for Pre-Silicon Validation

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionNext-generation SoCs demand robust and high-confidence DDR subsystem verification, yet traditional simulation struggles to keep pace. Long-duration DDR behaviors—such as training loops, refresh cycles, retention checks, and hours of sustained traffic—consume excessive simulation time and slow down project velocity. These time-intensive patterns often stall coverage closure, push out debug windows, and delay subsystem readiness.

This work showcases a high-performance verification acceleration strategy using the Siemens Veloce Strato CS hardware emulation platform to remove these bottlenecks. By transitioning existing UVM stimulus into an emulation-optimized transactor environment, the flow executes long-running DDR workloads at speed order of magnitude faster while maintaining cycle-accurate behavior and full debug correlation. The result is faster iteration, increased test throughput, and earlier discovery of timing-sensitive issues that rarely surface in conventional simulation schedules.

Key highlights include an optimized DDR command/data transactor architecture for emulation, transparent reuse of simulation sequences, and targeted debug techniques purpose-built for hardware-assisted verification. This accelerated DDR flow enables teams to run extensive, hours-to-days traffic profiles within practical timelines—transforming verification productivity and delivering higher confidence in subsystem quality ahead of tape-out.

People

Research Manuscript

Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionYield Multi-Corner Analysis validates circuits across 125+ Process-Voltage-Temperature corners, creating combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^5$ samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier.
We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11\%) with zero tuning, reducing total validation cost by over $10\times$.

People

Wei Xing

University of Sheffield

Kaiqi Huang

Shenzhen University

Jiazhan Liu

College of Mechatronics and Control Engineering, Shenzhen University

Hong Qiu

Macau University of Science and Technology

Shan Shen

Nanjing University of Science and Technology

Research Manuscript

BREW-RC: Bit-Exact Recovery of ECCs from Write Timing in ReRAM Crossbars

12:03pm - 12:16pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC3-II. Hardware Security: Attack and Defense

DescriptionWe present BREW-RC, a non-invasive technique that uses a timing side channel to reverse engineer error-correcting codes (ECCs) in ReRAM crossbar memories. ECCs use a parity submatrix to extend data words with parity bits, forming codewords. These parity bits cannot be read directly, but BREW-RC reveals them by using write latency variability to determine the aggregate polarity of codeword transitions. Timing perturbations caused by ECC parity bit updates are encoded as a SAT instance whose solution yields the bit-exact parity matrix. Knowledge of the parity matrix enables: (1) improved timing models for side-channel attacks/mitigations and latency-sensitive applications, and (2) ECC-aware reliability characterization of devices whose error correction capabilities are unadvertised. We demonstrate BREW-RC on two commercial ReRAM products, recovering the complete ECC from multiple samples of each.

People

Tyler Sheaves

Alric Althoff

ARM

Dustin Richmond

Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe rapid adoption of chiplet-based architectures and high-speed die-to-die interconnects primarily driven by AI/ML massive data throughput requirements and integration complexity presents significant mixed-signal verification challenges. Traditional Digital Mixed-Signal (DMS) flows lack analog fidelity, while Analog Mixed-Signal (AMS) flows struggle with scalability and manual overhead. To address these fundamental limitations, Analog Port, in close collaboration with Siemens EDA, developed a unified, top-down verification methodology designed to bridge the gap between analog fidelity and digital performance.

This innovative approach leveraging Symphony Pro, part of the Solido Simulation Suite, extends the conventional UVM based digital verification framework to mixed-signal domain, enabling a holistic verification strategy while overcoming tool fragmentation and data integrity issues. It seamlessly combines high-fidelity SPICE simulation for critical analog blocks with high-performance digital simulation for the broader system.

In this presentation, we will demonstrate how Analog Port achieved up to 26X memory savings and more than 3X performance gain for their RX and TX simulations. We will also explore this novel methodology and its implementation, showcasing how it successfully verified a complex 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface, significantly enhancing productivity, improving silicon quality, and reducing time-to-market by resolving traditional mixed-signal verification trade-offs.

People

Engineering Poster

Bridging Hardware-Software Abstraction In UVM Verification

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIn advanced verification environments, standard UVM monitors may not offer enough flexibility or abstraction to capture and relay all relevant hardware events to the testbench. To solve this, a standardized mechanism is needed that allows smooth, event-driven communication from hardware interfaces to the UVM environment. This is especially crucial when the testbench must respond to complex hardware events—such as status changes, signal transitions, or protocol-specific conditions—and use these events to drive scoreboards, perform checks, or trigger reference model transactions. By adding proxy objects that serve as intermediaries between the hardware (HDL) and software (UVM) domains, the testbench can respond to hardware events in a modular and reusable way, reducing dependence on direct signal polling and improving maintainability. This approach is generally applicable to any hardware signal that needs to stay synchronized with the UVM environment.

People

Bhaskar Vedula

Chandrakanth Betageri

Bridging Physics and Engineering: Quantum EDA for Superconducting Qubits and Amplifiers

Engineering Special Session

3:30pm - 5:00pm PDT Monday, July 27 Seaside RM 7

EDA

Quantum

DescriptionAs quantum computing continues to advance, superconducting qubits have emerged as a leading platform due to their scalability and strong compatibility with microwave engineering. At the same time, quantum amplifiers are essential for enabling high fidelity readout by amplifying fragile quantum signals while minimizing added noise. Designing these systems, however, remains challenging due to tight performance margins, dense integration, cryogenic operation, and complex interactions between electromagnetic, circuit, and quantum effects. In this talk, I discuss how Quantum EDA techniques—tailored to the unique requirements of superconducting quantum circuits—can help bridge physics driven design and scalable engineering practice. I will highlight how EM and eigenmode analysis, automated quantum parameter extraction, and nonlinear circuit co simulation can be combined to guide the design and optimization of qubits, readout resonators, and quantum amplifiers within a unified workflow. These approaches illustrate how Quantum EDA can accelerate development toward robust and scalable superconducting quantum systems.

People

Chris Mueth

Bridging Quantum, AI, and EDA: The Next Frontier of Design Automation

Research Panel

10:30am - 12:30pm PDT Wednesday, July 29 Mtg Room 104A

Design

DescriptionQuantum technologies are rapidly transitioning from academic curiosity to practical enablers of next-generation electronic design automation (EDA). Yet the real opportunity lies not only in quantum computing itself, but in the convergence of quantum simulation, materials modeling, AI-native design, and system-level automation. This panel brings together leaders across quantum hardware, software, and industrial design workflows to examine how quantum technologies—paired with frontier AI—will transform the semiconductor and system-design landscape over the next decade.

Today's design challenges have outgrown classical scaling curves. Whether optimizing advanced node devices, discovering novel materials, modeling parasitic effects, or designing 3D-IC systems with extreme multiphysics coupling, classical simulation methods are straining under exponential complexity. Emerging quantum-accelerated approaches offer breakthrough potential: Hamiltonian-based solvers for nanoscale transport; quantum-enhanced simulation for chemical and materials discovery; quantum optimization methods for scheduling, routing, and verification; and hybrid quantum-classical pipelines that integrate seamlessly with existing EDA flows.

At the same time, generative AI and large language models (LLMs) are redefining design productivity. The intersection—Quantum × AI × EDA—is creating a new paradigm where quantum simulation feeds AI-driven design agents, AI discovers optimal materials for quantum and classical devices, and EDA frameworks orchestrate end-to-end system exploration. This compounding loop is catalyzing a shift toward Materials Design Automation (MDA), automated device co-optimization, and rapid multi-physics exploration at atomic accuracy.

This panel will explore four key themes:

1. Quantum Simulation for Materials & Devices: How quantum-accurate modeling (AIMD, MLFF, QMC, variational quantum solvers) unlocks breakthroughs in semiconductors, batteries, photonics, and superconducting components.

2. Quantum Hardware and Software Stack Evolution: Practical roadmaps, error-correction thresholds, algorithmic readiness, and how near-term quantum systems can augment industrial design workflows.

3. AI-Native and LLM-Driven Design Automation: How foundation models, retrieval-augmented simulation, and autonomous design agents interface with quantum tools to accelerate PPA and manufacturability.

4. Industrial Adoption & ROI: What it will take for design teams—fabless, IDM, EDA vendors, and hyperscalers—to integrate quantum capabilities into real production flows.
The session will conclude with a forward-looking discussion on how quantum technologies may reshape the future of design automation—shifting the industry from traditional scaling to physics-accelerated, AI-co-designed innovation. Attendees will leave with a clear understanding of what's real, what's coming, and how to prepare their organizations for the quantum-enabled EDA era.

People

Jimmy Cheng

Bridging the Modeling Gap: State-Aware Liberty Enhancements for Multimode IP Designs

Joseph Bardin

Google / UMass Amherst

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern SoCs integrate a wide range of IP types: I/O's, SerDes, PLLs, DACs, ADCs, memories...each operating across multiple protocols, voltage domains, and performance modes. While characterization flows accurately capture this mode dependent electrical behavior (including distinct thresholds, load limits, slew limits, and rail sensitivities), the Liberty (.lib) format remains largely scalar and static.

Key attributes such as max_capacitance, max_transition, and voltage_map can only be expressed as fixed per pin values, and existing constructs like when or mode_support affect only logical activation, not the underlying electrical state of the IP.

This fundamental limitation forces designers to maintain multiple mode specific .lib files, which increases configuration overhead and risks silent extrapolation during sign off when tools operate outside valid characterized ranges.

We propose a State Aware Liberty Modeling approach that introduces explicit constructs for both electrical configuration states and operational modes (protocol specific electrical constraints). This allows voltage mapping, thresholds, load limits, and slew limits to vary per mode within a single unified library. These enhancements generalize across all IP types, improving silicon to model correlation and enabling robust, mode accurate timing and power sign off for next generation SoC architectures.

People

SAURABH SRIVASTAVA

Bringing Graphs Closer to Memory: Compiler-Driven Data Transfer Reduction in the PIM Accelerator

Research Manuscript

10:43am - 10:56am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionProcessing-in-Memory (PIM) alleviates the memory bottleneck of modern AI workloads; however, its limited computational capability often necessitates hybrid architectures that integrate PIM with nearby processing units. In such heterogeneous systems, communication and host-side overheads remain dominant performance bottlenecks. Our profiling of SK hynix's AiMX reveals that CPU–AiMX communication and CPU-side data reordering account for 50.07% of end-to-end LLM prefill and 78.36% of decode execution time. Notably, 54.03% of reordering operations occur adjacent to AiMX-executable nodes, indicating significant untapped potential for near-memory execution to eliminate unnecessary data movement.
We propose a graph compiler that jointly optimizes computation and data movement for AiMX-based acceleration. The compiler performs (1) graph simplification to maximize AiMX-kernel coverage, (2) DMA-assisted tensor reordering and layout redefinition to offload host-side preprocessing, and (3) operator fusion to suppress redundant memory transfers. Integrated into the ONNX Runtime, our approach improves 2.00~2.73x speedup in the prefill phase and 18.50~38.29x in the decode phase, demonstrating the substantial benefits of graph-level co-optimization for PIM-enabled LLM inference and achieving performance comparable to hand-tuned AiMX execution.

People

Solution Advanced Technology, SK hynix

Ilkon Kim

Solution Advanced Technology, SK hynix

Seon Wook Kim

Korea University

Exhibitor Forum

BRONCO AI: AI-Native EDA in Production: Lessons from Customer Deployments

11:15am - 11:45am PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionBronco Debug in production is able to tackle multi-day, multi-person debugs in a matter of minutes. This session covers some of Bronco's AI-native EDA tooling that enables this work at full-chip SoC scale.

People

Exhibitor Forum

BRONCO AI: Introducing Dvbench: A Production-Grade Benchmark for Design Verification AI

2:30pm - 3:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

DescriptionAn announcement and overview of DVBench — Bronco's to-be-released benchmark that evaluates AI across real DV tasks spanning multiple data modalities and design hierarchies from block-level to full SoC, at production difficulty.

People

Jeffrey Pan

Bronco AI

Research Manuscript

BSGCN: Taming Diverse Sparsities in GCNs via Adaptive Band-Segmentation and Tailored Caching

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionAbstract
Graph Convolutional Networks (GCNs), a foundational technology
for relational data applications, are often bottlenecked by irregular
memory accesses caused by sparse graph structures. Existing accelerators face two fundamental limitations: their rigid dataflows
cannot adapt to varying graph sparsities, and their narrow focus on
high-degree nodes (HDNs) leads to systematic neglect of memory
traffic from the vast number of low-degree nodes (LDNs).
To address these issues, this paper introduces BSGCN, an accelerator built on a novel band-segmentation strategy. This approach partitions the graph such that the majority of LDNs are
grouped into large bands with similar data reuse characteristics,
while the remaining nodes form small bands containing only a few
LDNs. This segregation enables two co-designed innovations: 1) a
Band-Segmented Dataflow (BSD), which applies a tailored traversal strategy to each band type to handle diverse sparsity patterns,
and 2) a Band-Segmented Caching (BSC) hierarchy, combining a
specialized caching policy to exploit the reuse potential of LDNs
with a dedicated pinning mechanism for HDNs. Evaluation results
show that BSGCN achieves average speedups of 1.41× (up to 4.80×)
over state-of-the-art accelerators, while reducing DRAM traffic by
24.24% and improving energy efficiency by 1.30×.

People

BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs

Weisheng Zhao

Beihang University

Research Manuscript

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionBackside power delivery networks (BSPDN) provide superior power integrity while freeing backside routing resources. However, existing works fail to fully exploit these resources for power, performance, and area (PPA) optimization through strategic net allocation. This paper presents a co-optimization framework that maximizes PPA by strategically routing both clock and signal nets on the backside, enabling double-side routing. Experimental results demonstrate 88.1% IR-drop reduction, 23.0% frequency improvement, 10.9% power savings, and timing improvements (66.3% WNS, 40.2% TNS) over FSPDN with negligible nTSVs overhead.

People

Leilei Jin

Haoyang Xu

Siyuan Liang

Zhen Zhuang

Zhou Hu

Zixiao WANG

Rongmei Chen

Tsung-Yi Ho

BSPDN: A Power Delivery Architecture for 19.8% Core Power Reduction and 9.3C Thermal Mitigation in Next-Generation AI Processors

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThis work evaluates the performance and thermal benefits of Backside Power Delivery Networks (BSPDN) compared to traditional Frontside (FSPDN) architectures. Instead of push to max-performance, we proposed to focus on power efficiency. Our results demonstrate that BSPDN achieves a 19.8% reduction in power consumption under nominal operating conditions compared to FSPDN. Furthermore, the structural optimization of the power grid significantly enhances thermal dissipation, resulting in a 9.3°C reduction in peak operating temperature. These findings suggest that BSPDN is a critical enabler for next generation datacenter.

People

Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?

DAC Pavilion Panel

3:00pm - 3:45pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

DescriptionArtificial Intelligence is rapidly transforming semiconductor design automation, promising major gains in productivity across the design lifecycle — from system requirements and architectural specifications to verification, layout optimization, and design closure. Yet unlike traditional EDA tools, AI systems rely on proprietary data, evolving models, and complex integrations with mission-critical workflows. This raises a fundamental and provocative question for the industry: would you trust an AI system to make decisions that directly impact tape-out success?

This panel brings together leaders from startups, established EDA vendors, and semiconductor design houses to explore how AI is being applied to both upstream activities such as requirements definition and specification development, as well as downstream design and verification tasks. The discussion will examine trust, explainability, data ownership, and accountability when AI influences critical engineering decisions.

Panelists will debate the strategic build-versus-buy decision for AI-based design automation, including whether AI-generated requirements should be treated as authoritative inputs and how organizations can balance innovation with risk in cost- and schedule-critical silicon programs.

People

GM IP and Data Management Business

Engineering Presentation

Building an Ontology-Driven Knowledge Graph for Constraint-Aware Navigation of Semiconductor Design Documents

11:15am - 11:30am PDT Monday, July 27 Seaside Ballroom A

EDA

DescriptionSemiconductor design involves extensive documentation, often spanning hundreds of pages in documents with highly intricate and complex internal relationships, making manual navigation and cross-referencing highly inefficient. To overcome this critical bottleneck, we implemented a solution that significantly reduces manual effort by leveraging an Ontology-based Knowledge Graph (KG). Our core methodology involves defining a formal ontology to systematically model the diverse entities (e.g., modules, registers, protocols) and their complex dependencies across disparate documents (specifications, reports, manuals). This structured conversion process transforms unstructured conversion process transforms unstructured documentation into a unified, queryable KG, which is the key to easily mapping and understanding the intricate web of connections inherent in the design. This paradigm shift from keyword matching to relationship-aware knowledge representation significantly simplifies knowledge discovery. Furthermore, this meticulously constructed Knowledge Graph serves as the knowledge base for Graph RAG chatbot, which provides engineers with accurate, context-aware answers to natural language queries.

People

Research Manuscript

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

5:18pm - 5:30pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionThe scaling-up of large language models (LLMs) necessitates computing systems to have multi-processor-chip architectures, elevating the importance of chip-to-chip (C2C) communication. However, designing efficient C2C hardware architectures for LLM workloads faces three key challenges: generating realistic LLM-specific C2C traffic, accurately simulating hardware-level communication at scale, and efficiently exploring the exponentially large C2C design space. We propose C2C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator (switch/full-mesh, up to 512 chips), and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads. Validated against FPGA-based C2C prototypes, the C2C simulator achieves 2.46–8.23% end-to-end timing error across diverse traffic patterns. Its hybrid cycle & event model further accelerates large-scale simulation by up to 7.8× over a pure cycle-accurate baseline. Applied to a 32-XPU DeepSeek-R1-671B inference workload, C2C-Explorer identifies configurations that improve goodput by 44.1% and reduce memory by 98.4%. C2C-Explorer is open-source and available at https://anonymous.4open.science/r/C2C-Explorer.

People

Research Manuscript

Cache Where It Counts: Towards Workload-Aware I/O Coordination for NUMA Storage Systems

1:55pm - 2:08pm PDT Tuesday, July 28 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionModern Non-Uniform Memory Access (NUMA) servers equipped with distributed Non-Volatile Memory Express (NVMe) storage present new challenges for I/O coordination. First, conventional page cache allocators ignore storage topology, resulting in inefficient cross-node cache placement and performance issues. Second, CPU schedulers overlook cache and storage locality, causing frequent cross-node cache accesses and further degrading performance. Third, the OS page cache employs a rigid eviction policy that fails to adapt to diverse application workloads, while even programmable alternatives often require complex manual tuning. To address these challenges, we propose Laelaps, a workload-aware I/O coordination framework for NUMA storage systems. Laelaps introduces three key techniques: (1) storage-topology-aware page cache placement, co-locating cache pages with their backing NVMe devices; (2) storage-topology-aware I/O thread scheduling that aligns thread placement with cache distribution to minimize cross-node accesses; and (3) workload-aware adaptive page caching that automatically selects eviction policies based on observed application access patterns. Evaluation shows that Laelaps achieves 1.41× geometric mean throughput improvement with 3.5% runtime overhead.

People

Wenda Tang

Yanwen Wang

Yiduo Wang

Jie Wu

Cachence: Fine-Grained Cache Partitioning in Both Time and Space

Research Manuscript

4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionCache partitioning mechanisms improve system performance by judiciously adjusting cache space among applications. Its effectiveness can be enhanced by partitioning in both time and space. However, existing solutions are limited to only one dimension.

This paper presents Cachence, a fine-grained cache partitioning mechanism in both time and space. Cachence profiles cache access patterns with theoretically guaranteed accuracy while incurring fixed storage overhead. Based on runtime microarchitectural statistics, we also propose a lightweight yet precise performance prediction model. Our evaluation shows that Cachence outperforms existing approaches by an average of 9.5% to 28.2%, and up to 48.8% on a 16-core system.

People

Michigan Technological University

Diyu Zhou

Cacheparallel: Comprehensively Exploring Multi-Level Acceleration for Diffusion Models

Research Manuscript

1:30pm - 1:42pm PDT Wednesday, July 29 Mtg Room 101B

AI3-II. AI/ML Application and Infrastructure

DescriptionDiffusion models, despite their exceptional generative capabilities, are bottlenecked by slow inference owing to their complex architectures and multi-step iterative processes. Although caching is a promising acceleration method, previous approaches suffer from a tight coupling with specific network structures and low computational density. Moreover, caching is challenging to integrate with other methods to further enhance performance due to non-orthogonality, as simple integration often leads only to model performance degradation.

To address these challenges, we propose CacheParallel, a novel training-free scheme that optimizes both caching and parallelism at the intra- and inter-step levels to reduce the computational load and increase the computational density simultaneously. We first introduced the fusion node to abstract the network structures into generic pre-fusion and post-fusion computational streams. For the pre-fusion stream, we applied intra-step caching optimized by the proposed CPS algorithm. For the post-fusion stream, we exploit inter-step output correlations to enable parallel computing and boost computational density. To mitigate accumulated errors and non-orthogonality issues, an error correction mechanism was designed based on our observation of the inherent linear correlations of the models.

Comparative experiments showed that we achieved significant performance improvements across various models, with the peak improvement surpassing 100\%.

People

Qianru Lyu

Di Niu

Jinwei Xu

Jingfei Jiang

Xiangrui Yang

Sheng ma

Dongsheng Li

CADENCE DESIGN SYSTEMS: LLMs in Production With Chip Teams: Opportunities, Challenges, and Lessons Learned

Exhibitor Forum

10:30am - 11:00am PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionThe growing complexity and specialization of modern chips necessitate a fundamental shift in how we approach design and verification. Large Language Models (LLMs) present a timely and transformative opportunity to address key bottlenecks in chip design flows.

This talk will explore how the advanced natural language processing capabilities of LLMs can streamline design and verification processes, from automated verification plan generation to intelligent debug assistance—supported by real-world case studies. We will share insights from fine-tuning LLMs for DV-specific tasks, demonstrating measurable improvements in accuracy of LLMs on real-world examples.

Beyond the opportunities, we will discuss the challenges of deploying generative AI solutions in production chip design teams, including infrastructure constraints, reliability concerns, and building user trust. By integrating generative AI with modern methodologies and software stacks, this talk will outline how LLMs can accelerate chip design cycles and significantly reduce time to market for next-generation chips.

People

Kartik Hegde

CADSTROM: Beyond DRC: How AI-Driven Component Modeling Is Closing the Verification Gap Between Schematic and Silicon

Exhibitor Forum

5:15pm - 5:45pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionDesign verification has made enormous strides at the chip level, yet a stubborn class of errors continues to plague teams working at the board and system level — voltage mismatches, misconfigured interfaces, overlooked datasheet constraints, and derating violations that standard DRC tools weren't built to catch. These aren't exotic corner cases. They're fundamental checks that experienced engineers know matter but that are tedious to perform manually and easy to miss under schedule pressure. The result: unnecessary respins, late-cycle fire drills, and eroded confidence in design closure.

This session explores how AI-assisted validation can bridge that gap by automatically constructing detailed behavioral models for every component in a design — grounded in actual datasheet specifications, not heuristic rules — and running deterministic checks on interface compatibility, power sequencing, thermal derating, and bus configuration as the schematic evolves. Unlike LLM-based "copilot" approaches, this methodology produces findings that are verifiable, traceable, and citable back to source documentation, while keeping proprietary design IP fully protected.

We'll walk through anonymized case studies from design consultancies, medical device OEMs, and industrial electronics teams where automated validation uncovered previously unknown, fabrication-blocking issues early enough to resolve with a schematic edit instead of a board respin. Attendees will leave with a concrete framework for where AI-assisted verification fits alongside existing EDA workflows — complementing, not replacing, the tools and judgment they already rely on.

People

Margot Blouin

Cadstrom

Research Manuscript

Can Asymmetric Tile Buffering Be Beneficial?

4:30pm - 4:42pm PDT Monday, July 27 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionGeneral matrix multiplication (GEMM) is the computational back- bone of modern AI workloads, and its efficiency is critically depen- dent on effective tiling strategies. Conventional approaches employ symmetric tile buffering, where the buffered tile size of the input 𝐴 along the dimension 𝑀 matches the output tile size of 𝐶. In this paper, we introduce asymmetric tile buffering (ATB), a simple but powerful technique that decouples the buffered tile dimensions of the input and output operands. We show, for the first time, that ATB is both practical and highly beneficial. To explain this effect, we develop a performance model that incorporates both the benefits of ATB (higher arithmetic intensity) and its overheads (higher kernel switching costs), providing insight into how to select effective ATB tiling factors. As a case study, we apply ATB to AMD's latest XDNA2™ AI Engine (AIE), achieving up to a 4.54× speedup, from 4.8 to 24.6 TFLOPS on mixed-precision BFP16–BF16 GEMM, establishing a new performance record for XDNA2™ AIE.

People

Chengyue Wang

University of Illinois Urbana-Champaign

Qiran Pang

Xinrui Wu

The University of Texas at Austin

HyeGang Jun

University of Illinois

Luis Romero

EPFL

Endri Taka

Diana Marculescu

The University of Texas at Austin

Tony Nowatzki

Pranathi Vasireddy

Joseph Melber

Deming Chen

UIUC

Jason Cong

CANNON: A CXL-Based Near-Memory Processing Architecture for Approximate Nearest Neighbor Search on Real Hardware

Research Manuscript

1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 202C

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionApproximate Nearest Neighbor (ANN) search is a foundational primitive for AI applications such as Retrieval-Augmented Generation (RAG). CPU and GPU-based solutions face scalability bottlenecks due to limited local memory, while a multi-tier architecture using SSDs introduces high latency from coarse-grained I/O, mismatched with fine-grained data access patterns inherent to ANN search. We present CANNON (A CXL-Based Near-Memory Processing Architecture for Approximate Nearest Neighbor Search on Real Hardware), a fully offloaded Near-Memory Processing (NMP) architecture implemented on real CXL hardware. CANNON transforms the ANN search pipeline into a fine-grained, deeply pipelined dataflow architecture to maximize throughput, and introduces asynchronous hashing, a speculative execution mechanism that hides hash-check latency to prevent pipeline stalls. Evaluated on large-scale vector datasets, CANNON achieves up to two orders of magnitude performance improvement over state-of-the-art CPU and GPU baselines.

People

Research Manuscript

CAPA: Convertibility-Aware Mixed-Precision Accelerator for Asymmetric GEMM in Weight-Only Quantized LLMs

11:18am - 11:30am PDT Tuesday, July 28 Mtg Room 101A

AI4-II. AI/ML Architecture Design

DescriptionFP-INT GEMM accelerators for weight-only quantized large language models suffer from large partial sum (psum) overhead and a lack of precision-convertibility, limiting scalability. To mitigate this, we propose CAPA, an accelerator achieving high efficiency and versatility. (1) CAPA introduces Hybrid Delta Block Floating Point (HDBFP), a novel INT-based format that reduces psum overhead, preserves accuracy, and integrates BF16/FP16 arithmetic. (2) CAPA adopts Weight Decomposition to unify INT8 and INT4 arithmetic, enabling parallel processing. We demonstrate CAPA attains identical GPU accuracy, improving area efficiency by 3.98x and power efficiency by 4.38x over the FP-FP baseline.

People

Engineering Poster

Capacitance Modeling for Meander Co-Planar Waveguide Devices Used in Quantum Computers

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionSeveral companies have been developing quantum computers. Co-Planar Waveguides (CPWs) couple qubits in a quantum computer and are also used to probe the quantum state in qubits. The design of meander CPW devices is an emerging area where the modeling of signal conductor's capacitance is important. Due to the complex shape of a meander CPW, a field solver is exclusively used to find the total capacitance of the signal conductor of a CPW device. In this work, we show how to model 3D capacitance in a CPW efficiently. We properly decompose the space along the path of the signal conductor into multiple regions and thus reduce the complex 3D capacitance modeling problem to a set of smaller 3D capacitance problems. Some of these smaller 3D capacitance problems (where the segment of the signal conductor is straight) are treated as 2D capacitance problems for a fixed cross section, although the shape of the cross section can vary as one moves to a next cross section. Others (where the segment of the signal conductor is a half-circle, for example) are still 3D capacitance problems. These remaining true 3D capacitance problems are further reduced into equivalent 2D capacitance problems.

People

Research Manuscript

Capacitive Touchscreens at Risk: Recovering Handwritten Trajectory on Smartphone via Electromagnetic Emanations

10:43am - 10:56am PDT Tuesday, July 28 Mtg Room 202AB

Security

SEC3-I. Hardware Security: Attack and Defense

DescriptionThis paper reveals and exploits a critical security vulnerability: the electromagnetic (EM) side channel of capacitive touchscreens leaks sufficient information to recover fine-grained, continuous handwriting trajectories. We present Touchscreen Electromagnetic Side-channel Leakage Attack (TESLA), a non-contact attack framework that captures EM signals generated during on-screen writing and regresses them into two-dimensional (2D) handwriting trajectories in real time. Extensive evaluations across a variety of commercial off-the-shelf (COTS) smartphones show that TESLA achieves 77% character recognition accuracy and a Jaccard index of 0.74, demonstrating its capability to recover highly recognizable motion trajectories that closely resemble the original handwriting under realistic attack conditions.

People

Nanjing University of Aeronautics and Astronautics

Yuan Li

Shihui Zheng

Capbench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction

Research Manuscript

10:56am - 11:10am PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionWe present CapBench, a fully reproducible, multi-PDK dataset for capacitance extraction. The dataset is derived from open-source designs, including single-core CPUs, Systems-on-Chip, and media accelerators. All designs are fully placed and routed using 14 independent OpenROAD flow runs spanning three technology nodes: ASAP7, NanGate45, and Sky130HD. From these layouts, we extract 61,855 3D windows across three size tiers to enable transfer learning and scalability studies. High-fidelity capacitance labels are generated using RWCap, a state-of-the-art random-walk solver, and validated against the industry-standard Raphael, achieving a mean absolute error of 0.64% for total capacitance. Each window is pre-processed into density maps, graph representations, and point clouds. We evaluate 10 machine learning architectures that illustrate dataset usage and serve as baselines, including convolutional neural networks (CNNs), point cloud transformers, and graph neural networks (GNNs). CNNs demonstrate the lowest errors (1.75%), while GNNs are up to 41.4 times faster but exhibit the larger errors (10.2%), illustrating a clear accuracy–speed trade-off.

People

Engineering Special Session

Capturing Quantum Components in Quantum EDA

3:30pm - 5:00pm PDT Monday, July 27 Seaside RM 7

EDA

Quantum

DescriptionAs we drive toward building the Quantum EDA (QEDA) stack, a familiar enemy stands in our way. To fully model a quantum chip—whether accurately capturing the physics of an individual qubit or solving the compact model of an entire processor—one must solve the quantum many-body problem. This is the "exponential wall" that pushes us to build a QPU in the first place. In this talk, I will lay the groundwork and thesis for a comprehensive QEDA stack. I will then discuss how Kothar's classical solvers pave a path to modeling hundreds of qubits without sacrificing the "quantumness" of the chip's components. Finally, we will establish a critical roadmap: the transition toward "using quantum computers to design quantum computers.

People

Jonathon Riddell

Kothar

Research Manuscript

CARAMEL: Boosting Device Utilization in Control Flow Auditing

4:06pm - 4:18pm PDT Monday, July 27 Mtg Room 203C

Security

SEC4. Embedded and Cross-Layer Security

DescriptionMicrocontroller Units (MCUs) are widely used in safety-critical systems, making them frequent attack targets. This demands lightweight defenses that remain reliable even after software compromise. Control Flow Auditing (CF-Aud) strengthens Control Flow Attestation by ensuring authenticated control-flow logs (CFLogs) are reliably delivered from a compromised prover (Prv) to a remote verifier (Vrf), enabling assessment of system behavior and support for remediation. However, existing CF-Aud designs rely on a costly busy-wait phase that limits Prv's utilization. In this work, we propose CARAMEL: a hybrid hardware-software root-of-trust architecture that reduces this bottleneck by enabling log transmission without halting execution. Its minimal communication interface and implementation are open-source.

People

Alexandra Lengert

University of Zurich

Adam Caulfield

University of Waterloo

Ivan De Oliveira Nunes

University of Zurich

Engineering Poster

CDG-DNN: Scalable Test Template Generation Using Adaptive Neural Architecture for Industry Class CDG Hardware Verification

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionCoverage-Directed Generation (CDG) is essential for driving verification toward hard-to-hit coverage events, but existing DNN-augmented CDG flows have largely remained at proof-of-concept scale with strong GPU dependence. This work presents a production-grade, design-agnostic DNN-assisted CDG framework deployed on next-generation IBM POWER and Z processor units, scaling from 4 parameters and 320 events to 1,800 parameters and 36,000 events while remaining practical for industrial flows. By exploiting latent clustering in coverage events, hidden-layer width is sized by correlation structure (∼100 clusters) instead of raw event count, delivering a 508× memory reduction (30 GB to 60 MB) and 3.75× CPU training speedup (7.5 h to 2 h), enabling CPU-only deployment without accuracy loss. On a complex production unit, the DNN-guided CDG hits 59 of 74 RIT-critical no-hit events in 10 days—including 4 events missed for 272 days by state-of-the-art regressions—while requiring one template to match and surpass five baseline CDG templates. The same configuration generalizes across units without hyperparameter retuning, demonstrating scalable, transferable CDG acceleration suitable for real tapeout schedules.

People

Research Manuscript

Celestialeye: A Synergistic CPU-FPGA Engine for Accurate Frequency Measurement in High-Speed Data Streams

4:54pm - 5:06pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionAccurate frequency measurement in high-speed data streams is crucial. While FPGA-based solutions are promising, existing designs often trade off throughput against accuracy due to limited hardware resources. This paper introduces CelestialEye, a CPU-FPGA synergistic architecture that employs a CPU-based heuristic decoding algorithm for high accuracy and offloads high-throughput tasks to the FPGA. Its pipelined hardware integrates hot/cold item separation, advanced compression, and encoding to optimize on-chip SRAM efficiency and bandwidth utilization. Furthermore, the frequency bounds generated by the FPGA process can accelerate the CPU's decoding. Experimental results demonstrate that CelestialEye significantly outperforms the state-of-the-art BitMatcher in both performance and accuracy.

People

Zhongxian Liang

Harbin Institute of Technology

Ying Li

Harbin Institute of Technology

Peng Cheng Laboratory

Research Manuscript

Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm

3:42pm - 3:54pm PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionStandard-cell-based design has long been the dominant approach in VLSI design, providing scalability and compatibility with established EDA tools. However, as design technology co-optimization (DTCO) becomes increasingly important at advanced process nodes, the fixed structure of standard cells limits the ability to optimize wirelength and area effectively, imposing a critical bottleneck at the Middle-of-Line (MOL) layers. In this context, dense pin access and M0 routing resources, critical for alleviating congestion on higher metal layers, are rigidly constrained by the cell boundary. A more flexible approach is to directly place transistors on the design canvas and perform routing at the transistor level, enabling physical-level optimization beyond the logic-level constraints imposed by standard-cell design. This work introduces a novel framework featuring cell-structure-independent transistor-level placement coupled with an MOL-aware routing engine. Experimental results demonstrate that the proposed framework achieves considerable improvements in wirelength and design area compared to the commercial standard-cell-based design tool and state-of-the-art transistor-level work.

People

Research Manuscript

Celle: Automated Standard Cell Library Extension via Equality Saturation

2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionAutomated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

People

Engineering Poster

Central DMA IP Verification Using Layered UVM Scoreboard

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionWe present a scalable verification strategy for a highly concurrent, partitionable Central DMA (CDMA) IP that supports inter‑execution‑environment transfers, multicast distribution, and native PCIe integration/exposure. The verification challenge spans deep AXI ID usage, unbounded read‑data interleaving, QoS and route‑by‑port attributes, ECC/parity reactions, and heterogeneous bus interfaces (AXI/APB/ACE‑Lite), compounded by system scale (dozens of station interfaces, MSI‑X vectors, and configurable engines/rings). Our solution is a layered, channel‑aware UVM scoreboard that cleanly separates transfer‑intent binding from protocol and data checking. A transactor decodes descriptors to publish transfer intent; the scoreboard binds read IDs (via first read ADDR of source), captures source data, then binds write IDs (via first write address of destination) to perform beat‑accurate data comparisons. Completed transfers sends out to specialized scoreboards—AXI attribute/protocol/bandwidth, writeback, and MSI‑X coalescing/ordering—with a unified completion model. Results show >50% reduction in average debug time, faster coverage closure (especially DMA cross bins), simpler scenario extensibility through reusable checkers, and earlier detection of critical issues; to date, no silicon issues have been observed. This layered approach improves observability, triage clarity, and reuse, accelerating time‑to‑market while lifting verification quality for CDMA variants.

People

Jagadish Rongali

NXP

Engineering Special Session

Challenges and Solutions in the next-Generation Emulation and Prototyping Solutions

3:30pm - 4:00pm PDT Tuesday, July 28 Seaside RM 7

Chiplet

EDA

Systems

DescriptionThis talk will explore the key challenges facing next-generation emulation and prototyping, including scalability, integration with heterogeneous systems, debugging capabilities, and support for emerging application domains such as AI and automotive. The session will then present cutting-edge solutions and best practices that address these hurdles, such as hybrid emulation approaches, cloud-based prototyping, improved hardware/software co-verification techniques, and advanced instrumentation for real-time analysis. Attendees will gain insights into recent technological advancements, practical deployment strategies, and future trends shaping the landscape of emulation and prototyping. This talk is intended for engineers, researchers, and decision-makers seeking to optimize verification flows and accelerate innovation in next-generation systems.

People

Engineering Poster

Channel Width Optimization for IR Drop Reduction in Advanced SoCs

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionPower delivery challenges in advanced System-on-Chip (SoC) designs are increasingly critical due to stringent performance, area, and reliability requirements. Traditional approaches to channel width optimization are performed late in the design cycle, often relying on post-RTL Engineering Change Orders (ECOs). These late-stage modifications are complex, error-prone, and risk project delays, while narrow or sub-optimal interconnects exacerbate IR drop and electromigration (EM) issues, degrading power integrity and yield.

We propose an early-stage methodology that shifts EM/IR analysis and channel width optimization to the early design phase, leveraging preliminary floorplans, power grid data, and pseudo currents derived from historical designs. This proactive approach enables identification of voltage drop and current density hotspots before RTL availability, allowing designers to balance IR drop mitigation against routing resource efficiency. Results from initial implementations demonstrate strong correlation with post-RTL simulations, validating the accuracy of early predictions.

By addressing EM/IR risks upfront, this methodology reduces reliance on late ECOs, improves design robustness, and accelerates turnaround time. Future integration with automated in-design IR-fixing techniques promises further efficiency gains, ensuring reliable power delivery in next-generation SoCs.

People

Research Manuscript

ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs

3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionFunctional verification accounts for over 50% of the IC development lifecycle, making SystemVerilog Assertions (SVAs) indispensable for rigorous digital chip verification. However, manual SVA authoring is labor-intensive and error prone. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. The AgentBridge platform facilitates systematic data generation, augmentation, and validation, decomposing complex verification processes into modular, verifiable subtasks. ChatSVA achieves syntax and function pass rates of 98.66% and 96.12%, averaging 139.5 SVAs per design with 82.50% function coverage. A ChatSVA web service is publicly available.

People

Lik Tung Fu

National ASIC Center, School of Integrate Circuits, Southeast University

Jie Zhou

shaokai ren

mengli zhang

Jia Xiong

Nan Guan

Chimera: A Unified FHE Accelerator with Enhanced Compatibility for TFHE

Hugo Jiang

University of Cambridge

Research Manuscript

3:54pm - 4:06pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionFully homomorphic encryption (FHE) allows direct computation on encrypted data and thus enables privacy-preserving computation in the cloud. Among FHE schemes, CKKS efficiently supports arithmetic computation, while TFHE excels in logic operations. Recent studies have attempted to develop unified FHE accelerators that support diverse computational tasks and leverage the complementary strengths of the two schemes. However, existing unified FHE accelerators are predominantly CKKS-centric. At the operator layer, TFHE is mapped onto CKKS-oriented operators, causing significant performance degradation. Furthermore, the invocation to functional units and memory is entirely dominated by CKKS, resulting in hardware underutilization for TFHE.

In this paper, we propose three coordinated co-optimizations to address these challenges. First, we unify the computation of Fast Fourier Transform (TFHE core operation) and Number Theoretic Transform (CKKS core operation), and design a dual-mode computational flow to efficiently support both computations. Second, we propose an aggressive strategy of bootstrapping key unrolling to maximize TFHE hardware utilization. Third, we design a hardware-oriented support for FFT Shrinking KeySwitch to mitigate the performance bottleneck of TFHE KeySwitch. Accordingly, we present Chimera, a unified accelerator that redesigns the functional units and memory organization for TFHE to efficiently support these optimizations. Lastly, we develop an error, memory, and bandwidth-constrained auto-tuning framework that derives optimal TFHE configurations to maximize TFHE hardware utilization. Compared with the state-of-the-art unified FHE designs, Chimera achieves an average performance improvement by 14.84x across TFHE workloads, while maintaining comparable performance on CKKS workloads, with only a 9.6% area increase.

People

Tenghui Hua

the Institute of Computing Technology, Chinese Academy of Sciences at Beijing

Huawei Li

Institute of Computing Technology, Chinese Academy of Sciences

Jianan Mu

ICT, CAS

Jing Ye

State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences

Liang Kong

Institute of Computing Technology

Mingzhe Zhang

Exhibitor Forum

CHIPAGENTS AI: AI Agent-Driven Timing Closure

1:45pm - 2:15pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

DescriptionTiming closure remains one of the most iteration-heavy bottlenecks in chip design, spanning multiple teams and abstraction levels from RTL through signoff. Each iteration requires running tools that take hours to days, making the feedback loop between identifying a timing violation and validating a fix prohibitively slow. Extracting actionable signal from massive timing reports, mapping timing violations back to RTL, and choosing among fixes with complex PPA tradeoffs demand deep expertise and remain largely manual. We explore how AI agents can be applied to this problem: what domain-specific capabilities they need beyond general code generation and how an agent-driven "shift-left" strategy can reduce iteration count and accelerate convergence. We present ChipAgents' approach to timing closure along with the lessons we've learned along the way.

People

Exhibitor Forum

CHIPAGENTS AI: Autonomous Root Cause Analysis: Agentic AI for Debugging at Commercial Scale

1:45pm - 2:15pm PDT Monday, July 27 Exhibitor Forum, Exhibit Floor

DescriptionOver half of frontend ASIC engineering time is spent on debugging and root cause analysis, navigating millions of lines of HDL and terabytes of waveform data. Despite this cost, hardware debugging remains almost entirely manual. This presentation introduces ChipAgents RCA, the first autonomous, agentic AI system for end-to-end ASIC root cause analysis using both code and waveform data at commercial scale.

ChipAgents RCA treats debugging as a structured search problem. The system combines three core innovations: (1) a waveform understanding engine purpose-built for AI agents that enables symbolic, query-based reasoning over massive waveform databases; (2) a novel multi-agent prover-verifier architecture that explores debugging hypotheses in parallel while enforcing skepticism and verification; and (3) a self-consistency ranking layer that calibrates confidence and surfaces the most reliable explanations to engineers.

The system has been evaluated across a diverse dataset of commercial-scale IPs, including bus fabrics, RISC-V cores, and complex protocols such as PCIe and DDR, spanning bug classes like backpressure, data corruption, protocol violations, and clock-domain issues. ChipAgents RCA achieves over 3x higher pass-at-one accuracy than state-of-the-art generic AI agents. In a representative PCIe 3.0 case study (36k lines of code, multi-level indirection), ChipAgents RCA isolated the exact root cause and patch in 10 minutes, compared to 4–8 hours of projected human effort, representing a 12x speedup.

This talk will present the system architecture, evaluation results, and lessons learned deploying autonomous debugging agents in real verification flows, highlighting how agentic AI can fundamentally change how hardware teams approach debug and verification closure.

People

Research Manuscript

Chiplanner: Physically-Aware and Timing-Driven Design Planner for 2.5D Multi-Chiplet Systems

2:47pm - 3:00pm PDT Monday, July 27 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionWhile chiplet-based 2.5D integration offers scalable high-performance computing with reduced manufacturing cost, it also poses significant challenges in design closure. Achieving timing closure in chiplet-based systems is notoriously difficult and frequently demands repeated engineering change orders (ECOs) and architectural-level iterations. To overcome these challenges, we propose ChiPlanner, a holistic {early-stage} design planner that integrates chiplet partitioning and physical planning. ChiPlanner first employs approximate placement to estimate post-chiplet-placement timing in advance of partitioning, which provides guidance for partitioning and helps reduce timing gaps. It further models inter-chiplet delay and incorporates a parallel net-weighting strategy in timing-driven physical planning to optimize overall system performance. Moreover, Bayesian optimization is leveraged to systematically explore the trade-off between chiplet manufacturing cost and system timing. Experimental results demonstrate that incorporating ChiPlanner's early-stage planning enables downstream chiplet design tools to achieve notably superior optimization outcomes, delivering average improvements of 42.4% in total negative slack (TNS) and 16.8% in worst negative slack (WNS).
These results confirm that accurate early-stage planning provides a far better initialization for chiplet design and significantly reduces the burden on later ECOs and architectural-level iterations.

People

Zixuan Li

Kanglin Tian

Fan Hu

Zirui Li

Xinyue Wu

hengyuan zhang

Shixin Chen

Jianwang Zhai

Xinfei Guo

Kang Zhao

Chiplite: High-Level Performance Modeling Methodology for Automotive Chiplet Systems

Work in Progress

6:33pm - 6:34pm PDT Monday, July 27 Exhibit Hall

DescriptionAs automotive compute platforms evolve toward chiplet-based
architectures, the increasing heterogeneity introduces new challenges
in exploring the architecture design space as a function of
metrics such as performance, power, area, and cost. In this pursuit,
traditional high-fidelity methodologies, using detailed virtual
prototypes, can be cumbersome to build and computationally prohibitive
for early-stage design exploration. In contrast, analytical
techniques such as roofline modeling offer rapid insights but depend
on overly idealized assumptions — such as perfect computation–
communication overlap, and sustained peak bandwidth —
that do not hold in heterogeneous chiplet systems.

To address these limitations, we introduce ChipLite, a hybrid
modeling framework that extends the hierarchical roofline model
with workload-aware task mapping, realistic memory-access distributions,
and inter-/intra-chiplet fabric flow modeling. Using
ChipLite, we analyze three distinct chiplet architectures as example
case studies and demonstrate how workload completion times
are shaped by inter- and intra-chiplet congestion. Compared to
a naïve roofline model, for these case studies, ChipLite achieves
up to 6x lower error in predicting execution time, while retaining
orders-of-magnitude faster turnaround than detailed simulation

People

Research Manuscript

Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification

5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionAs integrated circuit designs grow in complexity, reference model development for functional verification faces increasing challenges. We propose ChipModeler, an LLM-assisted platform that streamlines reference model generation and verification through design standardization and hierarchical agile modeling. By employing a building-block generation strategy, ChipModeler significantly enhances both efficiency and quality. Evaluation on 300 diverse designs shows up to 58.99% improvement in performance, a 9.18× increase in generation capacity, and a 7.11× acceleration in design and validation cycles compared to manual methods, demonstrating ChipModeler's effectiveness in automating reference model development.

People

National ASIC Center, School of Integrate Circuits, Southeast University

Nan Guan

Zhe Jiang

Xi Wang

Chipshub Faculty Fellows Train the Trainers Workshop

Workshop

9:00am - 12:30pm PDT Sunday, July 26 Mtg Room 201B

DescriptionThe ChipsHub is a new community infrastructure to broadly support IC chip design and semiconductor workforce development. The objective of the Faculty Fellows program is the creation of appropriate and sharable educational and tool content to enable a new pool of universities to teach chip design curricula to previously-unserved populations of learners. To this end, the Faculty Fellows are establishing a library of end-to-end design workflows and newly developed classes for post-fab chip testing. In this workshop, the ChipsHub Faculty Fellows will present their work in developing and disseminating pedagogical materials including lectures and tutorials for chip design workflows. The discussion will include how agile open source and industrial tool flows and PDKs will carry working code forward in a robust, maintainable, and scalable fashion.

People

Matthew Morrison

University of Notre Dame

Research Manuscript

CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators

10:30am - 10:43am PDT Monday, July 27 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionHigh-Level Synthesis (HLS) lowers the barrier to FPGA development by allowing a wider range of programmers to design hardware accelerators. However, determining the appropriate synthesis directives (pragmas) remains a major challenge, particularly for developers without hardware expertise. As designs grow more complex and the pragma search space expands, choosing the right pragmas becomes essential for achieving low resource usage and high performance. Automated design space exploration (DSE) provides an effective solution to this challenge. The enormous search space and time-consuming design-point evaluation highlight the need for efficient search strategies. However, existing search strategies mostly rely on inefficient exhaustive search, hyperparameter-sensitive metaheuristic methods, or dedicated methods that are difficult to port and generalize.
To address these issues, we propose a rule-mining-based search strategy that efficiently guides exploration toward the most promising regions of the design space. In addition, we introduce a design space decomposition method to prune the search space, as well as a CodeLLM-based design-point evaluation method, which is both faster than directly invoking HLS tools, and more accurate than prior GNN-based approaches. Experimental results on four widely-used HLS benchmarks demonstrate that, under the same time budget, our DSE framework achieves better Quality of Results (QoR) than the state of the art. Our demo code is released at https://github.com/ScopeHLS/CHiRM-DSE

People

Shi Chao

Zhu Qinggang

Hohai University

Qianyu Cheng

Jing Wu

Zhou Xuehai

ChiSER: Surrogate-Enhanced Resource-Aware Exploration of Chiplet-Based Deep Neural Network Accelerators

Research Manuscript

11:10am - 11:23am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionCo-designing chiplet-based neural-network accelerators spans partitioning, placement, dataflow, and microarchitecture under tight energy and latency limits. Fast system-level estimators scale to large searches but blur intra-core effects that dominate energy; fine-grain reference models capture them but are too slow in-loop. We close this speed–fidelity gap with a coarse-to-fine flow: a compact, architecture-aware surrogate of intra-core cost guides the global search, and only top designs are rechecked with the reference model. Our contributions are an energy-focused feature space and a lightweight predictor across convolutional and GEMM-like workloads. On ResNet-50 and a Transformer, we reduce a manufacturing-weighted energy–delay objective by up to 62\% and 44\%, respectively.

People

Yi-Cheng Lo

Siva Satyendra Sahoo

Ciphershield: Safeguarding DNN Inputs from Ciphertext Side-Channels in TEE

Research Manuscript

2:21pm - 2:34pm PDT Wednesday, July 29 Mtg Room 202AB

Security

SEC1. AI/ML Security/Privacy

DescriptionConfidential environments such as Trusted Execution Environments (TEEs) are increasingly used to protect the data and models of machine learning applications from adversarial attacks. Frameworks like TEE-protected Neural Networks (NN) have been deployed for secure cloud-based inference. However, recent studies have revealed one kind of ciphertext side channels that exploit the encryption process within TEE environments, known as CipherSteal attacks. Specifically, when data is transferred into a TEE using encryption schemes such as AES, the resulting ciphertext patterns can be observed to infer input data.

In this paper, we propose a series of methods named CipherShield to mitigate the ciphertext side-channel leakage and protect sensitive input data. It is a set of lightweight transformations that diffuse and decorrelate ciphertext without modifying the cryptography scheme. Our defenses, including block-based encryption, sparsity, and quantization, disrupt the per-address mapping patterns that ciphertext side-channels rely on to detect collisions while maintaining TEE compatibility and high throughput. The ciphertext hit rate, which reflects the amount of information leaked through ciphertext traces, drops from 50–80% to nearly zero across all evaluated datasets. On MNIST, CipherShield reduces classification accuracy from about 68% to as low as 2%. Evaluations on the Chest X-ray and CelebA datasets show similar reductions. Also, prototyping the block-based encryption in a TEE environment achieves markedly lower runtime than the original trace-based method, reducing encryption time by over 20x.

People

Hui Feng

University of California, Merced

Yuntao Liu

Lehigh University

Qian Wang

University of California, Merced

Research Manuscript

Circuitdiff: Bridging Netlist Knowledge with RTL Based on Graph Denoising Diffusion

11:36am - 11:50am PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionIn Integrated circuit (IC) workflows, EDA tools provide accurate circuit metrics by simulating and analyzing physical characteristics, but their computational overhead makes them impractical for rapid design iterations. Thus, accurate and efficient circuit metric prediction at the register-transfer-level (RTL) stage has become a hot topic. However, current methods still struggle to efficiently bridge the gap between RTL and physical characteristics. We propose CircuitDiff, a generative pre-training framework designed to learn a unified representation space between RTL and netlist. This is achieved by encoding the RTL graph as a condition for training a netlist graph denoising diffusion model. During fine-tuning, learnable queries are used to incentivize knowledge from the pre-trained model via cross-attention mechanisms. Experimental results show that CircuitDiff achieves superior performance in the prediction of early-stage circuit metric compared to state-of-the-art models, supporting the "left-shift" paradigm while maintaining computational efficiency. Our code and data will be publicly available at \url{https://github.com/CatIIIIIIII/CircuitDiff}.

People

Ning Wang

Zichong Deng

Bingkun Yao

Nan Guan

Closing the Loop Between AI and the Hardware That Fuels It

Exhibitor Forum

4:00pm - 5:00pm PDT Tuesday, July 28 Exhibitor Forum, Exhibit Floor

EDA

Systems

DescriptionRicursive Intelligence is a frontier AI lab focused on building self-improving systems, starting with chip design. We are reinventing chip development and closing the loop between AI and the hardware that fuels it, recursively accelerating the path to artificial superintelligence. We are the team behind AlphaChip (Nature 2021), RL-CCD (DAC Best Paper 2023), Insta (DAC Best Paper 2025), C3PO (ASP-DAC Best Paper 2026), with hands-on experience developing Gemini, Claude, and TPUs. Our team members come from Google DeepMind, Anthropic, NVIDIA, Cadence, Apple, Stanford, MIT, Harvard, and other top institutions, and we are backed by $335M from Sequoia, Lightspeed, DST, and NVentures. In this talk, we will discuss our technical progress and long-term vision for the future of AI and chip design.

People

Anna Goldie

Ricursive Intelligence

Research Manuscript

Closing the Loop: Hybrid NAS Guided by Analytical and Hardware-Calibrated Quantum Cost Modeling

2:21pm - 2:34pm PDT Wednesday, July 29 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionEstimating the true hardware cost of quantum machine learning (QML) models is challenging due to repeated circuit evaluations affected by noise, decoherence, and routing delays. Conventional metrics like gate count overlook such hardware-dependent effects. We propose an analytical quantum cost model that estimates required quantum hardware resources using real device calibration data, incorporating gate durations, routing overheads, and noise-induced inefficiencies. Complementing this, a classical cost model converts FLOPs into equivalent units, providing a unified hardware-aware hybrid cost metric. Integrating both, we then propose Hyb-HANAS framework which employs multi-objective NAS (NSGA-II) to jointly optimize accuracy, execution time, and parameter count in hybrid quantum–classical networks.

People

Muhammad Kashif

eBrain Lab, Division of Engineering, New York University (NYU) Abu Dhabi, UAE

Alberto Marchisio

New York University, Abu Dhabi

Muhammad Shafique

New York University, Abu Dhabi

Research Manuscript

CLUE-ECC: Low-Cost LPDDR6 Reliability Enhancement by Integrating System ECC with On-Die ECC

4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionDRAM scaling increases vulnerability to peripheral faults, making symbol level ECCs essential. LPDDR6 introduces a 12-bit data beat that misaligns with Reed Solomon codes with 8 or 16-bit symbol. An 8-bit RS code meets on-die parity budgets but cannot guarantee correction. A 12-bit RS code guarantees correction but exceeds the budget. CLUE-ECC pools the 16-bit on-die and the system ECC parity for proper correction with less parity. Evaluation shows superior error handling with 33.3% on-die parity storage, 14.83% area and 24.18% power savings with the same bandwidth impact compared to a conventional RS code.

People

Yonsei University & Samsung Electronics

Work in Progress

CMP-Aware Dummy-Fill Optimization via Generative Modeling and Measurement-Calibrated Prediction

6:54pm - 6:55pm PDT Monday, July 27 Exhibit Hall

DescriptionConventional rule-based dummy-fill methods satisfy density constraints but do not directly minimize chemical–mechanical polishing (CMP) variation, requiring costly post-layout fixing. We propose a learning-based dummy-fill insertion framework that enables proactive correction at the design stage by coupling a measurement-calibrated (MCAL) CMP predictor with a polygon-based conditional multilayer (PCM) fill generator. Trained on measurement data, the predictor, enhanced with shift correction for systematic offsets, achieves higher accuracy and efficiently identifies regions of high CMP variation. Leveraging PCM sequencing with blockwise causal attention, the generator produces diverse, design-rule-compliant multilayer fills conditioned on local active patterns. Coupling the generator and predictor enables design-space exploration that identifies optimal fills and reveals feature-CMP relationships guiding future fill strategies. The framework achieves substantially lower CMP variation on advanced-node benchmarks, demonstrating its effectiveness for practical deployment in advanced design flows.

People

Ji-Hye Lee

Computer Science Engineer (CSE) Team, Samsung Electronics

Min-Chul Park

Samsung Electronics, Device Solution

Yeji Kim

Computer Science Engineer (CSE) Team, Samsung Electronics

Usuk Chae

Technology Development, Samsung Electronics

Byungchul Shin

Technology Development, Samsung Electronics

Hyunjae Jang

Computer Science Engineer (CSE) Team, Samsung Electronics

JAE HYUN KANG

Technology Development, Samsung Electronics

SeongRyeol Kim

Computer Science Engineer (CSE) Team, Samsung Electronics

Young-Gu Kim

Computer Science Engineer (CSE) Team, Samsung Electronics

Dae Sin Kim

Computer Science Engineer (CSE) Team, Samsung Electronics

Research Special Session

Co-Designed Compute Memories for Ultra-Efficient DNN Inference

4:00pm - 4:30pm PDT Tuesday, July 28 Mtg Room 201A

Systems

DescriptionArtificial Intelligence (AI) at the edge must address conflicting performance and efficiency needs. One major challenge is the cost of data movement between processors and memories. Our proposed Near Memory Computing (NMC) architecture tackles this by providing memory arrays with lightweight arithmetic units, tailored to AI algorithms' needs for near sensor processing. We optimize holistically a) the design of NMC hardware, b) its integration within Systems-on-Chip (SoC) components, and c) edge AI applications. Our solution uses data parallelism, inherent in Deep Neural Network (DNN) models, to distribute computations across compute memory banks. It also employs aggressive quantization to reduce weight data size and lower computational demands. Additionally, it integrates seamlessly into standard SoC architectures, enabling end-to-end DNN inference near memory. Performance improvements of up to 250x are achieved compared to software execution, with only about 11% area overhead relative to similar non-compute memories.

People

Amirhossein Shahbazinia

Embedded Systems Laboratory (ESL), EPFL, CH

Research Manuscript

CO-MAC: A Center-Out Ordered Stochastic MAC for Low-Latency Inference

4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionStochastic computing offers efficient approximate arithmetic that aligns well with error-tolerant machine learning workloads, but its deployment is limited by long bitstream latency in stochastic multiply-accumulate (MAC) units.Prior work reduces MAC latency through deterministic bitstream generation and differential accumulation, but these methods do not fully exploit the statistical property of convolution weights.This work presents a novel stochastic MAC architecture named CO-MAC, which employs center-out weight ordering and an enhanced convolution engine design to reduce effective computation cycles while maintaining high accuracy.The method sorts weights by magnitude, reuses the incremental differences in magnitudes, and applies sign handling after accumulation.This shortens counter activity, maintains accuracy with long effective bitstreams, and simplifies the MAC hardware by avoiding bidirectional counters.Across convolutional neural network workloads, CO-MAC decreases MAC latency by up to 54.8% compared to prior stochastic MAC architectures, while preserving accuracy and hardware simplicity.

People

Research Manuscript

CODA: A Computation-Data Decoupled Dataflow Paradigm for DNN Computing on NPUs

10:30am - 10:43am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionDeep neural networks (DNNs) on Neural Processing Units (NPUs) require carefully optimized operator mappings to achieve high performance, yet the mapping space grows rapidly with increasingly complex on-chip memory hierarchies. Existing dataflow models rely on a computation–data coupled paradigm that forces all tensors to share identical storage structures and data transfer paths, severely limiting the expressible mapping space. We present CODA, a computation–data decoupled dataflow paradigm that enables tensor-wise independent modeling of on-chip storage and movement. CODA introduces the non-uniform loop space to jointly represent computation and per-tensor data mappings, together with an analytical performance model and a simulated-annealing–based optimizer. Across single-operator and fused-operator workloads, CODA achieves 1.10x-1.11x and 1.14x–1.85x speedup over state-of-the-art methods.

People

Research Manuscript

CODA: Cooperative Register Distribution and Arbitration Among Partitioned GPU Sub-Cores

11:50am - 12:03pm PDT Wednesday, July 29 Mtg Room 201B

AI4-II. AI/ML Architecture Design

DescriptionThe partitioned microarchitecture of Streaming Multiprocessor (SM) is a fundamental design that enables massive parallelism in modern General-Purpose Graphics Processing Units (GPGPUs). This approach, however, inherently introduces two critical inefficiencies: vast data redundancy across distributed private registers and severe conflicts and load imbalance in the limited banks. To holistically address these cross-partition bottlenecks, this paper introduces CODA, a cooperative Register File (RF) distribution and arbitration framework. CODA is composed of two synergistic mechanisms: the Cooperative Register Renaming (CRR), which eliminates data redundancy by maintaining a single physical copy of shared data across sub-cores, and the Dual-Skewed Arbitrator (DSA) that mitigates fine-grained bank conflicts by incorporating the operand collector ID into its arbitration logic. Evaluations on a diverse suite of deep learning workloads show that CODA exhibits superior performance compared to its baseline architecture, achieving a speedup of 28.9% alongside a 15.6% reduction in RF power consumption. These gains are directly attributed to a 15.9% reduction in RF load imbalance and a 12.7% lower bank conflict rate.

People

Bo Yuan

Sheng Liu

Yang Guo

Zekun Jiang

Jianfeng Cui

Cognitively Guided EM-Aware Routing Approach for Efficient Layout Implementation

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionElectromigration (EM) and resistance constraints are traditionally verified at sign-off, making routing electrically blind and leading to costly post-layout iterations. This paper introduces a simulation-driven routing (SDR) methodology that integrates electrical intent into the layout process, enabling EM-correct-by-construction routing. The proposed approach leverages average current datasets from circuit simulation or design intent (DI) set in schematic database to dynamically guide routing decisions. For optimal routing the automation implements customizable trunk stacking across multiple metal layers, optimized trunk widths for area efficiency, and uniform via distribution to minimize resistance. SDR supports configurable stacking strategies—Auto, Trunk, and Custom—allowing full user control through SKILL-based modifications for scalability across nodes. Visualization of current distribution further enhance topology optimization. Implemented on a 28nm analog design, the methodology achieves routing quality equivalent to golden reference while reducing EM sign-off iterations and manual effort. Results demonstrate 30% faster turnaround, zero area wastage, and improved reliability without compromising design integrity. This framework addresses critical pain points in conventional flows and provides a scalable solution for high-current nets in both mature and advanced technologies.

People

Akshita Bansal

Sachin Bhasin

COLA: Enabling Low-Latency Reads for Flash-Based SSDs via Code Length Adaptation

Research Manuscript

11:36am - 11:50am PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS6. Time-Critical and Fault-Tolerant System Design

DescriptionFlash-based SSDs are prone to bit errors in flash cells. To ensure reliability, SSDs employ error correction codes (ECCs) that encode user data bits into codewords composed of data and redundant parity bits, enabling correction of a limited number of bit errors. In practice, however, the raw bit error rate (RBER) of SSDs fluctuates over time. We observe that for ECCs with a fixed code rate (the fraction of user data bits per codeword), longer codewords provide higher reliability, while shorter codewords offer lower read latency. To this end, we propose COLA, an adaptive coding framework that optimizes the code length (i.e., total number of user data and parity bits per codeword) for individual SSD pages to achieve low-latency reads while maintaining reliability guarantees and constant storage overhead. COLA adopts a failure-aware read mechanism that selectively transfers and decodes failed codewords, and integrates a failure-aware read-latency model to determine actual read operations based on current RBERs and select the optimal code length for each write operation. Evaluation using the MQSim simulation shows that COLA significantly reduces average and tail read latencies compared to the default fixed-code-length approach.

People

Zhengyao Ding

Dingxin Wang

Xiaolu Li

Patrick P. C. Lee

Lingling Song

Rui Lu

Yichen Zhang

Yuchong Hu

Dan Feng

COM-BNN: A Configurable Low Power MRAM-Based Computing-in-Memory Accelerator for Binary Convolutional Computations

Research Manuscript

5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionIn resource-constrained tiny edge devices like MCUs, deploying data/compute-intensive AI like CNNs is challenging. Compute-in-Memory (CIM) and Binary Neural Networks (BNN) offer promising solutions by reducing memory access and simplifying computations. We propose RES-BNN, a lightweight, reconfigurable accelerator integrating MRAM-based CIM with serial BNN computation. It introduces a temporal reconfigurable input mechanism and an Integrate-and-Fire adder for serial MAC operations, plus an Exact Result Inferring method for efficient binary convolutional computations. RES-BNN achieves up to 85% energy and 83% power reduction over ADC-based CIM baselines, and enables dynamic latency-power tradeoffs, dropping power to 0.03% in serial mode for edge adaptability.

People

Keni Qiu

Can Gao

Xuejin Li

Chuting Xu

Li Su

Kaiwei Zou

Yongpan Liu

Compact ML-Based Glitch Propagation Modeling of Standard Cells

Work in Progress

6:36pm - 6:37pm PDT Monday, July 27 Exhibit Hall

DescriptionWith continuous technology scaling, accurate and efficient glitch modeling is critical for designing energy-efficient and reliable ICs. In this work, we present a new gate-level approach for glitch propagation modeling, utilizing Artificial Neural Networks (ANNs) to estimate the key glitch shape characteristics, propagation delay, and power dissipation. Moreover, we introduce a framework that automates ANN generation and integrates them into standard cell libraries, exploring different architectures to balance accuracy and memory footprint. The proposed framework employs efficient techniques to generate realistic input glitch waveforms, reduce characterization effort, and improve model accuracy, memory efficiency, and robustness. Experimental results on gates implemented in 7 nm FinFET and 45 nm bulk CMOS technologies indicate that our models exhibit a strong correlation with SPICE, achieving a mean R2 score of 0.995 across all gates and process, voltage, and temperature corners while maintaining low memory demands. Furthermore, validation on paths extracted from real circuits confirms our models' high accuracy and performance. Thus, our approach could enable accurate full-chip glitch analysis and effectively guide glitch reduction techniques.

People

Anastasis Vagenas

Dimitrios Garyfallou

George Stamoulis

Compart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning

Research Manuscript

3:54pm - 4:06pm PDT Tuesday, July 28 Mtg Room 203AB

EDA

EDA7-II. Physical Design and Verification

DescriptionHypergraph partitioning is a critical step in the design of complex embedded systems, essential for optimizing task mapping on heterogeneous MPSoCs and enabling multi-FPGA prototyping.
Many existing methods rely on community detection to identify modules with dense internal and sparse external connections, typically utilizing them to constrain the coarsening phase—a widely adopted paradigm. In this work, we propose ComPart, a generalized framework that integrates diverse community detection methods to uncover high-quality clusterings throughout the post-coarsening stages (i.e., initial partitioning and uncoarsening). These discovered clusterings serve as distinct structural guides, enabling the refinement process to identify superior partitioning solutions. Our framework offers two key advantages: (1) it establishes a new paradigm that leverages community structures detected during uncoarsening to escape local optima and explore globally meaningful solution subspaces, transcending the limitations of standard local refinements; and (2) it flexibly accommodates both existing and future community detection methods. Furthermore, we theoretically generalize locally-dense decomposition—originally from graphs—to the hypergraph domain. We provide the formal extension and necessary proofs to apply this technique to hypergraphs, marking its first application in hypergraph partitioning. Specifically, we utilize this rigorously derived decomposition to guide the initial partitioning phase toward superior starting points. Experimental results on standard benchmarks demonstrate that our method consistently outperforms state-of-the-art methods in solution quality.

People

Yugao Zhu

Hong Kong University of Science and Technology (HKUST)

Zhicheng Guo

Hong Kong University of Science and Technology (HKUST)

Yuchao Wu

Hong Kong University of Science and Technology (HKUST)

Mengming Li

Jing Wang

Hong Kong University of Science and Technology (HKUST)

Zhiyao Xie

Hong Kong University of Science and Technology (HKUST)

Research Manuscript

Compilation Pipeline for Predicting Algorithmic Break-Even in an Early-Fault-Tolerant Surface Code Architecture

2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 203AB

Design

Quantum

DES6. Quantum Computing

DescriptionRecent experimental progress in surface-code hardware, including
demonstrations of break-even logical memory on devices with up to
hundreds of physical qubits, has materially advanced the prospects
for fault-tolerant quantum computation. This progress creates ur-
gency for compilation workflows that directly target the forth-
coming generation of devices with thousands of physical qubits,
for which algorithm execution becomes practical. We develop a
pipeline for compiling logical algorithms to physical circuits imple-
menting lattice surgery on the surface code, and use this pipeline
to identify the requirements for achieving algorithmic break-even—
where quantum error correction improves the performance of a
quantum algorithm—for the quantum approximate optimization
algorithm (QAOA). Our pipeline integrates several open-source
software tools, and leverages recent advances in error-aware uni-
tary gate synthesis, high-fidelity magic-state production, and the
calculation of correlation surfaces in the surface code. We apply our
pipeline by performing classical simulations of physical Clifford
proxy circuits produced by our pipeline, and find that 5-qubit QAOA
can reach algorithmic break-even with 2517 physical qubits (surface
code distance 𝑑 = 11) at physical error rates of 𝑝 = 10−3, or 1737
physical qubits (𝑑 = 9) at 𝑝 = 5 × 10−4. Our work thereby identifies
conditions for achieving algorithmic break-even with near-term
quantum hardware and paves the way towards an end-to-end com-
piler for early-fault-tolerant surface code architectures

People

Sivaprasad Omanakuttan

Research Manuscript

Compilation Tells Energy: Rethinking Power Modeling for DNN Accelerator Agile Design

4:54pm - 5:06pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionRTL generators enable agile design of DNN accelerators, but the lack of early-stage power feedback forces designers to discover energy inefficiencies only after costly synthesis. Existing arch-level simulator-based approaches fall short for agile workflows: they require expertise and effort incompatible with rapid iteration. While machine learning struggles to capture software-hardware coupling, we reveal a key insight: compilation tells energy. Compiler toolchains in RTL generators already fuse workload and hardware characteristics—the coupling determining power. By extracting features from compiler IRs and multi-task learning, our methodology achieves practical accuracy through push-button workflows requiring no expertise. Validation on Gemmini and hls4ml demonstrates broad applicability, enabling true power-aware agile design.

People

Donger Luo

Shanghaitech University

Yihong Yi

Xinheng Li

Shanghai Tech

Tianyi Li

Jianwang Zhai

Compiler Framework for Directional Transport in Zoned Neutral-Atom Systems with AOD Assistance: A Hybrid Remote CZ Approach

Research Manuscript

1:55pm - 2:08pm PDT Tuesday, July 28 Mtg Room 203AB

Design

Quantum

DES6. Quantum Computing

DescriptionWe present a directional-transport (DT)-based remote CZ gate and compiler for zoned neutral-atom arrays that overcomes movement-bound entanglement limitations. Current AOD-based shuttling faces row/column non-crossing constraints, device-speed limits, and FOV/NA-restricted range—bottlenecks for long-distance connectivity. Our approach reserves AODs for channel setup and micro-tuning while making DT the default for remote entanglement. Under antiblockade, a detuning-modulated pi-pulse sequence drives directional transport of a Rydberg excitation along a dynamic and resettable ancilla corridor, realizing a CZ gate between stationary, non-adjacent qubits. This cuts entangling-stage duration by approximately 50% -90% versus AOD-only baselines and enables long-distance connectivity beyond objective-limited shuttling.

People

Lingyi Kong

Chen Huang

Zhemin Zhang

Yidong Zhou

Rutgers University

Xiangyu Ren

University of Edinburgh

Shaochen Li

Zhiding Liang

COmPOSER: Circuit Optimization of mm-Wave/rf Circuits with Performance-Oriented Synthesis for Efficient Realizations

Research Manuscript

4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionThis work presents COmPOSER, an open-source, end-to-end framework for RF/mm-wave design automation that translates target specifications into optimized circuits with layouts. It unifies schematic synthesis, layout generation for actives and passives, and placement/routing, incorporating physics-based equations and machine-learning-driven electromagnetic models.
Based on post-layout validation on multiple LNAs and PAs operating at up to 60GHz in a commercial 65nm process-kit, COmPOSER meets performance targets, comparable to expert manual designs, while delivering a 100-300x productivity gain.

People

Subhadip Ghosh

Surya Srikar Peri

Indian Institute of Technology, Madras

Ramprasath S

Sosina Berhan

Endalk Gebru

Ramesh Harjani

Sachin S. Sapatnekar

Comprehensive Physical Verification Approach for Heterogeneous 2.5/3D Integration

Engineering Presentation

10:30am - 10:45am PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionAs semiconductor technology advances, the industry is moving from traditional monolithic SoC designs to heterogeneous integration enabled by advanced 2.5D and 3D IC packaging. These architectures deliver higher performance, improved power efficiency, and greater functionality by combining multiple dies in a single package. However, this shift introduces complex physical verification challenges that conventional single-die methodologies cannot address.
Traditional techniques like DRC and LVS, designed for monolithic SoCs, are inadequate for multi-die integration, which involves new elements such as vertical interconnects, micro-bumps, TSVs, and interposers with unique geometric and electrical constraints. Simple XOR-based checks fail to accurately validate bump alignment, and multi-die LVS is complicated by the lack of foundry-provided rule decks, requiring custom solutions and multiple iterations—leading to time-consuming, error-prone flows and schedule risks.
To overcome these challenges, a scalable 3D physical verification methodology is essential. Leveraging tools like Calibre 3DStack enables precise die-to-die connectivity checks, robust micro-bump and TSV alignment validation, and efficient hierarchical verification flows. This approach minimizes iterations, reduces risk, and supports next-generation heterogeneous integration by enabling hierarchy reuse for improved design efficiency and scalability.

People

NagaMalleswari Metla

Ravali Pagidooju

KalyanaKumar Amruthuluri

Comprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification Methodology

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionPower systems are a critical component of the modern system on chips (SoCs) and present formidable mixed-signal verification challenges due to increasing design complexity and diverse power requirements. Designers face hurdles like managing numerous power domains, operating modes, intricate power sequencing, state transitions, and critical analog-digital interactions at domain boundaries. Furthermore, verifying complex Unified Power Format (UPF) strategies for isolation and retention adds significant complexity. Traditional full SPICE simulations for comprehensive power state validation are prohibitively time-consuming, often requiring weeks of runtime and delaying time-to-market by months.

To address these profound limitations, Microchip, in collaboration with Siemens EDA, developed an optimized mixed-signal verification methodology for comprehensive SoC power system validation. This innovative approach, leveraging Siemens EDA's AI accelerated Solido Simulation Suite employs a digital-on-top strategy, seamlessly integrating high-fidelity SPICE views for critical analog modules with high-performance digital simulation for the broader RTL design and UPF strategies.

In this presentation, we will detail this novel methodology and demonstrate how it achieves more than 22X runtime reduction for power states simulation without compromising accuracy, thereby enabling rapid and accurate verification of critical power management scenarios. This approach leads to improving verification coverage, Silicon quality and accelerating time-to-market for robust, energy-efficient SoCs.

People

Research Special Session

Content Meets Compute: How Disney+ Approaches Next-Gen XR Hardware Platforms

2:15pm - 3:00pm PDT Tuesday, July 28 Mtg Room 201A

DescriptionSince its inception, Disney has been at the forefront of adopting hardware that bridges the gap between imagination and reality. As Extended Reality (XR) hardware reaches new heights of graphical and computational fidelity, the boundary between the viewer and the narrative is dissolving. This talk explores Disney's strategic approach to the XR landscape, focusing on how we leverage next-generation hardware to transform Disney+ into a spatial entertainment hub. Using our work with Apple Vision Pro and Meta Quest as a case study, we examine how we moved beyond traditional 2D interfaces to develop a "Spatial UI" that prioritizes immersion and presence. We will discuss how the immense compute power of modern XR devices allows for innovations previously impossible on mobile or living room screens, such as photorealistic environments and high-bitrate 3D movie playback. These technical leaps continue to drive towards a future where Disney stories are no longer confined to a screen; they unfold in real time around the audience. This session offers a deep dive into the process of creating new experiences on cutting edge hardware platforms.

People

Daniel Baker

Disney+ | Interactive & Immersive Experiences

Research Manuscript

COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging

4:42pm - 4:54pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionAdvanced 3D and 3.5D IC packaging significantly improves integration density but elevates thermal management challenges due to cross-layer heat coupling and complex cooling structures. Traditional solvers deliver high fidelity but are too slow for iterative design flows, while existing learning-based methods either fail to capture inter-die thermal coupling or treat cooling structures as static components, limiting their applicability in real packaging co-design scenarios.
In this work, we introduce COOL, a cooling-aware point transformer framework that represents heterogeneous assemblies (dies, interposers, TIMs, heat spreaders) as annotated 3D point clouds embedding geometric, material, and power attributes. COOL explicitly encodes geometric boundaries and cooling structures, and introduces a physics-informed boundary condition (PI-BC) loss to enforce thermal consistency at material interfaces and cooling boundaries. Extensive experiments demonstrate that COOL achieves a remarkable 2.4% NMAE on our constructed benchmark of multi-package thermal designs, substantially outperforming existing learning-based approaches while providing over 15.7× speedup compared to commercial FEM solvers.

People

Yao Lu

Hong Kong University of Science and Technology (HKUST)

Zhicheng Guo

Hong Kong University of Science and Technology (HKUST)

Qijun Zhang

Hong Kong University of Science and Technology (HKUST)

Shang Liu

Hong Kong University of Science and Technology (HKUST)

Wenji Fang

Hong Kong University of Science and Technology (HKUST)

Wenkai LI

Hong Kong University of Science and Technology (HKUST)

Zhiyao Xie

DAC Pavilion Panel

Cooley's DAC Troublemaker Panel

3:00pm - 3:45pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Design

EDA

Design

DescriptionCome watch the EDA troublemakers answer the edgy, user-submitted questions about this year's most controversial issues! It's an old-style open Q&A from the days before corporate marketing took over every aspect of EDA company images.

People

Research Manuscript

Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning

2:34pm - 2:47pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionFull-chip inverse lithography technology (ILT) is critical for semiconductor manufacturing but remains difficult to maintain global solution integrity. While gradient fusion flow mitigates mask stitching artifacts, it suffers from a uniform, unweighted update policy. We identify heterogeneous smoothness and inter-clip coupling as key factors that create conflicts between local clip convergence and global integrity. We propose a coordinated clip-wise gradient scheduling framework trained via policy learning to resolve these conflicts. The method constructs a full-chip state by combining per-clip static geometric descriptors and dynamic optimization signals, and aggregates them with a graph neural network to encode inter-clip relations. From this state, a scheduler generates continuous, correlated gradient weights learned with flow-matching policy gradients, capturing cross-clip dependencies. On industry-scale layouts, the approach outperforms state-of-the-art full-chip ILT baselines.

People

Ziyang Yu

Shuo Yin

Su Zheng

The Hong Kong University of Science and Technology (Guangzhou)

Xiaoxiao Liang

Yuzhe Ma

The Hong Kong University of Science and Technology (Guangzhou)

CORE: Compact, Optimized, and Resource-Efficient Compute Engine for FP-INT GEMM Acceleration with Binary Coding Quantization

Research Manuscript

11:30am - 11:42am PDT Tuesday, July 28 Mtg Room 101A

AI4-II. AI/ML Architecture Design

DescriptionRecent advances in large language models (LLMs) have driven exponential growth in parameter counts, amplifying memory footprints and creating acute computational bottlenecks.
Weight-only quantization is a common mitigation because weights dominate storage and incur less accuracy degradation than activation quantization. However, it leaves activations in floating point (FP), forcing FP execution whose area and energy costs far exceed those of integer (INT) compute. To address this limitation, binary coding quantization (BCQ) lowers this cost by replacing many FP multiplies with FP additions, but still requires FP multiplications for scaling factors and suffers from limited representational capacity, causing non-trivial accuracy loss. In this paper, we propose a sum-of-power-of-two scaling factor–based BCQ (SS-BCQ) that approximates FP scaling factors with a small set of power-of-two terms, eliminating FP multiplications (shift–add only) while preserving accuracy. To efficiently realize SS-BCQ in hardware, we introduce CORE, a fully pipelined FP–INT general matrix-matrix multiplication (GEMM) engine. CORE features (i) an adaptive data-mapping module that computes optimized block-wise activation scales to minimize scaling operations, and (ii) an extra processing unit that allocates a small subset of processing elements to high-importance weights to retain accuracy at low cost. Evaluated on the OPT-6.7B model, SS-BCQ reduces perplexity by 3.14 compared with prior BCQ methods. Implemented in CORE, our approach achieves up to 1.41x higher area efficiency (TOPS/mm^2) and 2.18x higher energy efficiency (TOPS/W) than state-of-the-art FP–INT accelerators, enabling a homogeneous low-precision execution path for on-device LLMs.

People

Chaewon Park

Seoul National University of Science and Technology

Inseong Hwang

Seoul National University of Science and Technology

Beom Jin Kang

Seoul National University of Science and Technology

Hyun Kim

Seoul National University of Science and Technology

Engineering Presentation

Correct-by-Construction Framework for Robustness Against Divergent Voltage Drops and High Clock Divergence

10:45am - 11:00am PDT Tuesday, July 28 Seaside RM 7

EDA

Security

DescriptionLimitations in Sign-off Methodology:
Traditional STA corner selection 10% lower STA corner from PMIC voltage is selected- design is constantly optimised for 10% lower voltage, thereby failing to build margin against differential drop.
IR aware STA does not account timing path's geometric imbalances (logic depths), net dominated interconnect skews (net delays & metal layer variation) - all dominant in advanced process nodes. Furthermore, this is workload dependent: fixing IR STA violations does not build margins on unseen vectors.
Frequent Silicon issues due to these gaps:
Low voltage mode scan shift Vmin jumps need to meet slack on paths which become exponentially sensitive to voltage gradients. Even small differential IR drops (capture & launch traversing through contrasting IR hotspot & cool regions) cause catastrophic slack loss
High divergence paths with structural imbalances-where clock paths are net-dominated & are operated at high speeds often fail to meet hold timing, despite good pre-silicon margins due to high interlayer metal-sheet & via resistances in lower process nodes.
Additionally, there is considerable PPA impact -higher dynamic & leakage power in clock & data paths respectively in divergent paths. Our proposed solution aims to address above gaps.

People

Engineering Poster Gladiator

Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition

5:22pm - 5:30pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionIdentifying recurring sub-circuits within large transistor-level designs is a common requirement in circuit analysis and verification. Traditional approaches rely on exact subgraph isomorphism, requiring identical structure and attributes between a pattern and a design. However, real designs often include small structural variations introduced by incremental changes, optimizations, or renaming, causing exact matching methods to miss relevant instances and increasing manual analysis effort.
This work presents a scalable framework for partial subgraph matching that quantifies structural similarity rather than enforcing exact equivalence. Circuits are represented as attributed graphs, and matching is formulated as an injective optimization problem using a cost-based graph edit distance. The cost function captures label mismatches, unmatched nodes, and missing or extra edges, enabling fine-grained assessment of near-miss matches. To address the computational complexity of partial matching, the framework combines biased candidate subgraph sampling with an efficient approximation strategy based on greedy initialization and iterative refinement.
The approach produces ranked candidate matches along with detailed, interpretable difference reports that highlight structural deviations between circuits. Experimental results demonstrate predictable runtime scaling with candidate budget and consistent behavior across a range of circuit patterns. The framework also establishes a foundation for automated tuning of cost parameters and learning-based candidate filtering.

People

Research Manuscript

CoX-MoE: Coalesced Expert Execution for High-Throughput MoE Inference with AMX-Enabled CPU-GPU Co-Execution

4:10pm - 4:23pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionThe Mixture-of-Experts (MoE) architecture improves computational efficiency via sparse expert activation, but throughput-oriented inference faces substantial GPU memory pressure due to a significant parameter size and intermediate data. Prior works attempt to mitigate this using expert offloading with micro-batching or by offloading computation to the CPU. However, the fragmented workload resulting from micro-batching degrades operational intensity, causing expert execution to become memory-bound. Meanwhile, CPU offloading is constrained by slow PCIe transfers and its limited applicability to attention computation in the decode stage. Consequently, these inefficiencies prevent effective system utilization, severely restricting the end-to-end throughput of MoE inference.

To address these challenges, this paper proposes CoX-MoE, an Advanced Matrix Extensions (AMX)–enabled CPU–GPU collaborative system that comprehensively optimizes MoE inference by combining coalesced expert execution with strategic workload orchestration for higher throughput. CoX-MoE introduces (i) a coalescing-aware orchestration policy to jointly optimize resource allocation by adopting ordinary batch, instead of micro-batch, for expert computation and selective attention offloading, and (ii) a static expert-aware stratification scheme that pre-assigns frequently activated experts to the GPU, mitigating PCIe transfer overhead and balancing workload for the CPU and GPU during inference. Compared to state-of-the-art frameworks, CoX-MoE delivers significant gains, achieving up to 7.1x and 2.4x higher throughput than FlexGen and MoE-Lightning, respectively.

People

Research Manuscript

CPA-BNN: A Secure and Efficient CIM and PUF Architecture for BNN Accelerator

4:30pm - 4:42pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionBinary neural networks (BNNs) have emerged as promising models for lightweight intelligent inference by binarizing inputs and weights. Compute in memory (CIM) architectures, which reduce data movements through in-situ operations, have become a strong candidate for BNN accelerators. However, prior works often overlook the security of the model, leaving BNN weights exposed in memory cells and vulnerable to threats such as cloning, tampering, and reverse engineering. This work proposes CPA-BNN, a secure BNN CIM architecture based on resistive random access memory (RRAM). We propose a 4T2R RRAM cell design which implements in-situ encryption and ciphertext convolution operations to protect the weights. In addition, an in-memory batch normalization (BN) scheme is proposed to optimize area overhead and improve compute density. Besides, we propose an intrinsic physical unclonable function (PUF) entropy extraction method and a current tilt-based masking stratege, enabling reliable key extraction within a unified array. The results show that CPA-BNN achieves ~100% key reliability and effectively prevents model attacks. Compared to state-of-the-art SRAM/NVM BNN schemes, CPA-BNN achieves >1.4× compute density and >1.6× storage density improvement.

People

Engineering Presentation

CPPR-Aware Tap-Point Reassignment in Flex-H and Multi-Point CTS for Timing Closure in High-Performance Cores

2:30pm - 2:45pm PDT Wednesday, July 29 Seaside RM 7

EDA

DescriptionHigh-performance and high-frequency cores operate with aggressive clock targets, making timing closure highly sensitive to Common Path Pessimism Removal (CPPR). While advanced clock tree synthesis (CTS) techniques such as Flex-H and multi-point CTS effectively reduce skew and clock latency, they typically rely on static, geometry-based sink assignment, limiting achievable clock–data path correlation and CPPR on critical timing paths.

This work proposes a CPPR-aware tap-point sink reassignment methodology that selectively reassigns launch and capture sinks at clock tap points to maximize shared clock path length without modifying clock topology, buffer depth, or skew constraints. A script-driven framework identifies timing-critical tap-point pairs, evaluates reassignment opportunities based on timing impact, and integrates seamlessly with standard CTS optimization flows.

Experimental results on high-performance core designs demonstrate up to 25% reduction in setup total negative slack and up to 43% improvement in register-to-register setup TNS, along with ~13% improvement in hold TNS, achieved by reassigning a limited number of sinks. The proposed approach incurs negligible power and physical impact, enabling robust timing closure in advanced high-frequency designs where CPPR is often the primary remaining optimization lever.

People

Omang Mahure

CPW-SMO: Generating Mask Sets and Common Source for Maximum Common Process Window

Research Manuscript

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionSource Mask Optimization (SMO), as a key enabler in Design-Technology Co-Optimization (DTCO), plays a vital role in enlarging the process window (PW) for advanced technology nodes and PDK development. Conventional SMO relies heavily on iterative optimization using lithography models to obtain a single source-mask pair for improved PW. In full-chip applications, however, a set of critical patterns are co-optimized under a common source, forming a one-source-to-many-masks optimization paradigm for maximum common process window (CPW). To overcome the limitations of existing methods, we introduce CPW-SMO, a novel single-shot generative flow that simultaneously generates an optimal source and a set of corresponding mask patterns using set-based attention mechanisms. Our approach formulates the source and mask patterns as a unified set and employs a highly parallelized generative simulator to enable efficient training. By transforming multi-objective, non-differentiable CPW into a single-objective CPW preference penalty and optimizing generators through an SMO-aware gradient response method, CPW-SMO achieves nearly 2x CPW compared to state-of-the-art methods, while delivering ~200x speedup in runtime. These improvements significantly boost the practicality and effectiveness of SMO for holistic lithography applications.

People

Hongquan He

Ziyang Yu

Shanghai Optoelectronics Science and Technology Innovation Center

Jiaqi Liu

Jingyi Yu

Hao Geng

CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval

Research Manuscript

1:30pm - 1:42pm PDT Monday, July 27 Mtg Room 202C

Design

DES2B-I. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionDeploying Retrieval-Augmented Generation (RAG) on edge devices is in high demand, but is hindered by the latency of massive data movement and computation on traditional architectures. Compute-in-Memory (CiM) architectures address this bottleneck by performing vector search directly within their crossbar structure. However, CiM's adoption for RAG is limited by a fundamental ``representation gap,'' as high-precision, high-dimension embeddings are incompatible with CiM's low-precision, low-dimension array constraints. This gap is compounded by the diversity of CiM implementations (e.g., SRAM, ReRAM, FeFET), each with unique designs (e.g., 2-bit cells, 512x512 arrays). Consequently, RAG data must be naively reshaped to fit each target implementation.
Current data shaping methods handle dimension and precision disjointly, which degrades data fidelity. This not only negates the advantages of CiM for RAG but also confuses hardware designers, making it unclear if a failure is due to the circuit design or the degraded input data. As a result, CiM adoption remains limited. In this paper, we introduce CQ-CiM, a unified, hardware-aware data shaping framework to jointly perform Compression and Quantization, flexibly shaping data to fit various CiM designs. To the best of our knowledge, this is the first work to shape data for comprehensive CiM usage on RAG.

People

North Dakota State University

Umamaheswara Tida

North Dakota State University

Kai Ni

University of Notre Dame

X. Sharon Hu

University of Notre Dame

Research Manuscript

Credix: A Credit-Driven Distributed Buffer Management for Large-Scale Switching Chips

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionWith the scaling of switching chips, modular architectures are becoming mainstream.
As a result, buffers become physically distributed across tiles, leading to poor utilization under imbalanced traffic.
To address this, we propose CrediX, a lightweight dynamic buffer management mechanism that aggregates distributed buffers into region-based shared pools and allocates usage on demand through a Regional Credit Allocator (RCA).
The design leverages existing credit-based flow control and preserves packet ordering via a simple VC-to-path mapping.
Evaluations show that CrediX reduces backpressure by 65.6% under synthetic Hotspot traffic and mitigates severe hotspot occupancy in a realistic workload.

People

Xu Wang

Lanzhou University

Yang Zhang

Tsinghua University & Zhongguancun Laboratory

Danfeng Shan

Xi'an Jiaotong University

Fengyuan Ren

Lanzhou University&Tsinghua University

Engineering Presentation

Crosstalk Effect Prediction and Optimization for Detail Routing Using CNN Models and Reinforcement Learning Flow Framework

2:15pm - 2:30pm PDT Wednesday, July 29 Seaside RM 7

EDA

DescriptionWith the increasing complexity of high-performance VLSI designs at advanced technology nodes below 2 nm, crosstalk-induced signal integrity and timing violations have emerged as major challenges in physical implementation flows. Traditional crosstalk analysis is typically performed after detailed routing, making post-route fixes computationally expensive and time-consuming, often leading to prolonged design closure cycles. This work proposes a machine learning–driven framework for the early prediction of crosstalk effects prior to detailed routing and guiding Router to prevent crosstalk effect. The approach leverages deep convolutional neural networks (CNNs) to extract spatial and physical features and generate a crosstalk hotspot map that accurately identifies crosstalk-critical nets. To further enhance optimization, the CNN-based predictor is integrated with a reinforcement learning–based Cadence Cerebrus flow to guide routing decisions such as net ordering and spacing. Experimental results demonstrate that, after training on 40 Cerebrus regression runs, the proposed model achieves up to 74% prediction accuracy and delivers up to 15% improvement in setup total negative slack (TNS). The trained model is reusable across similar designs within the same technology node, yielding consistent PPA improvements and significantly reducing overall design turnaround time. The proposed framework enables efficient pre-routing signal integrity analysis, minimizes costly post-routing iterations, and improves timing closure, making it well suited for next-generation VLSI physical design flows.

People

Loknath Moogi

Mohit Gupta

Swathi Gangesetti

Ayush Khare

Crosstalk Hotspot Map Creation at Placement Stage Using CNN UNET Prediction Model

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionEarly identification of crosstalk-affected regions is critical for achieving timing closure in advanced VLSI designs. This paper presents a framework for the pre-routing prediction of coupling-induced timing and signal integrity risks within the physical design flow. The proposed method introduces a novel Coupling Capacitance Estimator (CCE) to accurately estimate coupling effects arising from neighboring interconnects.
The framework extracts multi-channel spatial features from the Innovus placement database, including congestion, pin density, timing criticality, routing density, macro blockages, and coupling characteristics, and feeds them into a CNN-based U-Net architecture to generate high-resolution crosstalk hotspot maps. Owing to its encoder–decoder structure with skip connections, the U-Net model preserves fine-grained spatial information and enables precise localization of crosstalk-sensitive regions in dense layouts.
Experimental evaluation across multiple design blocks demonstrates that the generated heatmaps closely correlate with post-routing signoff results, indicating strong predictive fidelity. By enabling reliable pre-routing crosstalk analysis, the proposed framework reduces dependence on costly post-routing iterations and supports improved timing closure, reduced design turnaround time, and enhanced physical implementation efficiency, making it well suited for advanced technology nodes.

People

Loknath Moogi

Crosstalk Timing Prediction via Graph Prompt Learning in Aggressor-Victim RC Networks

Research Manuscript

12:16pm - 12:30pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA3. Timing Analysis and Optimization

DescriptionWith continued technology scaling, crosstalk effects have become critical for timing closure. Existing graph learning-based timing models fail to accurately predict crosstalk timing due to limited modeling of coupling behaviors and multi-net interactions. We introduce a graph prompt learning framework featuring a dual-level prompt architecture. Node-level prompts capture fine-grained coupling effects while subgraph-level prompts model holistic multi-net interactions, effectively adapting pre-trained models. Experimental results demonstrate precise crosstalk timing prediction, consistently outperforming existing methods across benchmark designs.

People

Cryozip: An Efficient Cryogenic Compressor for Quantum Error Correction Syndromes

Qing He

Tongji University

Research Manuscript

10:56am - 11:10am PDT Tuesday, July 28 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionScaling fault-tolerant quantum computing is increasingly constrained by the limited bandwidth and power budget across the 4\,K-room temperature (RT) interface. We present CryoZip, a cross-layer cryogenic compression framework that cooperates with an lightweight in-house quantum error correction (QEC) predecoders to reduce syndrome transmission under realistic, circuit-level noise. CryoZip targets sparse syndrome vectors with a sliding-window compression architecture sized under strict decoding-latency constraints to maximize energy efficiency. We implement and evaluate the design in 22\,nm FDSOI characterized at 4\,K, using vector-based power, performance, and area analysis to obtain realistic hardware data. CryoZip achieves up to 48.3$\times$ compression---1.81$\times$ higher than state-of-the-art compressors---across various QEC codes; when paired with the predecoder it yields over 14,238.86$\times$ bandwidth reduction (48.3$\times$ without predecoding), and delivers 3.97-25.74$\times$ energy savings for cryo-to-RT links alone, rising to 42.19$\times$ when accounting for predecoding and realistic QEC interface overheads.

People

Guanchen Tao

Alexander Knapen

Jacob Mack

Gokul Subramanian Ravi

Qirui Zhang

Mehdi Saligane

Brown University

Dennis Sylvester

Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle

Research Manuscript

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 101B

AI2-I. AI/ML Algorithms and Models

DescriptionChain-of-Thought (CoT) reasoning in large language models (LLMs) significantly improves accuracy on complex tasks, yet incurs excessive memory overhead due to the long think stage sequences stored in the Key-Value (KV) cache. Unlike traditional generation tasks where all tokens are uniformly important, CoT emphasizes the final answer, rendering conventional KV compression strategies ineffective. In this paper, we present Crystal-KV, an efficient KV cache management framework tailored for CoT reasoning. Our key insight is the answer-first principle. By mapping answer preferences into think-stage attention map, we distinguish between SlipKV, which mainly maintains the reasoning flow but may occasionally introduce misleading context, and CrystalKV, which truly contributes to the correctness of the final answer. Next, we propose an attention-based Least Recently Frequently Used algorithm. It precisely identifies when a SlipKV entry's utility expires and evicts it, retaining CrystalKV without disrupting reasoning flow. Finally, we introduce an adaptive cache budget allocation algorithm. Based on the dynamic proportion of CrystalKV, it estimates the importance of each layer/head and adjusts the KV cache budget during inference, amplifying critical components to improve budget utilization. Results show that Crystal-KV achieves state-of-the-art KV cache compression, significantly improves throughput, and enables faster response time, while maintaining, or even improving, answer accuracy for CoT reasoning.

People

Zihan Wang

Cheng Tang

Cheng Li

Chao Wang

Ctxmem: OS-Hardware Co-Designed Tiered Memory with DRAM-SSD Hybrid CXL Devices

Research Manuscript

2:47pm - 3:00pm PDT Tuesday, July 28 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionThe "memory wall'" problem continues to constrain modern applications, making scalable memory expansion via Compute Express Link (CXL) increasingly critical. While DRAM-Flash hybrid CXL systems offer a capacity solution, their performance remains hampered by inefficient access models.

This paper presents CtxMem, an OS-hardware co-designed memory expansion system built on byte-addressable CXL interconnect and inexpensive flash storage. Unlike existing approaches, CtxMem introduces an asynchronous page fault-based mechanism that offloads the entire data plane of page fault handling to the CXL device. This is achieved through three key innovations: a dynamic direct-mapped cache that maximizes DRAM utilization, a lightweight hardware profiling unit enabling accurate and rapid hot/cold page identification with minimal overhead, and a OS-hardware co-designed page fault handling procedure that efficiently offloads data migration. Our GEM5-based evaluation shows CtxMem outperforms conventional CXL-SSD by 1.4x in execution time and doubles system throughput, demonstrating efficient large-scale memory expansion.

People

Research Manuscript

Cupilot: A Strategy-Coordinated Multi-Agent Framework for CUDA Kernel Evolution

1:42pm - 1:55pm PDT Monday, July 27 Mtg Room 101A

AI2-I. AI/ML Algorithms and Models

DescriptionOptimizing CUDA kernels is a challenging and labor-intensive task, given the need for hardware-software co-design expertise and the proprietary nature of high-performance kernel libraries.
While recent large language models (LLMs) combined with evolutionary algorithms show promise in automatic kernel optimization, existing approaches often fall short in performance due to their suboptimal agent designs and mismatched evolution representations.
This work identifies these mismatches and proposes cuPilot, a strategy-coordinated multi-agent framework that introduces strategy as an intermediate semantic representation for kernel evolution.
Key contributions include a strategy-coordinated evolution algorithm, roofline-guided prompting, and strategy-level population initialization.
Experimental results show that the generated kernels by cuPilot achieve an average speed up of 3.09$\times$ over PyTorch on a benchmark of 100 kernels.
On the GEMM tasks, cuPilot showcases sophisticated optimizations and achieves high utilization of critical hardware units.
The generated kernels are open-sourced at https://anonymous.4open.science/r/cuPilot-Kernels-1656.

People

TsingMicro Tech. Ltd.

Lin Ma

TsingMicro Tech. Ltd.

Custom Implementation of High-Speed Digital Blocks Using Virtuoso Studio

Engineering Presentation

11:45am - 12:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

Systems

DescriptionHigh-speed digital blocks integrated within traditional Place & Route flows pose verification and implementation challenges that analog-centric methodologies cannot fully address. As process technologies scale and timing margins shrink, these blocks exhibit strong sensitivity to parasitics, layout-dependent effects, and high-frequency interactions, demanding enhanced automation and predictability. While the Cadence Virtuoso studio provides unmatched control for custom transistor-level design and leverages Cadence Innovus for digital automation, it lacks capabilities for automated Structured Data Path (SDP) file and routing constraint creation from source.

This work introduces a unified implementation approach that bridges this gap by enabling SDP-based placement for custom standard cells with auto-generating SDP file from schematic or Verilog, and creating routing constraints such as matching and shielding based on net prefixes/suffixes from schematic/Verilog. The methodology improves design scalability, reduces manual effort, and strengthens flow automation for high-speed digital blocks. By combining Virtuoso studio custom design flexibility with Innovus-driven automation, the proposed solution delivers a robust, layout-aware implementation flow suited for next-generation high-performance SoC and PHY architectures.

People

Pratik Korde

Sumanth S

DAP: A Software/hardware Co-Design for Accelerating Multi-Chip-Based Distributed Sparse-Dense Matrix Multiplication

Kishan Chanumolu

Micron

Research Manuscript

3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionSparse-dense matrix multiplication (SpMM) is a core component in many critical applications such as deep learning and scientific computing. Existing SpMM accelerators employ the COO format to compress sparse matrices and rely on high-bandwidth off-chip memory for performance gains. However, four major challenges remain unaddressed: 1) Fixed 2-D partitioning strategies lead to workload imbalance among processing nodes due to irregular distribution of non-zero elements in sparse matrices. 2) Redundant metadata from the COO format results in a communication bottleneck that hinders the scalability of existing SpMM accelerators. 3) To accommodate irregular memory access patterns, the use of multiple data replicas significantly increases the pressure on on-chip storage resources. 4) Handling RAW hazards from floating-point adders in software incurs substantial pre-processing overhead. To address these challenges, we propose DAP, the first 2-D multi-chip-based architecture composed of dedicated accelerators, and SPU, a novel communication-friendly SpMM accelerator. To mitigate load imbalance caused by irregular non-zero distribution, we design a two-level matrix partitioning framework that effectively balances workloads across nodes in a 2-D computing array, achieving a performance improvement of 1.43x. Furthermore, the SPU adopts CSC over COO format to reduce communication traffic. SPU also minimizes redundant on-chip storage from data replication, with only a 0.067x performance penalty due to memory access conflicts. By employing a reservation buffer, the SPU resolves RAW dependencies without time-consuming pre-processing. Our simulation-based evaluation demonstrates DAP achieves geometric mean throughputs of 2.69x relative to NVIDIA A100 GPU at 500MHz frequency.

People

Xiuhua Yang

University of Macau

Hao Jia

Guangdong Institue of Intelligence Science and Technology

Chen Ding

Guangdong Institue of Intelligence Science and Technology

Haoming Chu

Guangdong Institue of Intelligence Science and Technology

Yufan He

Guangdong Institue of Intelligence Science and Technology

Lirong Zheng

Guangdong Institue of Intelligence Science and Technology

Ning Ma

Guangdong Institue of Intelligence Science and Technology

Yuxiang Huan

Guangdong Institue of Intelligence Science and Technology

Research Manuscript

DAPA: Distribution Aware Piecewise Activation Functions for On-Device Transformer Inference and Training

10:42am - 10:54am PDT Tuesday, July 28 Mtg Room 101A

AI4-II. AI/ML Architecture Design

DescriptionNon-linear activation functions play a pivotal role in on-device inference and training, as they not only consume substantial hardware resources but also impose a significant impact on system performance and energy efficiency.
In this work, we propose Distribution-Aware Piecewise Activation (DAPA), a differentiable and hardware-friendly activation function for Transformer architectures by exploiting the distribution of pre-activation data. DAPA employs a non-uniform piecewise approximation that allocates finer segments to high-probability regions of the distribution, improving generalizability over prior piecewise linear methods. The resulting approximation is further quantized using Distribution-Weighted Mean Square Error to reduce latency and resource utilization for hardware deployment.
Our HLS implementation demonstrates that DAPA speeds up GELU computation by 16x and decreases DSP utilization by 16x while maintaining comparable or better performance across vision Transformers and GPT-2 models.

People

Maoyang Xiang

Singapore University of Technology and Design

Bo Wang

Singapore University of Technology and Design

Research Manuscript

Dart: Towards Redundancy-Free RTL Simulation via DAG-Driven Execution

4:54pm - 5:06pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA2. Design Verification and Validation

DescriptionRegister Transfer Level (RTL) simulation is key to pre-silicon verification, yet its performance has stagnated in the face of rapidly escalating SoC complexity. Although recent CPU- and GPU-based simulators improve throughput through per-stimulus optimization or batch parallelism, they execute each stimulus in isolation and therefore fail to exploit the substantial computation locality that emerges across stimuli. As many stimuli converge to identical internal states, large portions of the circuit are redundantly re-evaluated, forming a principal bottleneck to scalable RTL simulation.

This paper introduces Dart, a Directed Acyclic Graph (DAG)-driven RTL simulation framework that systematically eliminates cross-stimulus redundancy. Dart constructs a DAG-based intermediate representation that makes structural commonality and shared subexpressions across stimuli explicit, enabling principled redundancy elimination through systematic sub-DAG merging. A computation-centric execution engine evaluates shared logic once and amortizes its results across all stimuli that traverse the corresponding state, while a lightweight state-reconstruction mechanism preserves per-stimulus correctness with negligible overhead. Across a suite of industrial RTL designs, Dart delivers speedups of up to 136.7x over Verilator and 4.1x over RTLflow, respectively.

People

Jingyi Zhou

Yi Zhang

Yu Huang

Yang Wu

Chunyan Xu

Shaofei Li

Institute of Computing Technology, Chinese Academy of Sciences

Xueqi Li

Long Zheng

Dataflowgen: An MLIR-Based Compiler for Efficient Dataflow Accelerator Generation

Research Manuscript

2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 201B

Chiplet

EDA

EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package

DescriptionHigh-level synthesis (HLS) has been widely adopted to map high-level languages to hardware, significantly improving hardware design productivity. Existing HLS tools have gaps in generating custom hardware due to data dependencies and differences in intermediate representation (IR) levels.
Appropriate IRs can be created for each by separating the algorithmic behaviour and the microarchitecture description, which is an effective way to reduce development costs and achieve competitive hardware designs.
In this paper, we propose DataFlowGen, an open-source framework built on MLIR for efficient dataflow accelerator generation. DataFlowGen explicitly introduces a two-level IR to perform operations at suitable abstraction levels, capturing dataflow characteristics and multi-level hierarchy.
Leveraging these representations, we develop an automated optimizer that outlines the application kernel and performs dataflow transformations to derive a hardware-oriented control dataflow graph (H-CDFG). It enables concise representation and resource efficiency of hardware architectures.
Experiments show that DataFlowGen achieves a performance improvement with significant resource reduction compared to state-of-the-art HLS tools. The results show that our optimizer effectively leverages the expressive power of IRs thus capturing kernel parallelism.

People

Workshop

DCgAA 2026: The 3rd International Workshop on Deep Learning-Hardware Co-Design for Generative AI Acceleration

1:30pm - 5:00pm PDT Sunday, July 26 Mtg Room 201B

DescriptionWorkshop Website: https://dcgaa.dk-lab.xyz/2026

In the rapidly evolving domain of computational technologies, the transformative impact of AI continues to shape the future. DCgAA (Deep Learning-Hardware Co-Design for Generative AI Acceleration) 2026 builds on the success of its inaugural edition by diving deeper into the frontier of deep learning (DL) and hardware co-design, with an amplified focus on real-world deployment challenges and next-generation innovations for generative AI applications. This third iteration of the workshop emphasizes expanding the scope beyond foundational discussions, addressing emerging paradigms in generative AI, including multimodal fusion, real-time adaptive processing, and decentralized edge applications. Acknowledging the growing role of foundation models, diffusion models, and large-scale generative systems, this workshop prioritizes optimizing these technologies for sustainable scalability, balancing performance, energy efficiency, and accessibility across diverse computing environments such as edge devices, AR/VR platforms, and ubiquitous IoT systems. Through a blended format of keynotes, paper presentations, and poster presentations, and by engaging thought leaders, researchers, and practitioners across academia and industry, DCgAA 2026 seeks to redefine the boundaries of DL-hardware integration and promises to set new benchmarks for hardware-aware generative AI, driving innovation that is efficient, scalable, and impactful in the real world.

Learn More: https://dcgaa.dk-lab.xyz/2026

People

Dongkuan Xu

North Carolina State University

Tinoosh Mohsenin

Johns Hopkins University

Caiwen Ding

Hua Wei

Xiaoxuan Yang

University of Virginia

Peipei Zhou

Brown University

Yingyan (Celine) Lin

DCTS: Differentiable Clock Tree Synthesis Based on Probabilistic Graphical Model

Yanzhi Wang

Northeastern University

Research Manuscript

4:18pm - 4:30pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionClock Tree Synthesis (CTS) constitutes a complex, discrete, and combinatorial multi-objective optimization (MOO) problem, which is typically fragmented into sequential steps, including clustering, topology generation, and buffering in traditional flows, leading to suboptimal results due to local optima. Despite significant potential in MOO, differentiable methods are inherently limited to represent dynamic topological adjustments during CTS. To solve this, We propose an end-to-end differentiable CTS framework, DCTS, based on Probabilistic Graphical Model (PGM) to re-parameterize the discrete topological search into a continuous gradient-based problem, enabling co-optimization of clock tree topology and buffer sizing within a global design space. The proposed DCTS was evaluated on ISCAS'89 and OpenCores benchmark circuits under the ASAP7 technology node. Experimental results show that it achieves competitive power, performance, and area (PPA) metrics against a leading commercial tool, along with a 2.78$\times$ speedup on large-scale circuits. Furthermore, when compared to state-of-the-art academic solutions, DCTS guarantees minimum improvements of 20\% in delay, 17\% in skew, 1\% in power, and 17\% in area, while also achieving a minimum speedup of 1.98$\times$ on large-scale designs.

People

Research Manuscript

Debug Like a Human: Scaling LLM-Based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing

4:06pm - 4:18pm PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionFault localization in modern processor design code is a critical yet time-consuming step during processor verification.
While recent advances in LLM-based techniques for module-level hardware design have shown promising results, automatically localizing bugs in large-scale, project-level processor designs remains challenging.
In this paper, we present BluesFL, a novel block-level LLM-based fault localization framework for processor designs.
Inspired by the way engineers debug processors, we first propose a dataflow-based code blockization approach to guide LLMs to focus on critical local code context.
We further propose a Block-level Instruction-Oriented Slicing (Blues) algorithm that enables LLMs to mimic human reasoning by analyzing instruction execution paths and processor states.
We evaluate BluesFL on a real-world RISC-V processor core comprising 19K lines of SystemVerilog code.
Experimental results demonstrate that BluesFL correctly localizes 24 bugs at Top-1, achieving 242.9% improvement over the existing state-of-the-art (7 bugs). Cost analysis shows that BluesFL requires an average of only $0.257 to localize a single bug.

People

Zizhen Liu

Xiaoguang Mao

Academy of Military Sciences

Deheng Yang

Jiayu He

Yihao Qin

Academy of Military Sciences

Guangda Zhang

Yan Lei

Chongqing University

Jianjun Xu

Academy of Military Sciences

Jiang Wu

Research Manuscript

Decoding the Past: Recovering Sensitive Data from SRAM Aging Imprints

11:50am - 12:03pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC3-II. Hardware Security: Attack and Defense

DescriptionLong-term data remanence in SRAMs can pose serious security risks when discarded ICs retain sensitive information. Unlike DRAM and Flash memories, SRAMs have been largely overlooked in this field due to their very short retention periods. Prior works demonstrated that aging-induced imprints enable partial data recovery in SRAMs, but only when recorded initial power-up states are available. In this paper, we have proposed a recovery approach that eliminates this requirement by reconstructing initial states through controlled aging. By analyzing the reconstructed and aged power-up states, we demonstrated near-complete data recovery from SRAM chips after 12 hours of controlled aging using only 32 copies.

People

Colorado State University

Ujjwal Guin

Auburn University

Engineering Presentation

Deep Reinforcement Learning Paradigm for Analog Design Automation

2:15pm - 2:30pm PDT Tuesday, July 28 Seaside RM 7

Design

EDA

DescriptionWe propose a tool capable of Automating Analog Design Sizing at scale in an industrial setting that meets sign-off quality. There have been several academic papers which talk about optimizing analog circuit but most of them operate under the academic umbrella which prohibits them from being viable solutions in the industrial setting where there are complex device models, PVT and Mismatch (MC) simulations, complex topologies with large number of design variable and specifications that have to be met with certain priority.

The proposed tool addresses all these challenges and is proven within our company to be a "Real" Analog Design Optimization tool.

We use Deep Reinforcement Learning and unique reward shaping algorithms to optimally tune device parameters to meet design specifications provided by the designers. The tool optimizes the design across all PVT (Process, Voltage, Temperature) corners and Mismatch (Monte Carlo) corners to produce a optimized circuit that is indistinguishable from a manually fine tuned circuit expect for the fact that, it does this much faster and arrives at the best possible solution (at least as good as the designer). It does this within a practical timeframe while being computationally economical.

At TI the solution is widely deployed and, 100+ analog circuits/blocks have been optimized with the proposed solution.

People

Sharath C R

Texas Instruments

Senthil Kumar Sundaramoorthy

Work in Progress

Defending Side-Channel Attacks in Client-Side Deduplication with Hardware/software Codesign

5:05pm - 5:06pm PDT Monday, July 27 Exhibit Hall

DescriptionClient-side deduplication can reduce redundant data transfer, but its duplicate check may expose the file existence status to attackers. Existing software-only defenses provide limited protection and impose substantial computation. Accordingly, we present RSCD, a Raptor-code and SGX Co-Designed framework that mitigate side-channel leakage in client-side deduplication. RSCD employs sparse XOR-based Raptor coding to obfuscate deduplication patterns with low overhead and uses an SGX enclave protected dirty-chunk detector to identify probing through feature analysis. Our formal analysis shows near-optimal privacy, and the experimental results demonstrate that RSCD consistently achieves lower latency, higher throughput and accuracy in attack detection than SOTA defenses.

People

Yinjin Fu

Sun Yat-Sen University

Qingli Zeng

University of South Carolina Upstate

Jian Wu

Nong Xiao

Deinfer: Efficient Parallel Inferencing for Decomposed Large Language Models

Research Manuscript

1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionExisting works of large language model (LLM) decomposition mainly focus on having better performance on downstream tasks, but they ignore the poor parallel inference performance when trying to scale up the model size. To mitigate this important performance issue, this paper introduces DeInfer, a high-performance inference system dedicated to parallel inference of decomposed LLMs. It consists of multiple optimizations to maximize performance and be compatible with state-of-the-art optimization techniques. Extensive experiments are carried out to evaluate DeInfer's performance, where the results can demonstrate its superiority, suggesting it can greatly facilitate the parallel inference of decomposed LLMs.

People

You-Liang Huang

Boston University

Xinhao Huang

The Hong Kong University of Science and Technology (Guangzhou)

Chengxi Liao

Hong Kong University of Science and Technology (HKUST)

Zeyi Wen

Hong Kong University of Science and Technology (HKUST)

Research Manuscript

Delay-Constrained Area Optimisation Using SAT-Based Local Improvement

4:10pm - 4:23pm PDT Tuesday, July 28 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionThis paper presents a new approach for minimising Boolean circuits subject to delay constraints.
The proposed approach extends the efficient but purely area-based Boolean circuit minimiser eSLIM.
The eSLIM minimiser reduces circuits by iteratively computing optimal replacements for small subcircuits on the fly.
We extend the SAT encoding used, for synthesising these replacements, to take account for delay.
While the additional constraints on delay restrict the set of possible candidates for the replacement, we can still harness the flexibility of making use of Boolean relations and multi-output circuits.
We implemented the proposed method as part of the industrial-strength tool ABC.
Surprisingly, in an experimental evaluation our implementation showed only a rather small deterioration in terms of area improvement, but substantial improvements in terms of delay compared to the purely area-based eSLIM approach on different benchmark sets.

People

Franz-Xaver Reichl

University of Freiburg

Christoph Scholl

University Freiburg

Research Manuscript

Deltasight: Architecting Efficient Video AIoT Systems via Cross-Stage Consistent Redundancy Elimination

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionThe high energy cost of video AIoT systems stems from redundant operations across sensing, transmission, and computation. While prior work optimizes individual stages, the lack of cross-stage coordination forces each stage to re-detect redundancy, limiting overall efficiency. We present DeltaSight, an algorithm–hardware co-design architecture that establishes a sensor-side unified redundancy criterion serving as the common basis for redundancy elimination throughout the pipeline. Algorithmically, we generate this criterion via sensor-side block-level redundancy detection whose output matches the granularity of downstream computation, complemented by a semantic-aware sampling strategy that adapts precision to task relevance. An architecture is designed to support this algorithm with minimal hardware additions. DeltaSight gains 2.4x sensor-side and 1.7x end-to-end energy efficiency, with slight accuracy improvements.

People

Qinyu Wang

Cen Chen

Jingkai Huang

Yawen Qiu

Hongen Shao

Hong Kong Polytechnic University

Xiaofeng Zou

Ziqian Zeng

Design Automation for Emerging AI: From AI Pins to Datacenter

Keynote

9:00am - 10:00am PDT Tuesday, July 28 Grand Ballroom

DescriptionAI is emerging as the foundational capability that defines the user experience and is reshaping the semiconductor industry into a high volume, multi-market business spanning an unprecedented diversity of power envelopes and form factors—from sub-5W battery-powered devices like AI pins and up to 500W cloud servers. This transition is also driving distributed, hybrid AI across personal devices, edge, and cloud, enabling personal AI systems that deliver low latency, improved privacy, and higher reliability – essential benefits of Edge AI.

To design silicon products that address the diverse AI workloads, power budgets, and form factors for these markets, we can leverage a common, modular IP library —including CPU, GPU, AI accelerators, connectivity, and security. However, the current process of adapting each IP and integrating it into a new SoC demands significant human effort. To minimize the NRE, we need tools that can support and automate the process, enabling engineering teams to quickly pivot and assemble SoCs that can meet the full spectrum of needs, from very low-power requirements to very high-performance.

Moreover, we face additional challenges with the slowing of Moore's law and the rise of chiplets. This necessitates new tools for 3DIC floor planning, package design, and thermal design.

During the talk, I will focus on the gaps between the current state of EDA tools and the needs of the semiconductor industry to leverage common IP across diverse products. I will also share perspectives on approaches that help to close these gaps.

People

Baaziz Achour

Qualcomm

Engineering Poster

Design Rule Checking for Rigid-Flex PCB

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionRigid-flex printed circuit boards present unique verification challenges that conventional Design Rule Check (DRC) tools fail to address, resulting in significant first-pass manufacturing failure rates and substantial respin costs per design. The fundamental problem stems from heterogeneous stackup transitions where layer count, material properties, and physical constraints vary spatially across the board—a scenario traditional 2D geometric DRC cannot comprehend.
We present a novel context-aware verification framework that integrates region-dependent rule evaluation with programmable custom DRC. Our approach combines enhanced constraint management providing real-time, location-aware design guidance with RAVEL-based custom DRC implementing sophisticated multi-domain rules that validate electrical, mechanical, and manufacturing constraints simultaneously across varying stackup configurations.
Experimental validation on multiple designs demonstrates substantial improvement in violation detection compared to standard DRC, identifying critical inter-layer issues including routing on non-existent layers, invalid via structures in flex zones, and impedance discontinuities at material transitions. Deployment results show dramatic improvements in first-pass success rates, significant reductions in verification time, and considerable project cost savings with rapid payback periods.
Keywords: Design rule checking, rigid-flex, rigid-flex PCB, heterogeneous stackup verification, RAVEL, constraint management, inter-layer validation

People

Kirti Sikri

Sr Principal Application Engineer

K Manimaran

Sr Principal Application Engineer

B G R Rao

James Donley

Sr Principal Application Engineer

Engineering Presentation

Design Spec to Die-Size Estimation Using ML Based Framework for Automotive SoCs

11:45am - 12:00pm PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionAccurate Die-Size estimation during the design specification stage is a pivotal factor in determining the cost, manufacturability, and market competitiveness of modern Automotive System-on-Chip (SoC) products. Traditional estimation approaches, which rely on linear models and heuristics, often fall short due to the increasing complexity and diversity of SoC architectures, especially as they integrate numerous IP blocks with varying requirements. This presentation introduces a machine learning (ML) framework, leveraging Random Forest algorithms, to address these challenges by learning from historical project data - including RTL structure, hard macro specifications, architectural parameters, and physical design metrics (PNR data). The proposed workflow encompasses data collection, feature engineering, model training, and prediction phases, enabling module-level area estimation and aggregation to the full SoC die-size. Empirical results, based on data from three completed SoC projects and over 1800 unique RTL modules, demonstrate the framework's robustness, achieving an R² accuracy of up to 0.95 and a mean absolute percentage error (MAPE) of 16%. This ML-based approach aims to empower chip architects and system design engineers to perform high-confidence, early die-size planning, facilitating design exploration, area recovery analysis, and informed decision-making for competitive product development.

People

Research Manuscript

Design Technology Co-Optimization for Network on Chip in High Performance CPUs at 3nm Node Using Monolithic 3D and Backside Interconnect Technologies

11:50am - 12:03pm PDT Monday, July 27 Mtg Room 202C

Design

DES5. Emerging Device and Interconnect Technologies

DescriptionWith the rapidly growing demand of cloud computing and large-scale AI models, many-core systems are facing challenges of longer global interconnect distances in Network-on-Chip (NoC). Though conventional 2D NoCs can apply relative high metal layer for global routing, the extensive repeater insertion for long-distance transmission causes significant number of via-stacking, leading to performance degradation. Targeting high-performance CPU clusters at 3nm node, this work adopts a design–technology co-optimization (DTCO) framework to evaluate long-distance NoC interconnects across four implementation schemes: conventional frontside 2D (F2D), frontside 3D (F3D) with M3D integration, F2D with backside power delivery network (BSPDN), and backside 2D (B2D) leveraging wafer backside signal routing & PDN. Based on post-layout extraction of the ARM Neoverse CSS N2 computing tile, we incorporate realistic PDN characteristics, technology-dependent RC modeling, and IR-drop-aware circuit simulation. Results show that F3D and B2D reduce delay by 53% and 68%, and energy–delay product (EDP) by 32% and 63%, respectively, compared with F2D. F2D-BSPDN achieves performance comparable to F3D. System-level NoC evaluations further demonstrate that F3D/B2D enable 2.1×/3.1× feasible link frequencies of F2D, and lower average NoC latency of F2D by 23%/35%. The DTCO analysis indicates that while F2D remains adequate for small cores (Cortex-A76), B2D is the optimal choice for mid-core (Cortex-A720, X4) and large-core (Cortex-X925, CSS N2) clusters, with F3D providing secondary benefits through repeater relocation. These findings identify backside interconnect as

People

Engineering Poster

Design Verification Automation (DVA) for PCB Signal and Power Integrity

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern PCB designs contain thousands of signal nets operating up to multi-GHz frequencies, coupled with components requiring tight supply tolerances and increasing power demands through complex power distribution networks. These designs require comprehensive signal and power integrity (SIPI) verification to achieve first-pass design success and minimize board iterations. However, traditional SIPI workflows create significant bottlenecks, requiring extensive electromagnetic (EM) extraction and simulation setup expertise and manual intervention across multiple tool interfaces. Conventional analysis consumes weeks to months per design iteration while limiting verification to specialized engineers—a critical constraint for organizations.
This work presents an integrated SIPI verification framework that automates the complete workflow from EM extraction through circuit simulation to performance evaluation. The methodology introduces: (1) automated mesh generation and solver configuration reducing setup time from hours to minutes, (2) template-based circuit testbenches enabling seamless SPICE and IBIS model integration with extracted parasitic networks, and (3) automated post-processing with customizable pass/fail criteria and standardized reporting templates.
Validation across several production board designs demonstrates reduction in revision time from 24% to 3% while achieving 100% first-pass prototype success rate. This framework enables engineers with basic SIPI knowledge to perform comprehensive verification and optimization, expanding team capacity and design coverage.

People

Sherif Amer

Adam El-Mansouri

Colton Love

Garrett Stauffer

Tracey Windley

Design-for-FV Approach on a RISC-V Memory Page Walker

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAheadComputing is developing a high-performance RISC-V core where delivering a bug-free memory subsystem is a top verification priority. The memory page walker (PW) is especially critical because it must conform to the open RISC-V Privileged Architecture specification while also meeting design-specific requirements.
This submission presents a design-for-FV methodology applied early to enforce a clean architectural boundary that improves formal reachability and convergence, enabling shift-left bug discovery. In this case, all design-specific features are isolated in wrapper RTL modules, while the page walker remains a pure implementation of the RISC-V spec. From the earliest stages, the FV team can build an independent SystemVerilog reference model for the PW as an independent implementation of the same architectural specification as RTL. Embedded SVA checkers in the reference model enable rapid formal closure, exposing RTL bugs and spec-translation issues that are difficult to catch with simulation alone. At higher integration levels, proof scalability is further improved by substituting the PW RTL with a PW abstraction model—a simplified reference model that preserves architectural behavior while reducing formal complexity.
In a short case study, we show how this flow drove interface and micro-architecture refinements, improved maintainability, and accelerated confidence in spec-compliance for a critical RISC-V memory component.

People

Engineering Presentation

Designing Power- and Area-Efficient Custom NPUs for Edge AI

10:45am - 11:00am PDT Wednesday, July 29 Seaside Ballroom B

Design

EDA

Security

Systems

DescriptionEdge AI is increasingly popular in applications requiring real-time decision making and autonomous operation. Different from NPUs for cloud platforms, edge AI processors can be made application-specific. By tuning their ISA and memory architecture to the network models required by the application, power consumption and silicon area are drastically reduced.

Tools for application-specific instruction-set processors (ASIPs) can be used to design custom NPUs for edge AI. We present the design of "SmarT", an ASIP with a RISC-V ISA augmented with specialized vector units for convolutions and quantization, with 64 MACs. It supports circular gather/scatter addressing of vector data in parallel with computations. Low-overhead DMA moves data blocks from external to local memory.

ASIP tools enable a software path from TensorFlow using LiteRT. We optimized selected LiteRT kernels in conjunction with the processor architecture. SmarT uses only 200Kgates, while delivering 100GMAC/s performance, making it suited for many low-power sensor, audio and video applications.

People

Engineering Special Session

Deterministic, Solver‑Accurate Physics Intelligence for Chips‑to‑Systems Design: What Breaks, What Validates, What Automates

1:30pm - 3:00pm PDT Monday, July 27 Seaside RM 7

Chiplet

Design

EDA

Systems

DescriptionAs chiplet architectures, 3D integration, and HBM‑class systems push thermal‑mechanical‑electrical coupling into the critical path, engineering teams are discovering that traditional simulation workflows—built around manual setup, sparse sampling, and human‑driven iteration—cannot scale to manufacturing‑resolution design. In this regime, nondeterminism, approximation, and workflow variability become failure modes rather than accelerants.

This session examines what it takes to make physics‑based AI viable for production engineering workflows, where deterministic execution, solver‑accurate validation, and reproducible physics reasoning are essential. We will explore what breaks when probabilistic or approximate methods are applied to high‑stakes physical design, the technical and operational criteria required for trustable results, and which elements of chips‑to‑systems workflows can be automated once physics reasoning operates continuously at machine scale. Drawing on semiconductor, advanced packaging, thermal, and multiphysics domains, a panel of industry and academic experts will discuss how deterministic, physics‑grounded AI enables broader design exploration within real development timelines.

People

Research Manuscript

Detrojan: Detecting Trojan Circuits Using a Purpose-Built Graph Neural Network with Community-Enhanced Classification

10:30am - 10:43am PDT Tuesday, July 28 Mtg Room 203C

Security

SEC3-II. Hardware Security: Attack and Defense

DescriptionGate-level Hardware Trojan (HT) detection using Graph Neural Networks (GNNs) often suffers from limited accuracy due to the reliance on structure-only features and fragmented node-level predictions. We propose a GNN-based framework, \papertitle, to overcome these challenges through three key innovations:
(1) functionality-aware feature engineering,
(2) an edge-aware GNN architecture with Jumping Knowledge and global context aggregation, and
(3) accurate Trojan circuit localization with community-aware classification refinement.
Evaluated on the 2025 ICCAD CAD Contest Hardware Trojan benchmarks, DeTrojan achieves a 16.7% improvement in circuit-level prediction accuracy and a 47.3% relative increase in gate-level F1-score over the state-of-the-art machine learning (ML)-based methods. Furthermore, incorporating our proposed features and refinement modules into the existing approaches yield up to 16.6% gain in accuracy and a 2× improvement in the F1-score, demonstrating the effectiveness and generality of our framework.

People

Chien-Tung (Cherie) Kuo

Chen-Ching Nieh

Jie-Hong Roland Jiang

Chung-Yang (Ric) Huang

Development of Machine Learning Framework for Split-Parameter Optimization of LDMOS Devices

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionChip development timelines are often limited by device (transistor) readiness. When devices miss targets, schedules slip by additional shuttle fabrication runs. This risk is higher when teams rely on newly characterized devices in a given process, which forces process and device engineers to tune measured current-voltage (I-V) and capacitance-voltage (C-V) behavior by sweeping split parameters of device structure. Currently, this split-parameter search is largely trial-and-error: each iteration takes months, only a small fraction of the split space is measured, and design teams often run circuit simulations based on device data from non-optimized structures. We present an explainable machine-learning framework that learns from sparse tapeout measurements to predict measured LDMOS I-V/C-V curves directly from split parameters. Data augmentation and ensemble modeling improve robustness in the low-data regime. Compared with commonly used modeling baselines, the framework achieves very high accuracy (low mean relative error) while providing interpretable attributions across operating regions to identify which split parameters drive key behaviors. The trained model then screens up to billions of candidate split parameters and supports inverse design to recommend parameters that meet user-defined device performance, such as breakdown voltage. Overall, the approach converts limited silicon data into decision-ready guidance that accelerates split exploration, reduces shuttle iterations, and shortens the silicon-to-design cycle.

People

Ariel Yeh

Leafy Lab

Research Manuscript

DFA-DRIVE: A Cross-Layer Delay Fault Analysis and Optimization Framework for Robust Multi-Task Driving Perception

2:21pm - 2:34pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS1. Autonomous Systems (Automotive, Robotics, Drones)

DescriptionAutonomous driving systems increasingly rely on deep neural network (DNN) based multi-task perception models for reliable, real time scene understanding. At nanoscale technology nodes, these workloads are highly susceptible to timing errors arising from temperature fluctuations, voltage droop, and device aging. Among these, temperature poses a critical challenge prolonged high thermal stress exacerbates delay faults, degrading perception accuracy and endangering safety-critical operation.
We present DFA DRIVE, a cross-layer Delay Fault Analysis Framework for Autonomous Driving that bridges circuit-level timing analysis with system level resilience evaluation. DFA DRIVE quantifies how temperature induced timing failures propagate through object detection, drivable area segmentation, and lane line segmentation, exposing task level reliability bottlenecks.
Building on this foundation, we introduce DFA-OPT, an adaptive DNN hardware mapping algorithm that dynamically reassigns systolic-array resources based on DNN layer and applicaiton level thermal sensitivity. Targeting the automotive reliability envelopes of AEC-Q100 Grade 0 (–40 °C to 150 °C) and Grade 1 (–40 °C to 125 °C), DFA-OPT restores near baseline accuracy of small, high reliability systolic arrays (e.g., 4×4) even when large systolic arrays (e.g., 256×256) experience accuracy drops of up to 4% at 150 °C, achieving comparable accuracy with up to 92% fewer computation cycles.

People

Nrusinga Charan Gantayat

Sandia National Laboratories

Philip Jacobson

Matthew Marinella

Sandia National Laboratories

Ben Feinberg

Jeff Zhang

DFT Ready Design with SCO Canvas : Shift Left of DFT Designs

Engineering Presentation

11:45am - 12:00pm PDT Monday, July 27 Seaside Ballroom A

EDA

DescriptionAs semiconductor designs scale in complexity, Design-for-Test (DFT) has become a critical bottleneck, often delayed until the post-RTL freeze stages. This paper introduces a novel "DFT-Ready Design" methodology using SOC Canvas to bridge the chronic gap between system design and DFT. Unlike conventional flows where DFT engineers rely on fragmented pre-DFT information, our approach captures system-level functional intent—such as power, clock, and I/O configurations—via an intuitive GUI at the earliest architectural stages. SOC Canvas then automatically generates IEEE 1687-compliant hardware structures and integrated control logic, ensuring total data consistency across RTL, synthesis, and DFT. We validated this methodology in a large-scale AI accelerator project, successfully reducing the total design cycle by 25% while eliminating the manual iterations typically required for DFT logic insertion. By shifting DFT responsibilities to the left and automating the generation of test-control infrastructures, this work provides a scalable foundation for modern SoC and emerging chiplet ecosystems, ensuring that designs are inherently "DFT-ready" before synthesis begins.

People

Hoyeon Jeon

ITDA semiconductor Co.,Ltd.

Research Manuscript

DIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing

11:10am - 11:23am PDT Monday, July 27 Mtg Room 203AB

Design

DES2A. In-memory and Near-memory Computing Circuits

DescriptionDynamic-iterative aggregation (DIA) in graph neural networks updates node states sequentially and asynchronously. This expands the receptive field without adding layers and improves accuracy-per-operation versus layer-synchronous models. However, DIA introduces fine-grained serial dependencies and highly irregular sparse traffic that undermine conventional SIMD/accelerator designs. We present DIA-CIM, a 28-nm compute-in-memory (CIM) macro co-designed for DIA. DIA-CIM employs a CSR-driven, output-stationary dataflow to keep partial sums local while streaming edges, a sparsity-priority BF16 pipeline that exploits bit/value sparsity. Fabricated in 28-nm CMOS, DIA-CIM reaches 60.01 TFLOPS/W. On representative DIA workloads, it delivers >3.56 × lower energy and >2.32 × lower latency.

People

Zhaoyang Zhang

Tianhao Zhao

DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization

Research Manuscript

1:42pm - 1:55pm PDT Tuesday, July 28 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionPost-layout optimization is a critical step in modern chip design. However, existing Machine Learning (ML)-assisted methods struggle to capture the cross-stage reasoning dependencies that underlie the optimization challenges. While large language models (LLMs) excel at semantic reasoning, the lack of structural and physical awareness limits their effectiveness in post-layout optimization. To address these limitations, we propose DiffDEG, a diffusion-enhanced, reasoning-aware foundation model that bridges LLM-based semantic reasoning with circuit-level structural and physical representations. DiffDEG reformulates the conventional timing graph into a Design Evolution Graph (DEG), enabling cross-stage reasoning through text-annotated netlists. By leveraging directional diffusion and self-supervised pretraining, DiffDEG jointly interprets semantic, timing, and physical information, forming a unified representation adaptable to diverse optimization tasks. Experimental results show that DiffDEG consistently enhances optimization outcomes across multiple optimization paradigms, achieving an average 12.5% performance improvement and 4x runtime speedup over commercial tools.

People

Jiajie Xu

Leilei Jin

Peng Cheng Laboratory

Longxing Shi

Differentiable Fill Insertion with Explicit Delay Optimization

Research Manuscript

1:30pm - 1:42pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionFill insertion need to consider not only density uniformity but also delay. Existing algorithms reduce such delay implicitly by minimizing proxies (fill amounts, overlays between fills, etc) but there remains misalignment between the reduction of proxies and improvement of the signal delay. We propose DiffFill, a novel differentiable framework for fill insertion that explicitly optimizes both uniformity and delay. At the heart of DiffFill is the CapFormer, a Transformer-based capacitance extractor that estimates capacitance values used to construct a differentiable delay objective based on the Elmore delay formulation. DiffFill significantly outperforms the state-of-the-art methods.

People

Jinoh Cho

Pohang University of Science and Technology (POSTECH)

Jinmo Ahn

POSTECH

Jakang Lee

Department of Electrical Engineering, POSTECH, Pohang, South Korea

Jaeseung Lee

Seonghyeon Park

POSTECH

Seokhyeong Kang

Pohang University of Science and Technology

Engineering Poster

Differential Validator: Ensuring SoC ROM to Hierarchical Blocks Node Voltage Integrity

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionSoC Flat IR/EM signoff is generally done for multiple cycles thus generally mandating 2+ days to cover a single scenario- not only is the coverage limited but also expensive since even small ECO fixes trigger full analysis repeat (of same resources). Additionally, designs which have multiple hierarchical block level instantiations - this is massively computationally redundant.

Reduced Order Model (ROM) Flow: Hierarchical Abstraction for IR/EM Signoff:
ROM eliminates computational redundancy by using abstract representations of pre-verified blocks. It leverages tweaked SoC flat analysis to have appropriate block level details to enable 10-20× faster SoC turnaround and broader scenario coverage. Below is its mechanism:
The Common Connection Layer (CCL) acts as the electrical boundary between block & SoC top. ROM preserves full detail only at the CCL and CCL-1, while the lower metal layers (M0 to CCL-2) are rolled up into equivalent impedance model to maintain signoff accuracy.
Designers use a mix of detailed instances for same critical block with reduced instances to optimize resource usage as shown in Fig 1.
The Validation Problem with ROM- Trust Gap:
Context Mismatch: ROMs are generated in standalone conditions, failing to account for top-level grid impedance and adjacent block coupling.
Fidelity & Coverage Loss: Abstracting 12-14 layers can mask local voltage violations; current manual spot-checks are insufficient since these fail to quantify if CCL node voltages in all ROM instances match their power-domain & scenario specific simulation values
Objective of this work:
Systematic validation across all ROM instances & all power domains in a quick (wall time ~mins for SoC) else it would offset ROM runtime benefits.
Quantitative fidelity metrics with low violation thresholds & spatial coverage for debug to understand root cause of localised errors.

People

Research Manuscript

Diffsp: Differentiable Sequence Pair-Based Analog Placement

4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionAnalog placement with compact representations is traditionally solved using heuristic or simulated annealing methods that are difficult to integrate with a differentiable optimization engine.
This paper introduces DiffSP, a differentiable sequence-pair-based analog placement method that bridges discrete combinatorial representation with continuous gradient optimization.
We derive a smooth relaxation of the sequence pair constraint graph via Gumbel–Sinkhorn relaxation, which allows area, wirelength, and symmetry objectives to be jointly optimized via automatic gradient calculation.
A MILP-based legalization stage then enforces exact geometric and symmetry constraints.
Experiments on industrial-level OTA benchmarks show that DiffSP achieves better placement quality and post-layout performance metrics than state-of-the-art analog placers with significantly reduced runtime.

People

Peng Xu

Mingzi Wang

Yapeng Li

Yuyang Ye

Tinghuan Chen

Tsung-Yi Ho

Digital Inside Analog: Continuous-Time Pipelined ADCs for Wideband Analog-to-Digital Conversion

Engineering Special Session

2:00pm - 2:30pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

DescriptionThis talk explores the concept of "Digital Inside Analog" through the lens of the continuous-time pipelined analog-to-digital converter (ADC). This sophisticated architecture is an example where digital signal processing works intimately within the analog signal path to achieve orders-of-magnitude improvement in performance for the same power dissipation. Unlike traditional discrete-time pipelines, the continuous-time approach eliminates power-hungry front-end sample-and-hold amplifiers while providing inherent anti-aliasing filtering. We delve into the unique challenges of this architecture, and how analog imperfections are mitigated using "digital-inside" calibration. By leveraging digital assistance, the continuous-time pipeline achieves a lower power disspation, higher linearity and lower noise than a traditional signal chain that consists of an antialias filter followed by an ADC. Measurements from prototype lowpass and bandpass CTP ICs will be given.

People

Shanthi Pavan

IIT Madras

Engineering Special Session

Digitally Assisted Analog Techniques for Next‑Generation Data Converters, Test, and Clocking

1:30pm - 2:00pm PDT Tuesday, July 28 Seaside Ballroom B

Design

EDA

DescriptionOver the past two decades, digital logic density has increased by more than three orders of magnitude, while analog metrics such as gain, linearity, and noise have improved only incrementally. Digital calibration and compensation can cut analog design margins by up to 50%, enabling smaller and more power-efficient circuits, while techniques such as dynamic voltage and frequency scaling, algorithmic noise shaping, and digital redundancy consistently deliver order‑of‑magnitude energy savings over analog-only solutions. Furthermore, digital subsystems inherently support in‑situ testability, with scan-based and BIST methods achieving production fault coverage exceeding 99%. Reflecting this shift, modern SoCs are now more than 80% digital—even in RF, clocking, and sensor interfaces. This talk explores how digitally assisted analog techniques are reshaping mixed‑signal design, enabling scalable, low-power, and highly testable solutions for next‑generation systems.

People

Ankur Bal

ST Microelectronics

Research Manuscript

Disentangled Differentiable Timing-Power Co-Optimization with Quad-Gradient Gate Sizing

10:43am - 10:56am PDT Monday, July 27 Mtg Room 202AB

EDA

EDA3. Timing Analysis and Optimization

DescriptionCo-optimizing timing and power in modern VLSI designs remains challenging under realistic static timing analysis and standard-cell libraries. Classical gate sizing often scales poorly, while learning-based sizers behave as expensive black boxes with limited generality. Recent differentiable physical optimization enables gradient-based design flows, but existing approaches still struggle to stay aligned with library-based implementations and to provide controlled timing–power trade-offs. We propose a library-native quad-gradient gate sizing framework that leverages differentiable timing to derive structured guidance for timing and power, enabling more systematic and interpretable co-optimization in the standard-cell sizing space. On the ICCAD 2025 contest benchmarks, our framework achieves, on average, 40.4 percent points (%pt) larger reduction in TNS and 16.2 %pt better total power change than the 1st-place contest flow.

People

Research Manuscript

DM-MARK: Software and Hardware Co-Design of Watermarking Accelerator for Authorized Diffusion Model Usage on Edge Devices

12:16pm - 12:30pm PDT Monday, July 27 Mtg Room 101B

AI4-I. AI/ML Architecture Design

DescriptionWith the rapid growths of generative models like diffusion models (DMs), distinguishing authentic images from forfeited ones has become increasingly challenging, raising privacy, security, and ethical concerns. Watermarking offers an effective solution for authentication and traceability of generated images. Unlike traditional methods, emerging watermarking techniques for DMs enable marking AI-generated content with resilience to commonly used watermark weakening or erasing techniques. However, these methods demand high computational resource and latency, posing challenges for practical use, especially on edge devices.This work presents DM-MARK, a software-hardware co-optimized diffusion framework supporting efficient watermark generation and reverse detection. DM-MARK is implemented in 12nm FinFET technology, achieving robust watermarking with improved quality and reduced overhead. Evaluations show 11.33% higher detection accuracy, 18× latency speedup over GPU, 3.1× on-chip memory savings, an average of 4.56× EMA reduction. It also achieves 212.5× speedup over the baseline ASIC design with negligible accuracy loss. The proposed DM-MARK scheme offers a scalable and practical solution for protecting AI-generated content in real-time on edge devices.

People

Shiyu Guo

Jie Gu

DRΛMA: Detailed Routing by a Versatile Maze Routing Algorithm

Research Manuscript

5:06pm - 5:18pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionDetailed routing, despite its long history of study, is considered one
of the most challenging problems in Electronic Design Automation,
due to complex design rules and enormous scale. In this work, we
propose a versatile maze routing algorithm to deal with the various
challenges in detailed routing. By introducing hybrid grid graph, our
maze routing algorithm can create both on-track and off-track wires
during path search. By adopting a scalable track-based resource
model and techniques like adaptive grid graph sparsification, it can
handle both large guide-based and small region-based grid graphs.
Moreover, we also propose a simple and effective rip-up and reroute
strategy. As a result, we achieve design rule violation-free on most
designs (9/10) in the ISPD 2018 detailed routing benchmarks, with
2.5% better score, 4.6% fewer vias, and 14.7% shorter runtime on
average, and significantly lower non-preferred usage, compared
with the state-of-the-art approaches.

People

Jinwei Liu

Hong Kong Baptist University

Xingyu Cui

Liang Xiao

Bangqi Fu

Evangeline Young

DR. OPC: Differentiable Rasterization for Advanced Optical Proximity Correction

Research Manuscript

1:42pm - 1:55pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionOptical proximity correction (OPC) is essential for mitigating lithographic distortions in semiconductor manufacturing. A standard OPC iteration involves the rasterization, lithography simulation, and correction of mask patterns. However, the non-differentiable nature of rasterization limits both optimization efficiency and flexibility. In this paper, we propose DR. OPC, a fully differentiable OPC pipeline enabled by differentiable rasterization. It natively supports advanced features like curvilinear patterns, multi-segment solving, process window improvement, and mask rule violation correction.
Experiments demonstrate that DR. OPC achieves reductions of 52.1\%, 16.0\%, and 21.1\% in L2 error, PVB, and EPE, respectively.

People

Su Zheng

Xinyun Zhang

Martin Wong

DRCA: Reliable Bitwise Logic in DRAM via Dual-Rail Compute and Access

Research Manuscript

12:16pm - 12:30pm PDT Monday, July 27 Mtg Room 203AB

Design

DES2A. In-memory and Near-memory Computing Circuits

DescriptionDRAM-based processing-in-memory (PIM) emerged as a promising approach to alleviate the memory wall by executing massively parallel bitwise operations inside DRAM arrays. However, most prior designs operate on a single bitline and leave the dual-rail complementary signals naturally available on each bitline pair underutilized. We present DRCA, a novel dual-rail compute-and-access scheme that exploits both rails of a bitline pair for computation and data access. DRCA integrates two dual-contact compute cells, DRCA-OR and DRCA-XOR, which leverage full-swing dual-rail signaling on the bitline pair to perform bitwise logic with high reliability. Furthermore, the design enables concurrent operations on a single bitline pair, improving the efficiency of complex bitwise logic processing. Our evaluation shows that DRCA reduces failure rate by 2.29x compared with the most robust prior PIM design, while delivering superior average performance on basic bitwise operations.

People

Yuxuan Qin

Chuxiong Lin

Shanghai LEDA Technology Co., Ltd

Shuo Yan

Guoming Rao

Weiguang Sheng

Weifeng He

Drcagent: A Design Rule Aware LLM Agent for DRC Auto-Fix with Adversarial Reinforcement Learning

Research Manuscript

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionAs semiconductor manufacturing advances toward leading-edge nodes, such as 7 nm and below, Design Rule Checking (DRC) and violation correction have emerged as critical bottlenecks in achieving design closure. This escalation arises from intricate geometric constraints and complex rule dependencies, which traditional template-based or heuristic approaches are inadequate to resolve efficiently. These methods offer limited adaptability when migrating to new process nodes. To overcome these challenges, we propose drcAgent, a novel framework for automated DRC violation correction. The framework integrates a multimodal Large Language Model (LLM) agent with a Retrieval-Augmented Generation (RAG) mechanism grounded in a Design Rule Knowledge Graph (DRKG). We develop a self-play adversarial multi-turn reinforcement learning framework where a Generator agent and a Fixer agent co-evolve, enabling the agent to iteratively improve its correction policy through real interactions with commercial EDA tools. Experimental results on real industrial-scale design cases demonstrate that the proposed framework can be effective at fixing violations, offering a promising new learning-based solution for chip design.

People

Research Manuscript

DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation

4:42pm - 4:54pm PDT Tuesday, July 28 Mtg Room 202AB

EDA

EDA7-I. Physical Design and Verification

DescriptionVLSI layout pattern generation plays a crucial role in design for manufacturability (DFM). Patterns that incorporate specific design rule checking (DRC) violations are valuable for applications such as foundry design-rule deck development, EDA tool validation, and generating training data for AI-based DRC research. However, existing research primarily focuses on producing DRC-clean layouts by enforcing rule compliance through constraints or filtering, while ignoring the generation of controllable violations. To address this gap, we propose DRCGen, a controllable framework for generating DRC violation patterns with cross-PDK transferability. DRCGen is based on a diffusion model with conditional control, generating structured control hints to encode spatial and semantic violation information for fine-tuning the model. The model can generate violation patterns of user-specified types within a target
region based on a natural-language prompt, while maintaining DRC-compliance outside the region. Additionally, we incorporate few-shot learning to facilitate rapid transfer across different PDKs. Experimental results show that, compared to state-of-the-art methods, our approach achieves a 2.27× increase in topological diversity and a 1.02× increase in geometric diversity. Compared to Calibre LSG, we achieve 3.31× and 1.15× improvements in topological and geometric diversity, respectively.

People

Research Manuscript

DRIFT: Harnessing Inherent Fault Tolerance for Efficient and Reliable Diffusion Model Inference

5:18pm - 5:30pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionDiffusion model deployment has been suffering from high energy consumption and inference latency despite its superior performance in visual generation tasks. Dynamic voltage and frequency scaling (DVFS) offers a promising solution to exploit the potential of the underlying accelerators. However, existing approaches often lead to either limited efficiency gains or degraded output quality because they overlook the inherent fault tolerance of the diffusion model. Therefore, in this paper, we propose DRIFT, a novel algorithm-architecture co-optimization framework that harnesses the fault tolerance for efficient and reliable diffusion model inference. We first perform a comprehensive resilience analysis on representative diffusion models. Building on these observations, we introduce a fine-grained, resilience-aware DVFS strategy that selectively protects error-sensitive network blocks, and a rollback-ABFT mechanism that adaptively corrects only critical errors by reverting to previous timesteps. We further optimize offloading intervals and reorganize data layouts to reduce memory overhead. Experiments across diverse models and datasets show that DRIFT can achieve on average 36% energy savings through voltage underscaling or 1.7x speedup via overclocking while maintaining generation quality.

People

Peking UniversityPeking University

Research Manuscript

Drop-In Masked Modular Reduction for ML-DSA: Cutting Side-Channel Cost in the Root-of-Trust

5:06pm - 5:18pm PDT Tuesday, July 28 Mtg Room 203C

Security

SEC2. Hardware Security: Primitives, Architecture, Design & Test

DescriptionMasking is an effective defense against side-channel attacks, yet it remains costly under hardware constraints. The Caliptra Root-of-Trust is a representative case, where its masked ML-DSA implementation incurs about 6× area overhead. We propose a novel first-order masking solution that optimizes Caliptra, achieving significant improvements in area–delay efficiency. Compared to Caliptra's ML-DSA reduction, our design achieves a 12.1× speedup, reducing LUTs by 86.7% and FFs by 94.5%, while improving area–delay efficiency by 91×. The optimized architecture increases signing throughput by 1.32×. TVLA, with over 1,000,000 traces, shows no first-order leakage, satisfies Caliptra's security requirements, and significantly improves implementation efficiency.

People

Merve Karabulut

Florida Atlantic University

Reza Azarderakhsh

Florida Atlantic University

Research Manuscript

Dropping Multiple Literals per SAT Call in IC3 Model Checking

10:54am - 11:06am PDT Wednesday, July 29 Mtg Room 202AB

EDA

EDA2. Design Verification and Validation

DescriptionIC3 is the state-of-the-art model checking algorithm where generalizing
cubes by dropping literals one-by-one is the most computationally
expensive step. We propose multi-literal drop strategies that
eliminate two or more literals simultaneously. Successful n-drop saves
n−1 SAT invocations. To mitigate performance losses from failures,
we introduce deduction mechanisms that analyze counterexamples to
generalization and identify non-droppable literals early. With these, failed
multi-drop attempts are sometimes as useful as conventional
single-drops. Additionally we analyze the diminishing returns of higher-order
drops. Implementation on ABC solves 28 unique and 16 more cases than
vanilla ABC and implementation on rIC3 runs 6% faster.

People

Tianjun Bu

Zhichao Lyu

Qiusong Yang

DScNMP: A Dataflow Scheduling for the Precision-Scalable Near-Memory Processing Microarchitecture

Late Breaking Results

5:42pm - 5:45pm PDT Monday, July 27 Exhibit Hall

DescriptionNear-memory processing (NMP) mitigates the overhead of host-memory data movement while maintaining efficient data access.
We introduce DScNMP, an architecture-dataflow co-design that employs dataflow scheduling to optimize NMP executions.
DScNMP incorporates dynamic workload scheduling, intra-cycle coordinated control, and state supervision units, ensuring efficient resource management.
Evaluation results show that DScNMP, occupies 0.006384 mm^2 in 14 nm, achieves 2.7× lower data access latency, up to 8.9× and 4.9× fewer cycles for external data movement and memory-bound workloads, respectively, and delivers 2.4× higher multiply-accumulate efficiency than Armv8.1-M.

People

yueting Li

Hangzhou International Innovation Institute, Beihang University

Research Manuscript

DSPE: An Energy-Efficient Edge Processor for Deepseek Inference with Merkletree-Based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing

11:50am - 12:03pm PDT Monday, July 27 Mtg Room 101B

AI4-I. AI/ML Architecture Design

DescriptionIn recent years, DeepSeek has achieved strong inference performance but remains hard to deploy on energy-constrained edge devices. This paper presents the DeepSeek Processing Element (DSPE), an edge-oriented architecture that alleviates the model's heavy computational and energy demands. DSPE introduces three techniques: the MerkleTree-based Incremental Pruning Scheme (MIPS) for secure redundant-vector reduction, the Multi-Stage Boothing Lookup Method (MBLM) for bit-flip–aware approximate multiplication, and the Dynamic Adaptive Posit Processing Mechanism (DAPPM), which introduces a new DA-Posit format and its corresponding hardware multiplication architecture. Implemented in TSMC 28nm CMOS, DSPE achieves 91.7 TFLOPS/W energy efficiency compared with state-of-the-art designs and offers a scalable foundation for edge deployment.

People

Yuhan Zhang

Northeastern University

Zhou Wang

Imperial College

Zhou Shu

School of Electrical and Computer Engineering of National University of Singapore

Jiuren Zhou

Hangzhou Hikvision Digital Technology

Yanqing Xu

Beijing Wisemay Science and Technology Co.,LTD

Xiaonan Tang

shushan qiao

Tianchun Ye

Nanyang Technological University

Yang Liu

Anil Bharath

Imperial Global Singapore, Imperial College London

Emm Drakakis

Imperial Global Singapore, Imperial College London

Research Manuscript

DUET: Disaggregated Hybrid Mamba-Transformer LLMs with Prefill and Decode-Specific Packages

12:03pm - 12:16pm PDT Wednesday, July 29 Mtg Room 101A

AI4-I. AI/ML Architecture Design

DescriptionLarge language models operate in distinct compute-bound prefill followed by memory bandwidth-bound decode phases. Hybrid Mamba–Transformer models inherit this asymmetry while adding state-space model (SSM) recurrences and element-wise operations that map poorly to matmul-centric accelerators. This mismatch causes performance bottlenecks, showing that a homogeneous architecture cannot satisfy all requirements. We introduce DUET, a disaggregated accelerator that assigns prefill and decode phases to specialized packages. The Prefill package utilizes systolic array chiplets with off-package memory for efficient large matrix multiplications and long-sequence SSMs. The Decode package utilizes vector-unit arrays with high-bandwidth in-package memory to accelerate token-by-token SSM and vector–matrix multiplications. Both architectures are runtime-configurable to support hybrid models with mixed Mamba and attention layers. Evaluations on Nemotron-H-56B, Zamba2-7B, and Llama3-8B across four workloads show that DUET achieves 4x faster time to first token, 1.4x higher throughput, and 1.5x lower time between tokens over the B200 GPU.

People

Alish Kanani

Sangwan Lee

University of Ulsan

Han Lyu

Jiahao Lin

Samsung Austin Research Center/ACL; University of Wisconsin-Madison

Jaehyun Park

University of Ulsan

Umit Ogras

Research Manuscript

Duet: Exploiting High-Order Lossless Sparsity for Bit-Serial Transformer Acceleration via Distribution-Aware Pruning

10:56am - 11:10am PDT Wednesday, July 29 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionTransformer models achieve exceptional performance, but face high computational costs that hinder their deployment on resource-constrained devices. While bit-column sparsity (BCS) offers promising post-training acceleration, existing distribution-agnostic methods neglect natural sparsity in the most significant bits (MSBs) from Gaussian-like weight distributions, requiring aggressive accuracy-degrading modifications on the least significant bits (LSBs). This paper presents Duet, a bit-serial accelerator fully exploiting High-Order Lossless Sparsity in BCS for load-balanced Transformer acceleration. At the algorithm level, Distribution-Aware Pruning (DAP) partitions weights by a hyperparameter to maximize lossless MSB pruning opportunities, while Fixed Redundant Hierarchical Search (FRHS) optimally handles remaining compression, achieving 3.13/3.25 effective bits with negligible accuracy loss. At the architecture level, our Duet accelerator addresses four key challenges: (1) two-level shifter resolves bit significance mismatch in Duet encoding format; (2) parallel Metadata-Weight pipelines support variable bitwidths while completely hiding metadata processing overhead; (3) Activation Sum Generator supports time-multiplexed Metadata Pipeline; (4) dual mode operation handles both linear and attention layers in Transformer models. Duet accelerator ensures load-balanced execution for all Processing Elements (PEs). Experiments on BERT and ViT demonstrate 1.45× ~ 4.30× speedup and 1.32× ~ 2.94× energy improvement over SOTA accelerators.

People

Research Manuscript

Duplication-Aware Retiming and Cell Interface Redesign for Superconductor Circuit Minimization

5:16pm - 5:30pm PDT Tuesday, July 28 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionSuperconductor electronics have increasingly shifted away from RSFQ and its variants toward logic families that eliminate explicit gate-level clocking. While this transition enables simpler circuits and more efficient architectures, it also introduces an implicit reliance on dual-rail codes, resulting in inherent gate duplication. This work presents a duplication-aware retiming methodology for Josephson junction (JJ) count minimization, co-optimizing register placement and polarity assignment. The approach applies beyond SFQ to any monotonic circuit. We further identify cell interfaces—specifically, interconnect drivers, receivers, and fanout (FO) elements—as dominant contributors to JJ count in each cell. A new amplifier design is introduced to reduce these costs, integrated within existing SFQ cells, experimentally verified, and characterized to form a new SFQ cell library. Our results demonstrate a 63-71% JJ count reduction in single-cycle implementations and 41-66% reduction in multi-cycle implementations compared to the prior state-of-the-art. The latter establishes a new Pareto frontier, achieving both shorter critical paths and lower JJ counts than the best-to-date single-cycle implementations.

People

Panagiotis Papanikolaou

Alex Vanasse

Haoran Jin

Georgios Tzimpragos

Jennifer Volk

Dynamic CDC Verification Using SVA for Waiver Review

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAsynchronous clock domains in modern SoC designs present critical verification challenges, as Clock Domain Crossing (CDC) issues remain the second most common cause of silicon re-spins. While static CDC ensures structural synchronization, it relies on manual constraints and waivers that may be inaccurate or hide functional bugs. Furthermore, formal analysis often leaves properties "partially proven" due to computational complexity.

This paper proposes a closed-loop methodology to validate these "design intent" assumptions dynamically. The flow begins by running structural CDC and filtering results to identify waived paths. These waivers—including those translated from TCL to constraint formats—are converted into protocol-aware SystemVerilog Assertions (SVA). By integrating these SVAs into dynamic simulation, engineers can stress-test protocols like data-hold and glitch protection.

If simulations pass, waiver validity is confirmed for sign-off; failures trigger design or constraint refinement. This methodology is a "MUST" for SoC design, uncovering corner-case bugs unreachable via manual reviews. Key advantages include significantly reduced Turnaround Time (TAT) and high-quality sign-off guaranteed by measurable assertion coverage.

People

Research Manuscript

Dynamic-Cost Area Recovery for Fracturable LUT-Based FPGAs

4:50pm - 5:03pm PDT Tuesday, July 28 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionFracturable LUTs (FLUTs) creates variable logic consumption for LUT implementations since two LUTs can be merged to one FLUT under certain constraints. Traditional technology mapping algorithms fail to exploit this feature due to their static-cost area models. To bridge this gap, we introduce merging probability, a quantitative, mapping-stage metric that predicts the likelihood of LUT merging during the subsequent packing phase. Based on this, we present a dynamic-cost LUT area model, enabling area recovery better suited for FLUTs. Experimental results on EPFL benchmarks demonstrate that our method reduces the usage of FLUTs by at most of 10.3% on mainstream commercial FPGAs, compared to the state-of-the-art technology mapping algorithm, without any performance degradation.

People

Research Manuscript

Dypamear: Efficient and Scalable Dynamic Graph Pattern Mining on Practical Processing-in-Memory Architecture

11:30am - 11:45am PDT Wednesday, July 29 Mtg Room 203AB

Design

DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionDynamic Graph Pattern Mining (DGPM) has been widely applied in various domains. However, existing solutions still suffer from severe memory access bottlenecks due to the irregular and data-intensive nature of DGPM workloads. In this paper, we propose DyPamear, the first full-stack hardware-software co-designed system for accelerating DGPM on practical Processing-in-Memory (PIM) hardware. DyPamear is built atop UPMEM, an emerging commercially available PIM platform. To fully exploit UPMEM's bandwidth and parallelism, DyPamear introduces a cross-layer design that integrates load-aware task distribution, data-driven asynchronous execution, and a degree-adaptive set intersection kernel to balance load and alleviate architectural constraints. Evaluations on real UPMEM hardware show that DyPamear achieves average speedups of 267.38x, 82.52x, and 8.78x over Cheetah, PimPam, and PSMiner, respectively, and scales nearly linearly to 20,480 DPUs. The source codes are available at https://github.com/DyPamear-AE/DyPamear-AE.

People

Yi Zhang

Yu Huang

Deting Chen

Chaoqiang Liu

Haifeng Liu

Institute of Computing Technology, Chinese Academy of Sciences

Xueqi Li

DySL-VLA: Efficient Vision-Language-Action Model Inference via Dynamic-Static Layer-Skipping for Robot Manipulation

Research Manuscript

10:30am - 10:45am PDT Wednesday, July 29 Mtg Room 202C

Systems

SYS3. Embedded Software

Descriptionwe propose DySL-VLA, a novel framework that addresses computational cost by dynamically
skipping VLA layers based on each action's importance. DySL-VLA categorizes its layers into two types: informative layers, which are consistently executed, and incremental layers, which can be selectively skipped. To intelligently skip layers without sacrificing accuracy, we invent a prior-post skipping guidance mechanism to determine when to initiate layer-skipping. We also propose a skip-aware two-stage knowledge distillation algorithm to efficiently train a standard VLA into a DySL-VLA. Our experiments indicate that DySL-VLA achieves 2.1% improvement in success length over Deer-VLA on the Calvin dataset.

People

Shenzhen Institute of Artificial Intelligence and Robotics for Society

Shaoshan Liu

Shenzhen Institute of Artificial Intelligence and Robotics for Society

Meng Li

Peking UniversityPeking University

Research Manuscript

EARL: Entropy-Aware RL Alignment of LLMs for Reliable RTL Code Generation

4:18pm - 4:30pm PDT Monday, July 27 Mtg Room 101A

AI1. AI/ML Frontiers for Hardware Design

DescriptionRecent advances in large language models (LLMs) have demonstrated significant potential in hardware design automation, particularly in using natural language to synthesize Register-Transfer Level (RTL) code. Despite this progress, a gap remains between model capability and the demands of real-world RTL design, including syntax errors, functional hallucinations, and weak alignment to designer intent. Reinforcement Learning with Verifiable Rewards (RLVR) offers a promising approach to bridge this gap, as hardware provides executable and formally checkable signals that can be used to further align model outputs with design intent. However, in long, structured RTL code sequences, not all tokens contribute equally to functional correctness, and naïvely spreading gradients across all tokens dilutes learning signals. A key insight from our entropy analysis in RTL generation is that only a small fraction of tokens (e.g., always, if, assign, posedge) exhibit high uncertainty and largely influence control flow and module structure. To address these challenges, we present EARL, an Entropy-Aware Reinforcement Learning framework for Verilog generation. EARL performs policy optimization using verifiable reward signals and introduces entropy-guided selective updates that gate policy gradients to high-entropy tokens. This approach preserves training stability and concentrates gradient updates on functionally important regions of code. Our experiments on VerilogEval and RTLLM show that EARL improves functional pass rates over prior LLM baselines by up to 14.7%, while reducing unnecessary updates and improving training stability. These results indicate that focusing RL on critical, high-uncertainty tokens enables more reliable and targeted policy improvement for structured RTL code generation. We will release the code upon acceptance. An anonymized repository for review is available at https://anonymous.4open.science/r/EARL-1C25.

People

Engineering Poster

Early Antenna Analysis for IC Design: A Shift-Left Approach to Improve Productivity and Signoff Quality

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAntenna verification is a crucial step in physical design signoff to prevent transistor damage during IC fabrication. Traditional antenna DRC methods, however, are time-consuming and rely on short-free designs, making early analysis difficult when routing shorts or incomplete implementations exist. SoC teams often require early antenna assessments to provide actionable feedback to block owners on interface-level violations, enabling timely corrective measures. Conventional flows force teams to wait for clean designs, delaying detection and slowing overall progress.
Shift-left antenna methodologies address these challenges by enabling early, incremental analysis with 2–6X faster runtimes. Short-aware techniques, combined with selective net and block verification, allow teams to focus on critical areas even when shorts are present. These approaches help identify violations sooner, refine routing strategies proactively, and reduce late-stage fixes. By integrating these flows early in the implementation process,

People

NagaMalleswari Metla

Praneeth Narsingoju

KalyanaKumar Amruthuluri

Early DEF-Based Hierarchical Power Grid Shorts Analysis

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionHierarchical power grid shorts represent a critical challenge in modern chip design, typically discovered late in the schedule during physical verification and LVS analysis at integration, causing significant delays and expensive fixes near tapeout. This work presents an innovative DEF-based methodology to detect power grid shorts early in the PNR flow with exact coordinate reporting. The approach analyzes power and ground net shapes to identify unintended collisions between different net types, particularly for multi-voltage domain crossings. By processing DEF data from individual PNR blocks in the context of their hierarchical placement, the methodology enables shorts identification in hours rather than days. This system integrated at the floorplan level of the PNR implementation flow significantly reduces physical verification churn, eliminates weeks of LVS iteration, and improves design schedule predictability while providing precise location information for rapid resolution.

People

Research Manuscript

Early Design Stage Thermal Prediction and Optimization: Machine-Learning Driven Approach

4:18pm - 4:30pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionAs semiconductor technologies continue to scale toward advanced nodes, the sharp increase in transistor density has led to a substantial rise in on-chip power density, making thermal effects a first-order design concern. Traditional thermal mitigation techniques (e.g., thermal-aware coarse-grained floor-planning, thermal-aware (post-route) cell adjustment, and structural cooling enhancements)
suffer from thermal prediction inaccuracy or incur high fabrication cost, limiting their practical applicability to modern SoC designs. To overcome the limitation, in this work, we present an ML-based early-stage thermal prediction and mitigation framework that enables proactive thermal management in the course of physical design process. Precisely, our approach (1) predicts first the power density map which is the underlying source of thermodynamic behavior during the global placement stage using machine learning models, and then (2) accurately estimates the steady-state thermal map through a physics-guided thermal interpolation. The predicted temperature is subsequently leveraged by (3) an ML-model based optimization engine that adjusts the placement solution to minimize thermal hotspots without timing degradation. Experimental results demonstrate that our proposed model achieves 49.0% and 34.9% accuracy improvement in power density and thermal prediction, respectively, compared to tool estimation. When applied to thermal-aware placement optimization, the framework successfully reduces the maximum chip temperature by 9.97◦C while maintaining equivalent timing and area. These results confirm the effectiveness of our proposed early-stage thermal modeling and optimization framework in improving thermal reliability for modern power-hungry SoCs.

People

Chanhee Jeon

Munwon Lee

Taewhan Kim

Early Thermal Analysis and Silicon Correlation for Face-to-Face 3DIC Physical Design

Engineering Presentation

11:15am - 11:30am PDT Monday, July 27 Seaside RM 7

Chiplet

EDA

DescriptionFace-to-face (F2F) 3DIC integration introduces new thermal challenges due to increased power density, inter-die heat coupling, and limited vertical heat dissipation, making early thermal visibility critical during physical design. This work presents an early-stage thermal analysis methodology jointly developed by the Synopsys RedHawk-ET team and the Broadcom APD AI team to rapidly identify thermal hotspots in F2F 3DIC stackups. The proposed flow leverages early floorplan and power information to enable fast thermal evaluation, allowing designers to proactively adjust floorplanning, power distribution, or die placement to mitigate trapped heat. The methodology is lightweight enough to execute in under a few hours, making it suitable for iterative use during early implementation stages. Correlation with post-silicon thermal measurements demonstrates prediction accuracy within 3 °C across both top and bottom dice. This work highlights practical considerations, tradeoffs, and lessons learned in deploying early thermal analysis as part of a production 3DIC physical design flow.

People

Jason Crop

Broadcom

Sujyesh Aanandh Manjunthan

Early, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICs

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionDue to the increasing size and complexity of high-performance integrated circuits (ICs), especially in advanced technology nodes, the influence of parasitics on the layout has become dominant. Traditional signoff tools and internal scripts often suffer from slow execution, challenging maintenance, and insufficient precision, which limits their effectiveness in addressing the stringent requirements of precision ICs.

To overcome these limitations, a systematic flow for early IC layout parasitic analysis has been developed for quick and efficient detection and debug of parasitic violations. Our shift-left methodology establishes a framework for defining constraints upfront on all critical design nets, enables comparison of multiple layout revisions and provides unique capabilities for verifying large top-level design hierarchies - ensuring robust coverage across diverse design teams and technology nodes.

The flow's scalability allows its adoption for various design styles, facilitating early detection, debugging, and resolution of even minute parasitic violations that would otherwise require lengthy simulation cycles. As a result, design time is significantly reduced by minimizing iterative simulation runs, leading to substantial savings in hardware resources and software license requirements for simulation tools. This systematic early parasitic analysis flow represents a transformative advancement for precision IC development, delivering enhanced design quality, reliability, and productivity.

People

Research Manuscript

EastPCG: An Efficient and Self-Tuning Graph Sparsification Based PCG Solver for Circuit Simulation

4:30pm - 4:42pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionGraph spectral sparsification plays an important role in extensive EDA applications. For preconditioned conjugate gradient (PCG) solvers, graph spectral sparsification is a promising preconditioning technique in both theory and practice. In this paper, a highly efficient and stable graph sparsification algorithm based on spectral probability is proposed. Meanwhile, targeting at minimum total solution time of the linear equation with multiple right-hand sides, an efficient self-tuning PCG framework powered by neural networks is proposed. Combining the proposed techniques, an efficient and self-tuning graph sparsification based PCG solver, named EastPCG, is finally developed. Extensive experiments on various benchmarks have demonstrated the advantages of the proposed algorithms over existing counterparts.

People

Research Manuscript

EASY-ZKP: An End-to-End FPGA-Accelerated System for Zero Knowledge Proofs

3:30pm - 3:42pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionZero-knowledge proofs (ZKPs) enable parties to prove possession of information without disclosure, strengthening privacy and security. However, ZKP proof generation suffers from high computational and memory overheads. We present EASY-ZKP, an end-to-end FPGA-accelerated ZKP system with multi-scalar multiplication (MSM) and number theoretic transform (NTT) architectures that improve performance and balance resources for efficient FPGA co-deployment. We further develop an automated design space exploration framework that minimizes latency under resource constraints. Prototyped on a Xilinx Alveo U280, EASY-ZKP achieves up to 19.5× speedup over a CPU implementation and up to 7.7× better energy efficiency than a GPU implementation.

People

Illinois Advanced Research Center at Singapore

Wei Zhang

Shandong University of Technology

Lei Ju

Shandong University of Technology

Engineering Poster

ECO Strategy for BIG DIE SOC Convergence

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionThe SSIR Customer Design Service (CDS) team supports projects spanning big die AI, automotive, and HPC SoCs. Schedules and designs demand static timing analysis (STA) and engineering change order (ECO) flows that close designs quickly. An ECO strategy for a large die AI SoC is difficult: the design contains about 1.6 billion instances, must meet a 1.6 GHz target, and relies heavily on multiply-instantiated-modules (MIM). MIMs complicate violation fixes because each change must be evaluated for impact on other MIMs. Additional challenges include clock path skew, extensive boundary models (BMs), and long data paths, all hindering a sustainable ECO methodology.

To address these issues, the team adopted a "divide and conquer" policy. Multiple STA models with BMs were generated for the top level, enabling parallel analysis and reducing compute load and turnaround time. The CERTUS platform, with its advanced high capacity (HC) ECO engine, prunes the netlist by identifying violations, making the flow lightweight and efficient. At the block level, Twopass and Paradigm were used as ECO tools to converge the design. SSIR worked closely with Cadence field and R&D groups to tailor the flow, creating a recipe that significantly improves fix rates while preserving timing, logical DRCs, and legalization.

People

Chetan B S

Ecprefix: Erasure-Coded Prefix KV Cache for Optimizing Load Balancing in Large Language Model Serving

Research Manuscript

3:56pm - 4:10pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionPrefix KV cache is widely used to accelerate LLM serving by trading more storage for less computation, and state-of-the-art methods often replicate hotspot caches for load balancing. However, we observe that the few nodes that have cache replicas still lead to severe load imbalance. This paper presents ECPrefix: a new prefix KV cache framework based on erasure coding (instead of replication), which distributes encoded blocks of hot prefix caches (organized as profile-guided objects) across nodes, along with adaptive striping and pipelined reading optimizations. Evaluation shows that ECPrefix reduces TTFT by up to 52.3% over existing systems.

People

Feifan Liu

Yuchong Hu

Mingqi Li

Lin Wang

Chenxuan Yao

Zhenghao Yu

Dan Feng

EDA Opportunities in Building High Performance AI Accelerators

SKYTalk

10:15am - 11:00am PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

EDA

DescriptionThe rapid growth of artificial intelligence (AI) applications is driving unprecedented demand for high‑performance, energy‑efficient AI accelerators, placing new and complex demands on Electronic Design Automation (EDA) flows. Scaling these designs from chips to full systems introduces challenges that traditional EDA methodologies were not built to handle.

With increasing accelerator size and complexity, traditional EDA tools and methodologies face challenges spanning advanced process nodes, large‑scale parallelism, and system‑level performance and data movement. These issues increasingly emerge at the boundaries between compute, memory, interconnect, and software behavior, where system‑level interactions has significant impact on design outcomes. In addition, the speaker will discuss the evolving landscape of EDA tools, highlighting the augmentation of conventional methodologies with AI-driven approaches to better address the increasing intricacy and verification demands in hardware design. Emerging trends such as hardware‑software co‑design, faster iteration through prototyping and comprehensive design‑space exploration are discussed as key approaches to addressing these challenges.

Attendees will leave with practical insights into current limitations of EDA at AI scale, emerging solutions being deployed in production environments, and the implications for next‑generation accelerator and system design – from silicon architects to EDA practitioners working across the full chips‑to‑systems stack.

People

Artour Levin

Microsoft

Work in Progress

EdgeQ‑GEMM: INT4/INT8 Mixed‑Precision GEMM Accelerator with On‑the‑Fly Quantization for Accuracy–Energy Tunability in Edge AI Processors

6:34pm - 6:35pm PDT Monday, July 27 Exhibit Hall

DescriptionEdge workloads such as keyword spotting and activity recognition must process continuous FP32 sensor data under tight power–performance–area budgets, making full-precision GEMM units impractical. EdgeQ-GEMM is a compact, processor-integrated INT4/INT8 mixed-precision GEMM accelerator that performs on-the-fly quantization and computation without FP hardware. It supports two modes: adaptive mode, dynamically quantizing FP32 activations to INT4 or INT8 using a design-time QCM to expose a tunable accuracy–energy design space, and layer-wise mode, executing QAT/PTQ models with layer-mixed INT4/INT8 weights by applying on-the-fly INT32-to-INT8 activation quantization. Implemented in edge AI processors and validated via FPGA and 45nm synthesis, EdgeQ-GEMM enables efficient, flexible precision adaptation for diverse workloads.

People

Research Manuscript

Edgesc: Universal Stochastic Computing Architecture for Efficient Edge Detection

2:34pm - 2:47pm PDT Wednesday, July 29 Mtg Room 101A

AI3-II. AI/ML Application and Infrastructure

DescriptionStochastic computing (SC) enables compact and low-complexity hardware but remains underexplored for vision applications. We propose EdgeSC, a unified stochastic framework that extends edge detection to diverse and composite operators. Pixel intensities are encoded as stochastic bitstreams, and gradients are computed through finite-state machines (FSMs) ensembles operating in the probability domain. A differentiable MUX mapping learns operator-specific behaviors without changing the architecture. Fabricated in 28-nm CMOS, EdgeSC achieves 15.9$\times$ smaller area, 4.4$\times$ lower power, and 6.3$\times$ better area-delay product than 8-bit baselines while maintaining comparable accuracy and throughput.

People

Xincheng Feng

Wenyong Zhou

Taiqiang Wu

Zhengwu Liu

Peking UniversityPeking University

Meng Li

Ngai Wong

Efficient Electromagnetic Extraction of Superconducting Circuits Used with Quantum Computers and Rapid Single Flux Quantum Designs

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionQuantum computing is a promising technology for cryptography and optimization problems. Additionally, rapid single flux quantum (RSFQ) circuits are a promising technology for an interface with the quantum computer in the cryogenic chamber to reduce the number of connections required. Design of these superconducting systems requires accurate modeling of the resonant frequency of the quantum computing readout resonators, and the inductance of the RSFQ interconnect. One challenge in the design process is the time required to determine the layout of the system to achieve performance targets. Also, most commercially available extraction tools do not model the kinetic inductance present at cryogenic temperatures. Some extraction tools do exist which model kinetic inductance, and these can be used to model arbitrary cryogenic structures, but these tools are not integrated into the standard integrated circuit (IC) design platforms, require expertise to run, and have limited capacity.
We propose using a high-capacity partial element equivalent circuit (PEEC) solver with automated geometry simplification and integrable with common IC design platforms to quickly design the superconducting structures to verify circuit performance. We demonstrate accuracy by comparing with measured data and extractions with other tools. We demonstrate capacity by extracting a representative shift register.

People

Garth Sundberg

Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks

Research Manuscript

11:50am - 12:03pm PDT Monday, July 27 Mtg Room 201B

EDA

EDA5. RTL/Logic Level and High-level Synthesis

DescriptionHigh-level synthesis (HLS) and multi-die FPGAs have been widely applied in large-scale accelerator design. To address cross-die boundary delays and local congestion issues in HLS designs on multi-die FPGAs, prior work proposed a coarse-grained floorplanning and pipelining method to improve frequency performance. However, achieving higher frequency still requires multiple iterative implementations in Vitis to tune parameters, incurring significant time overhead. To accelerate this process, we propose a graph neural network (GNN) based floorplan quality predictor at the FPGA slot level, achieving an accuracy of 84.13% and an F1-score of 0.86 in the congestion prediction task, with an average inference latency of only 0.58ms. Compared with the traditional tool flow that requires tens of hours, our method enables millisecond-level floorplan parameter fine-tuning, improving an unroutable and 318.2MHz case to 329.2MHz and 330.3MHz, respectively. Furthermore, we integrate our method into the HLS design-space exploration framework, achieving an average frequency improvement of 11.2%, with the maximum improvement reaching 23.8%. The execution time of all benchmarks is reduced by 30.9%.

People

Haoran Xue

Qianyu Cheng

Zhendong Zheng

Xi Li

Efficient IR-Aware Powergrid Optimization

Engineering Presentation

4:15pm - 4:30pm PDT Monday, July 27 Seaside Ballroom A

EDA

Systems

DescriptionAs design sizes and complexities grow, IR-drop is increasingly becoming a long-pole activity towards final signoff of digital designs. Manual fixing of IR issues in complex grids is iterative, time-consuming and often non-converging. Industry has used some form of IR-fixing ECO strategy – but those are custom and could not be generalized. With the pre-trained IR analytics and full integration into a P&R engine, Cadence Voltus InsightAI is expected to help improve turnaround time of powergrid closure for IR by automatically reinforcing the grid with additional stripes where needed. For that to work, a detailed design impact analysis is needed to create a comprehensive methodology encompassing the tool capabilities and working around its limitations. This paper will discuss that.

People

Harshit Pratik

Sharath C R

Texas Instruments

Rohit Somwanshi

Efficient Power Management in USB4 Routers

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionEfficient power management is essential to address the growing demand for low-power connectivity solutions. It aligns with mobile compute, always on, and compute everywhere initiatives, offering increased battery lifetime, and strengthens the competitiveness of our IPs. We have developed an innovative power management architecture that standardizes processes for low-power entry and exit across various protocol adapters in USB4 routers. This streamlined approach not only enhances overall energy efficiency but also simplifies the router's power management architecture. The successful integration of our USB4 router IP -- featuring the power management function -- into a major customer's silicon has yielded remarkable outcomes, validating the effectiveness of our solution.

People

Engineering Presentation

Efficient Power Modeling of Multi-Domain Clock Gating Circuits

1:30pm - 1:45pm PDT Tuesday, July 28 Seaside RM 7

Design

EDA

DescriptionStandard LCBs (Local Clock Buffers) drive a single clock gating domain and are controlled by a single clock enable signal. Even for smaller domains, the same LCB is used for clock gating, leading to a large number of under-loaded LCBs. Multi-domain clock gating circuits (or Micro Clock Gated, MCG) were introduced for handling such scenarios and for power savings. MCG LCBs drive multiple domains and have additional enable signals for separate control of each domain. Power modeling and analysis of micro-gating has its own set of challenges. Simpler approaches (averaging etc.) do not give an accurate picture of power dissipation, making it difficult to gauge the power savings obtained using micro clock gating. For correct power estimation and assessment of right set of tradeoffs during optimization, we need 1) a power model accounting for all modes of operation 2) micro domain power granularity for accuracy 3) manageable size of the power model for efficiency in both, modeling and analysis 4)one model for use across different power flows with appropriate activity signatures. In this presentation, we propose efficient and accurate power modeling techniques for MCG circuits using IEEE 2416 artifacts.

People

Engineering Presentation

Efficient Routing and Connectivity Repair for Large-Scale Hierarchical Metal Networks

2:00pm - 2:15pm PDT Wednesday, July 29 Seaside RM 7

EDA

DescriptionPower, clock, and tie networks in modern designs form massive, multi-layer, and hierarchically distributed metal connected components with millions of shapes. Accurately modelling and maintaining connectivity for such nets is critical throughout the physical design flow, yet existing approaches rely on static spatial partitioning, leading to poor scalability, excessive runtime, and incorrect connectivity artifacts in hierarchical layouts.
We present a bottom-up, shape-driven method to construct the smallest possible metal connectivity subgraphs using dynamic region queries and disjoint-set union structures. The approach enables scalable, parallel connectivity modelling while preserving synchronization between physical and logical connectivity. To handle hierarchical pin and power interactions, we introduce a pin-accessibility graph that explicitly models reachability and filters redundant guides using a graph-based algorithm. The resulting subgraphs enable independent and parallel execution of connectivity repair, tie-net routing, and traversal operations. Experimental results on production designs demonstrate up to a 60× runtime reduction with near-linear multi-thread scalability. The method is deployed in industrial server and ASIC design flows, enabling fast, correct, and scalable connectivity processing for large-scale metal networks.

People

Research Manuscript

EHPC: Efficient Heterogeneous Probabilistic Computing Architecture for Combinatorial Optimization Acceleration

4:54pm - 5:06pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionIn this work, we propose an efficient heterogeneous probabilistic computing (EHPC) architecture based on volatile RRAM to accelerate combinatorial optimization. We fabricated the OxRAM-multiplexed EHPC circuit and successfully used it to solve max-cut problem. In hardware simulations of max-cut problems, EHPC achieves a superior solution quality to existing works in under 1s, using the same computational resources. The results of the floorplanning problems demonstrate that our EHPC architecture significantly boosts computation speed, ranging from 20× to 1,500×, with area expansion <1.7% compared to the best-performing conventional methods, highlighting its advantages in speed, efficiency, and scalability for solving COPs.

People

Research Manuscript

eLLM: Elastic Memory Management Framework for Efficient LLM Serving

4:30pm - 4:42pm PDT Tuesday, July 28 Mtg Room 101B

AI5-I. AI/ML System and Platform Design

DescriptionGPU memory management is critical for efficient Large Language Model (LLM) serving. LLM memory usage primarily comprises weights, activations, and KV caches. While weights are static, activations and KV caches exhibit dynamic and unpredictable behavior, posing significant memory management challenges. Modern LLM serving systems address this through a dual-level approach: activations inherit static tensor abstractions from deep learning frameworks, while KV caches employ specialized page-table virtualization (i.e., PagedAttention). Although this reduces KV cache fragmentation, the fundamental isolation between activation and KV cache management prevents memory sharing across these spaces, leading to suboptimal utilization and 20\% throughput degradation.

To address these limitations, we propose eLLM, an elastic memory management framework. The core components of eLLM include:(1) Virtual Tensor Abstraction: Decouples the virtual address space of tensors from physical GPU memory, creating a unified and flexible memory pool;(2) Elastic Memory Mechanism: Dynamically adjusts memory allocation through runtime memory inflation and deflation, and leverages CPU memory as an extensible buffer;(3) Lightweight Scheduling Strategy: Employs Service-Level Objective (SLO)-aware policies to optimize memory utilization and effectively balance performance trade-offs under stringent SLO constraints.
Comprehensive evaluations demonstrate that eLLM outperforms state-of-the-art systems, achieving up to 2.32$\times$ higher throughput.

People

Yi Xiong

University of Science and Technology in China

Jiale Xu

Yangjie Zhou

Weiming Hu

Hao Wu

Ant Group

Boyu Li

Junping Zhao

Ant Group

Minyi Guo

Jingwen Leng

zongwei zhu

ELMBA: Escape from Local Minima in Buffer and Splitter Insertion for AQFP Circuits

Research Manuscript

10:43am - 10:56am PDT Tuesday, July 28 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionAdiabatic Quantum-Flux-Parametron (AQFP) is a promising superconducting logic family that combines ultra-low power consumption with high-speed switching. However, the extensive insertion of buffers and splitters (B/S) to satisfy fan-out and synchronization constraints significantly increases circuit area and depth, becoming a key bottleneck in AQFP synthesis. Existing heuristic approaches are lightweight but prone to local optima, while global or exact methods achieve higher solution quality at the expense of runtime and scalability. In this work, we propose the first Large Neighborhood Search (LNS)-guided framework for AQFP B/S insertion, which combines multi-granularity group movement with a destruct-and-repair paradigm to systematically escape local minima while ensuring legality through constraint-aware repair. Extensive experiments on ISCAS'85 and EPFL benchmarks show that our framework achieves up to 14.0% fewer B/S insertions and 13.1% fewer junctions on large EPFL circuits, while yielding the lowest circuit depth among state-of-the-art methods. It also attains up to a 3.1× runtime speedup on large benchmarks, and on the ISCAS'85 suite reduces B/S and JJs by 13.0% and 8.1% respectively.

People

Yanshuang Teng

SSSLab, China University of Petroleum-Beijing

Rongliang Fu

SSSLab, China University of Petroleum-Beijing

Xijie Wang

Research Manuscript

Emudrop: A Minimalistic, Hardware-Based Emulation Detection Approach Through Intel Reserved Opcodes

12:03pm - 12:16pm PDT Tuesday, July 28 Mtg Room 202AB

Security

SEC3-I. Hardware Security: Attack and Defense

DescriptionEmulation-based dynamic analysis detects malicious software by observing runtime behavior in a controlled environment.
Malware increasingly adopts evasion techniques to recognize such environments and hide malicious activities.
In this paper, we propose EmuDRop, a minimalistic emulation-detection attack that exploits Intel reserved opcodes.
EmuDRop leverages microarchitectural differences between real hardware and emulators to identify emulated execution.
We reverse-engineer reserved opcodes, characterize their microarchitectural effects, and evaluate EmuDRop on five Intel CPU cores and QEMU, a widely used and representative emulator.
The results show that EmuDRop reliably identifies emulated environments.

People

Kaiyuan Rong

Key Laboratory of System Software (Chinese Academy of Sciences) and State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences

Ke Fang

Pengfei Qiu

Key Laboratory of System Software (Chinese Academy of Sciences) and State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences

Dapeng Ju

Tsinghua University & Zhongguancun Laboratory

Dongsheng Wang

Tsinghua University & Zhongguancun Laboratory

Engineering Presentation

Enabling AI Agent Flows for Verification Triage & Debug

10:45am - 11:00am PDT Tuesday, July 28 Seaside Ballroom A

Design

EDA

DescriptionVerification remains the most time-consuming phase of hardware development, with millions of simulation jobs generating diverse fail signatures. Manual triage and root cause analysis (RCA) of these failures is a critical bottleneck, consuming significant engineering effort and requiring specialized expertise.
We present an AI-driven approach that leverages agentic workflows to automate and accelerate fail triage and debug. Our solution integrates heterogeneous verification context—design specifications, HDL, waveforms, coverage data, and prior issues—through Model Context Protocol (MCP) servers, enabling agents to retrieve and correlate information efficiently. Customized agents iteratively process simulation traces, extract cone-of-influence logic, and correlate transactions with waveform and coverage data. Deployed in IBM Z hardware verification, these flows have demonstrated substantial productivity improvements, estimated reduction of manual effort by 15-40% and enhanced overall verification throughput. This work also provides insights into MCP integration challenges such as context bloat and API granularity and outlines best practices for implementing AI-driven debug solutions in complex hardware environments.

People

Research Manuscript

Enabling AI ASICs for Zero Knowledge Proof

5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 203C

Security

SEC4. Embedded and Cross-Layer Security

DescriptionZero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a layout-stationary CPU–TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles and maintain full matrix-unit utilization. Implemented in JAX/XLA, MORPH enables TPUv5p for better energy efficiency and comparable performance on MSM and NTT than SotA implementations on GPUs.

People

Jianming Tong

Jingtian Dang

Massachusetts Institute of Technology

Simon Langowski

Tianhao Huang

Massachusetts Institute of Technology

Massachusetts Institute of Technology

Tushar Krishna

Enabling Automated Software Testing in Emulation Environments via Fastboot Virtualization and On-Premises LLM-Based Failure Analysis

Engineering Presentation

4:15pm - 4:30pm PDT Monday, July 27 Seaside Ballroom B

Design

EDA

Systems

DescriptionAutomated software testing that integrates Android driver features is widely adopted in post-silicon environments to improve software robustness through unattended flashing, reboot, recovery, and failure analysis workflows. Such automation workflows leverage multiple Android interfaces, including ADB and fastboot, to support device control, recovery, and post-failure log collection. Applying these automated testing workflows in pre-silicon environments, particularly emulation-based platforms, is highly desirable, as it enables real software bugs and robustness issues to be discovered and mitigated early in the development cycle, prior to silicon availability.

However, extending automated software testing to pre-silicon emulation environments faces two independent challenges. First, fastboot is not natively available in pre-silicon platforms. Although fastboot is technically feasible via USB, it is prohibitively slow for use in emulation environments. In contrast, ADB demonstrates that host–target connectivity can be realized through virtualized communication mechanisms in pre-silicon–like environments, motivating a similar approach for fastboot. Second, even when failure detection is automated, test platforms still struggle to determine whether a detected kernel panic represents a genuine software bug or a non-critical event, such as a bring-up artifact. Moreover, the use of external large language models, such as ChatGPT, is often restricted by security and data confidentiality requirements.

To address these challenges, we present an unattended end-to-end software test automation framework for pre-silicon emulation environments that integrates fastboot virtualization with an on-premises LLM-based failure analysis pipeline. The proposed framework has been validated in an ongoing flagship SoC project, demonstrating early discovery of real software bugs and improved system readiness at silicon bring-up.

People

Engineering Presentation

Enabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power Modeling

4:30pm - 4:45pm PDT Monday, July 27 Seaside Ballroom A

EDA

Systems

DescriptionAs semiconductor designs scale toward higher power densities and heterogeneous integration, the prediction of thermal behavior at early design stage becomes essential for both performance and reliability. Conventional board-level thermal models use simplified uniform power assumptions which fail to capture localized hotspots. Whereas high resolution power maps generated require high design collaterals, which are available only at sign-off, and are computationally expensive.

We overcome these limitations by creating a high-resolution, tile-based power map using the instance power and location files from the implementation tools and on-die routing information from GDSII file of a former design. This generates the detailed power map nearly 2x faster, with less than 2% loss in accuracy compared to the currently available methods of generation using EM-IR sign-off tools.

We demonstrated this method on a 2DIC design with the power map consisting of multiple blocks of different functionalities stitched together. The package model and heat sink system is included. The junction temperatures obtained using this method yielded 4-5°C more accurate temperatures against simplified block power based thermal analysis. This methodology helps in analyzing the thermal behavior of the chip at very early design stages and designing appropriate system level cooling solutions.

People

Aakrati Jain

IBM Research

Sujyesh Aanandh Manjunthan

Enabling PSS-Driven Early SoC Verification By Enriching IP-XACT Information

Cheng Chi

IBM Research

Engineering Presentation

11:30am - 11:45am PDT Monday, July 27 Seaside Ballroom B

EDA

Systems

DescriptionModern SoC designs increasingly exhibit functional corner-case bugs that remain hidden until silicon validation. The failure to uncover corner-case bugs can be primarily attributed to two factors: SoC-level specification incompleteness and limitations in the verification environment.
Leveraging the fact that IP-XACT is widely adopted in integration flows to manage SoC-level design metadata(hierarchy, interface protocol, connectivity, address, signal behaviors), we proposed an automated methodology that generates a complete PSS(Portable Test and Stimulus Standard) model directly from IEEE-1685 IP-XACT metadata, thereby eliminating manual RTL-path coding effort and expanding functional coverage.
By parsing multiple IP-XACT XML files, we construct a unified JSON-based modeling database that facilitates a seamless transition to PSS structured models. From this database, structural PSS components that were base models for generating test scenarios are built automatically.
By associating the SoC-level behaviors extracted from IP-XACT specifications with the structured PSS models and IP-level action libraries, our approach systematically generates test cases targeting specific ports. In a realistic case study, the resulting model enables systematic behavior exploration and significantly expands functional coverage, achieving approximately a 30% increase in total coverage bins through automatic enumeration of design-derived function conditions.

People

Research Manuscript

Enabling Robust On-Device Personalization via Pulse-Based Mapping and Noise Suppression for Non-Ideal CIM Architecture

11:45am - 12:00pm PDT Wednesday, July 29 Mtg Room 203AB

Design

DES2B-II. In-memory and Near-memory Computing Architectures, Applications and Systems

DescriptionComputing-in-memory (CIM) architectures alleviate the data movement bottleneck by performing neural computations directly within memory arrays, which significantly addresses the resource constraints for edge AI applications. As edge applications increasingly demand user-specific adaptation, on-device deep model personalization has become essential for supporting evolving environments, privacy-sensitive data, and low-latency intelligence. However, in CIM-based systems, deep model parameters cannot be efficiently extracted for external fine-tuning due to the high cost of reading, digitizing, and transferring analog device states. Consequently, personalization is expected to be executed directly on the CIM hardware through in-situ weight updates. Prior works have focused primarily on improving inference robustness under non-ideal CIM conditions, leaving the problem of robust on-device fine-tuning fundamentally unaddressed. To fill the gap, we propose CIM-MP, a hardware–software co-optimized framework enabling stable and accurate on-device personalization under noisy CIM conditions. CIM-MP introduces a pulse-based mapping strategy that ensures convergence during in-memory weight updates. To further enhance robustness, we propose a Feature Variation Elimination (FVE) mechanism to mitigate feature-map noise in forward propagation, and a Gradient Adaptive Purification (GAP) mechanism to refine gradients during backpropagation. Experiments show that CIM-MP achieves up to 35.1% accuracy improvement over state-of-the-art approaches, demonstrating the feasibility of efficient and robust on-device learning directly on CIM platforms.

People

Engineering Poster

Enabling Time-Aware Systems Across Silicon-System Boundary

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionTime is a fundamental physical resource in silicon, yet in most system architectures it remains an implicit and locally confined assumption. While monolithic cyber physical systems operate effectively with stable local clocks and design time temporal constraints, these abstractions break down as systems scale across distributed nodes and networks. Network uncertainty amplifies timing errors, and the lack of system level time control limits scalable coordination and collaborative intelligence. This work presents an agile time aware system architecture that elevates time from a hidden local property to an explicit and controllable system resource. The architecture is enabled by a flexible silicon level time primitive that provides unified control and observation of clock frequency, phase, and time across hardware, runtime, network, and application layers. The proposed architecture enables fine grained frequency and phase control while maintaining architectural composability beyond protocol centric synchronization mechanisms. The effectiveness of the approach is demonstrated through hardware based multi node synchronization experiments, showing a transition from passive drift to active convergence under varying node counts and uncertainty conditions. The results indicate improved scalability, robustness, and design reuse without architectural redesign, providing a practical foundation for time aware system design that bridges the silicon system boundary.

People

Xiangye Wei

TAF Circuits Co., Ltd.

Liming Xiu

TAF Circuits Co., Ltd.

Research Manuscript

ENACT: Ensemble Neural Fields for Reactive Robot Control

4:06pm - 4:18pm PDT Wednesday, July 29 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionTracking moving targets through clutter and occlusions demands real-time sensorimotor control that adapts to dynamic uncertainty. Model predictive control (MPC) incurs high computational cost, while reinforcement learning requires task-specific retraining. We introduce ENACT (Ensemble Neural Attractor Components for Tracking), a modular framework decomposing reactive control into coordinated Dynamic Neural Fields (DNFs). Each DNF module---attention, gating, memory, context---addresses a distinct sensorimotor primitive through continuous attractor dynamics, enabling runtime reconfiguration without retraining. We benchmark ENACT on both simulation and a Cortex-M7 microcontroller, showing up to 86% lower tracking RMS error, ~2.8x faster disturbance-recovery times, predictable sub-millisecond control latency, and ~9x lower SRAM footprint compared to MPC baseline.

People

Hammad Omar

University of Texas at Dallas

Ismail Mohamed

University of Texas at Dallas

Mohamed Ibrahim

University of Texas at Dallas

Research Special Session

End-to-End Physical Design Automation Flow for Yield-Optimized Inverse-Designed Large-Scale Electronic-Photonic Integrated Circuits

2:00pm - 2:30pm PDT Wednesday, July 29 Mtg Room 201A

EDA

DescriptionThis talk presents an open-source end-to-end physical design automation flow for yield-optimized, inverse-designed EPICs. We integrate three key components: (1) AI-augmented photonic inverse design and inverse lithography framework; (2) GPU-accelerated routability-optimized PIC placement; and (3) curvy-aware photonic routing with electrical-optical co-routing. This flow synthesizes EPIC netlists into fabrication-ready, yield-robust GDS layouts within an hour, enabling scalable photonic tensor cores and interconnects for next-generation AI systems. This work establishes a first-of-its-kind open-source foundation for large-scale, manufacturable EPIC design.

People

Jiaqi Gu

Energy-Efficient Edge AI and Autonomy

Tutorial

9:00am - 12:30pm PDT Sunday, July 26 Mtg Room 202AB

DescriptionThis tutorial provides an accessible entry point for designers across the low-power design space working on power-constrained on-device intelligence. It covers the landscape of low-power edge intelligence from algorithm, architecture, circuit, and application perspectives. The four-talk progression addresses: low-power on-device ML, memory-efficient algorithms for edge inference, neuro-inspired approaches to edge intelligence, and streaming processing in autonomous edge platforms. The tutorial serves a broad DAC audience in machine learning, including those working in edge AI or neuromorphic computing, while highlighting emerging energy-efficient edge computing and system research.

People

Saibal Mukhopadhyay

Arnab Raha

Hun-Seok Kim

Kaushik Roy

Purdue University

Saibal Mukhopadhyay

Energyhdc: Intermittent Hyperdimensional Inference on Energy-Harvesting IoT

Research Manuscript

11:23am - 11:36am PDT Tuesday, July 28 Mtg Room 202C

Systems

SYS2. Design of Cyber-Physical Systems and IoT

DescriptionAmbient energy harvesting technologies offer the promise of perpetual operation for batteryless Internet of Things (IoT) devices; however, their execution is frequently halted by unpredictable power failures. Traditional methods to ensure correctness, such as software checkpointing (e.g., Mementos) and newer systems for deep neural networks (e.g., DynBal), are burdened by substantial energy and latency overheads for progress preservation, limiting their use on ultra-low-power platforms. This paper introduces EnergyHDC, an energy-aware inference system designed for intermittent operation by integrating Hyperdimensional Computing (HDC). The system pairs HDC's algorithmic robustness with fine-grained energy adaptation using three key contributions: (1) an energy-proportional checkpointing that optimizes preservation granularity against available energy; (2) a dimension-first reordering that slashes per-checkpoint storage; and (3) a priority-based pruning that allows for compile-time energy-accuracy trade-offs. Evaluated on an MSP432P401R microcontroller platform under intermittent power, EnergyHDC demonstrates up to 214x speedup compared to Mementos. It also achieves 19.6x faster inference than DynBal under similar accuracy and realistic energy-harvesting conditions. These results validate that a co-design approach, coupling energy-aware execution with HDC's intrinsic robustness, can reframe intermittence from a system constraint into an opportunity for efficient edge intelligence.

People

YUSHENG LIU

National Yang Ming Chiao Tung University (NYCU)

Yong-Cheng Liaw

National Yang Ming Chiao Tung University

Shuo-Han Chen

National Yang Ming Chiao Tung University

Keynote

Engineering Life - Where Biology and Technology Meet

9:00am - 10:00am PDT Wednesday, July 29 Grand Ballroom

Design

DescriptionIn a keynote address at the 2007 Design Automation Conference, I discussed the potential of an emerging technology known as synthetic biology and the role integrated circuit design methodology could play in shaping this nascent field.

Now almost 20 years later, synthetic biology has matured significantly. Today It offers the opportunity not only of addressing genetic diseases, but also of engineering life itself. In fact, we are witnessing the simultaneous emergence and explosive growth of three technologies that are bound the shape of the future of humanity: genetic engineering (such as enabled by CRISPR-CAS9), artificial intelligence, and brain-machine interfaces (BMIs).

While all three are equally influential, this presentation will focus primarily on the latter – that is, direct interfaces with the human brain. Brain-machine interfaces are systems that create a direct communication pathway between the brain and external devices. By translating neural signals into actionable information, BMIs can be used to restore lost abilities, augment human capabilities, and enable entirely new forms of interaction with technology. They hold the promise of revolutionizing fields such as medicine, rehabilitation, neuroscience, and even human-machine collaboration.

We will review the state-of-the-art, identify progress, speculate where it may lead, and address some pertinent questions such as privacy and morality implications. But most importantly, we will explore the essential role that the design community can —and must—play in the conception, design, integration and deployment of these groundbreaking technologies.

People

Jan M. Rabaey

University of California at Berkeley

Engineering Poster

ENHANCED AUTOMATION FOR GENERATING LOGIC-OPTIMIZATION ECOs (EAGLE) IN SIGNOFF

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern high-performance digital circuits face significant challenges in achieving optimal timing closure due to the complexity of designs with millions of transistors. While APR tools provide sophisticated optimization capabilities, they often compromise on local optimizations due to global constraints, tool limitations, and PPA trade-offs. Non-optimized structures residing on critical paths directly impact on the achievable operating frequency, creating performance bottlenecks. During the ECO phase, setup violating paths undergo re-ordering, creating opportunities for logic optimization. The positive slack paths, which were not optimization targets during synthesis, become exposed during ECOs and offer greater potential for logic optimization to achieve timing targets. However, current solutions suffer from lack of Primetime compatibility and absence of direct APR tool integration, necessitating manual intervention that extends design closure timelines. EAGLE overcomes these constraints through a comprehensive Primetime-integrated framework that leverages ECO-phase optimization opportunities and delivers APR tool-compatible ECOs directly.

People

Research Special Session

Enhancing Scientific Discovery via Reliability vs Performance Trade-Offs for Scientific Computing at Sun-Earth L2

12:00pm - 12:30pm PDT Tuesday, July 28 Mtg Room 201A

DescriptionNASA's Habitable Worlds Observatory (HWO) will directly image Earth-like exoplanets by suppressing starlight by a factor of 10−10 using a coronagraph instrument. Maintaining this suppression requires a closed-loop control system—high-order wavefront sensing and control (HOWFSC)—that continuously corrects optical aberrations by commanding deformable mirrors. The dominant computational kernel is a dense matrix-vector multiply (GEMV) with a precomputed gain matrix exceed- ing 106 GB in double precision at flight scale. The memory bandwidth demanded by this kernel at the required control frequency exceeds radiation-hardened processors by orders of magnitude, motivating deployment on commercial off-the-shelf (COTS) hardware aboard a co-flying satellite at Sun-Earth L2—outside Earth's magnetosphere, where single-event upsets (SEUs) from galactic cosmic rays and solar particles can corrupt computation. We apply Algorithm-Based Fault Tolerance (ABFT) to protect this GEMV. The gain matrix is severely ill-conditioned (singular values spanning 66 decades), causing checksum noise floors that challenge naive ABFT. We address this with row- scaling preconditioning and analytically derived Higham-bound adaptive thresholds that require no empirical tuning. Using physically realistic gain matrices from a FALCO coronagraph model at two actuator scales, we demonstrate 100% detection of all science-threatening faults with zero false positives and ∼6 orders of magnitude of margin between the noise floor and the dangerous-fault threshold. We further show that the gain matrix can be stored in reduced precision—as few as 23 mantissa bits with block floating point—reducing memory by 62% while consuming less than 0.03% of the contrast error budget.

People

Barry Lyu

Vaibhavi Manjarekar

Nathan Bleier

Enhancing the Robustness of Impinj RAIN RFID Design Through the Application of AI-Powered Process Flow

Engineering Poster

5:00pm - 6:00pm PDT Tuesday, July 28 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionUHF RFID tagging is the fastest-growing segment of the RFID market, connecting billions of items worldwide. By enabling internet connectivity and real-time visibility into everyday objects—such as apparel, medical supplies, automotive parts, and food—Impinj RAIN RFID facilitates truly scalable Internet of Things (IoT) applications. As performance requirements for Impinj RAIN RFID systems continue to increase, designs must achieve higher sensitivity and accuracy while maintaining low power consumption. Meeting these performance requirements for billions of Impinj RAIN RFID tag chips presents significant verification challenges, where achieving high-sigma verification across all process, voltage, and temperature (PVT) corners typically requires a large number of simulations and hence long turnaround times.

To address these challenges, Impinj and Siemens EDA have collaborated on an advanced verification workflow that enables efficient high-sigma verification across PVT corners. Siemens EDA's Solido PVTMC tool intelligently identifies worst-case corners at higher sigma levels, significantly reducing the number of required simulations. When combined with the Solido SPICE simulator, this approach allowed Impinj to accelerate verification runtimes while meeting stringent accuracy and reliability targets. This presentation slide deck presents the workflow and highlights its impact on Impinj RAIN RFID design verification.

People

Engineering Poster

Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionAnalog Compute-In-Memory performance in 3D heterogeneous chiplet integration is highly sensitive to spatial temperature gradients and temporal temperature fluctuations. Conventional thermal sign-off based on the maximum junction temperature is insufficient for ensuring the memory algorithmic precision across diverse operational phases. This study proposes a System-Technology Co-Optimization (STCO) framework featuring Thermal Avoidance and Thermal Compensation strategies to enhance spatial-temporal temperature uniformity. The approach synergizes hardware-level spatial optimization, such as selective transistor density reduction and controllable heating element deployment, with software-level temporal regulation, such as load-rate modulation and dummy workflow supplement. The proposed strategies are validated by the thermal simulations of an 8-layer memory stack on a high-power SoC utilizing a granular Chip Thermal Model (CTM). The results demonstrate that the SoC-adjacent memory die has the highest thermal risk and the strategies can reduce its spatial temperature gradient by up to 25%. This work provides a practical, early-stage STCO solution for maintaining memory reliability and functional integrity in advanced 3D integrated systems.

People

Yuan Chen

WITMEM

Mingyang Liu

Beijing Zhicun (Witmem) Technology Co., Ltd

yu tian

Runjian Wang

Yue Heng

Hangzhou Zhicun (Witmem) Technology

hengzhi hu

Witintech

Yi Chen

Engineering Poster

Enhancing UVM RAL for Secure and Privileged Flash Memory Interface Verification Using Cadence AMBA VIP

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionEmbedded non-volatile memory (NVM) interfaces in next-generation microcontrollers demand rigorous verification of security and privilege semantics. While the UVM Register Abstraction Layer (RAL) standardizes register access, it offers limited control over bus-level attributes required for validating secure and protected transactions. This work introduces an enhanced user adapter layer for Cadence AMBA AHB VIP, enabling verification of four distinct access modes: Privileged-Secure, Privileged-Nonsecure, Unprivileged-Secure, and Unprivileged-Nonsecure.
Our methodology integrates an extension class within the UVM RAL flow to propagate HPROT and HNONSEC attributes through reg2bus APIs, preserving abstraction while ensuring full control over secure and protected semantics. The solution extends the default adapter, which traditionally transfers data using a fixed uvm_reg_bus_op structure, by declaring an extension class handle in reg2bus. Results demonstrate improved regression stability, reduced debug effort, and systematic coverage closure without sacrificing portability. This approach strengthens verification efficiency and confidence for advanced memory interfaces in safety-critical and secure applications.

People

Research Manuscript

EPAR: Electromagnetic Pathways to Architectural Reliability in Quantum Processors

10:30am - 10:43am PDT Tuesday, July 28 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionAs superconducting processors scale, understanding how physical layout shapes qubit interactions is essential for architectural reliability. Existing methods offer limited insight into how electromagnetic design choices translate into execution-level behavior. We present EPAR, an electromagnetic-to-architecture framework that predicts robustness early directly from physical design by reconstructing how design distortion modifies the effective Hamiltonian, reroutes mediated connectivity, and influences control-pulse response. Across all tested layouts, EPAR's structural scores show 100% agreement with two-qubit error trends yet reveal over 10x robustness differences among edges with identical calibrated error rates, going beyond conventional metrics to provide improved and actionable compiler guidance.

People

Navnil Choudhury

Rensselaer Polytechnic Institute

Yizhuo Tan

Yale University

Jiaqi Yu

Jakub Szefer

Epicell: Electro-Physical Co-Modeling for Standard Cell PPA Prediction

Kanad Basu

RPI

Research Manuscript

2:21pm - 2:34pm PDT Tuesday, July 28 Mtg Room 101B

EDA

EDA8. Design for Manufacturability and Reliability

DescriptionIn advanced process nodes, the pursuit of extreme PPA optimization has driven an explosion in the demand for customized standard cells. To satisfy this demand, automated layout synthesis has been increasingly adopted to explore vast design spaces. However, this paradigm shifts the bottleneck from design creation to verification, as characterizing the massive volume of generated variants via SPICE is computationally prohibitive.
Meanwhile, conventional geometric heuristics fail to proxy PPA at advanced nodes due to dominant layout effects. Existing learning-based surrogates often lack the fidelity to capture these complex dependencies. To bridge this gap, we propose EPiCell, an electro-physical co-modeling framework for rapid PPA estimation. EPiCell features a Heterogeneous Graph Transformer (HGT) that explicitly models transistors, routing metals, and supply rails as distinct entities, unifying circuit topology with fine-grained layout geometry. By employing relation-aware attention, it effectively captures the non-local electro-physical interactions governing cell performance. Validated on a dataset of over 18,000 auto-generated layouts based on ASAP7, EPiCell achieves high fidelity against SPICE simulations, with low average prediction errors of 1.82% for leakage power, 4.01% for internal power, 3.06% for delay, and 3.29% for transition. Crucially, it demonstrates superior ranking consistency with SPICE, attaining a median Spearman Rank Correlation Coefficient of 0.90 for internal power, 0.81 for delay, and 0.70 for transition. This offers a scalable surrogate model to enable efficient design space exploration.

People

Wenbo An

ESCAPE: Elegant Scan Chain Activity Probability Establishment for Programmable Low-Power LBIST

Research Manuscript

2:08pm - 2:21pm PDT Wednesday, July 29 Mtg Room 202C

EDA

EDA9. Test, Validation and Silicon Lifecycle Management

DescriptionThis paper presents an Elegant Scan Chain Activity Probability Establishment (ESCAPE) architecture for programmable low power LBIST. In the designed low-power control circuit, a programmable probability generator periodically outputs a user-configurable sequence of probabilities to drive hold registers. A 2D AND-gate array formed by two groups of hold registers then produces a rich set of low-power control signals. By modulating the enable probability of the lockups situated before the phase shifter, ESCAPE achieves precise per-chain power management. Experimental results on industrial-scale designs demonstrate that, the proposed method achieves high coverage, while reducing peak power consumption and incurring lower hardware overhead.

People

Hairui Cai

Yumei Hu

Xiaohui Xue

Yaning Wang

Yu Huang

Zhouxing Su

Zhipeng Lv

Zezhong Wang

Xing Wang

Escaping Flatland: A Placement Flow for Enabling 3D FPGAs

Research Manuscript

5:06pm - 5:18pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

Description3D field-programmable gate arrays (FPGAs) promise higher performance through vertical integration. However, existing placement tools, largely inherited from 2D frameworks, fail to capture the unique delay characteristics and optimization dynamics of 3D fabrics. We introduce a 3D FPGA placement flow that integrates partitioning-based initialization, adaptive cost scheduling, refined delay estimation, and a simulated annealing move set — all targeted at 3D FPGA architecture. Together, these enhancements improve timing estimates and the exploration of layer assignments during placement. Compared to Verilog-To-Routing (VTR), our experiments show geometric-mean (max) critical-path delay reductions of ∼3% (∼7%), ∼2% (∼4%), ∼3% (∼8%), and ∼6% (∼18%) for four 3D architectures: 3D CB, 3D CB-O, 3D CB-I, and 3D SB, respectively. We also achieve geometric-mean (max) routed wirelength reductions of ∼1% (∼3%), ∼2% (∼8%), < 1% (∼5%), and ∼5% (∼10%), respectively. Our work will be permissively open-sourced on GitHub.

People

Cong "Callie" Hao

Andrew Kahng

Bodhisatta Pramanik

Ismael Youssef

Etch-Vigen: A Video Generation Model for Etching Simulation

Work in Progress

6:51pm - 6:52pm PDT Monday, July 27 Exhibit Hall

DescriptionWith the scaling down of integrated circuit dimensions and the increasing complexity of transistor structures, the role of etching in manufacturing has become increasingly critical. We propose an etching simulation approach based on a video generation model, which models the evolution of the etching process as a video generation task. By embedding frames into quantized latent codeword representations by VQ-VAE (Vector Quantized Variational Autoencoder) and leveraging a temporal autoregressive prediction model, we achieve generation model of the etching process. On both simulated and experimental data, we validate the effectiveness of our model. Our approach achieves a 6,000× speedup over the Monte Carlo method while reducing the simulation MAE (Mean Absolute Error) by 14.4% compared with the state-of-the-art video generation model. Furthermore, results generated by our video based model show strong agreement with experimental data.

People

Research Manuscript

Etherssd: An In-Storage Ethereum Analytics Platform with Minimized I/O and Authentication Overhead

4:42pm - 4:54pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionEthereum's massive data requires auxiliary proofs (e.g., Merkle proofs) for trusted queries, creating significant I/O and data movement overhead.

We introduce EtherSSD, an innovative in-storage Ethereum analytics platform with computational storage devices (CSDs) designed for real-time data analysis. EtherSSD bridges the semantic gap between the host and CSDs, dissolving authenticated data queries into flattened (highly concurrent) in-CSD page accesses with slashed I/O operations from the host side. Additionally, EtherSSD incorporates an authentication engine that offloads cryptographic verification computations from host CPUs. Evaluations under real-world workloads demonstrate that it reduces authenticated query execution time, particularly the I/O and authentication overhead.

People

Beijing institute of Technology, Zhuhai

Kecheng Huang

Excavating Consistency Across Editing Steps for Effective Multi-Step Image Editing

Research Manuscript

4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionMulti-step image editing with diffusion models typically requires repeatedly executing the inversion–denoising paradigm, which leads to severe challenges in both image quality and computational efficiency. Repeated inversion introduces errors that accumulate across editing steps, degrading image quality, while regeneration of unchanged background regions incurs substantial computational overhead. In this paper, we present ExCave, a training-free multi-step editing framework that improves both image quality and computational efficiency by excavating consistency across editing steps. ExCave introduces an inversion sharing mechanism that performs inversion once and reuses its consistent features across subsequent edits, thereby significantly reducing errors. To eliminate redundant computation, we propose the CacheDiff method that regenerates only the edited regions while reusing consistent features from unchanged background regions. Finally, we design GPU-oriented optimizations to translate theoretical gains into practical reductions in end-to-end latency. Extensive experiments demonstrate that ExCave achieves superior image quality and dramatically reduces inference latency, establishing a new paradigm for accurate and efficient multi-step editing.

People

Chunyu Qi

Zhuoran Song

Cheng Gu

Haibing Guan

Expcheck: Dynamic Expert-Aware Checkpointing for Mixture-of-Experts Based Models

Research Manuscript

4:30pm - 4:42pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionLarge-scale Mixture-of-Experts (MoE) models are pivotal in modern AI, yet their massive parameter size creates a "storage wall" for fault tolerance, where limited bandwidth restricts checkpoint frequency and risks significant wasted computation. We present "EXPCheck", a dynamic expert-aware checkpointing system designed to resolve the conflict between massive MoE states and limited persistence bandwidth. Grounded in the observation that expert activation is highly imbalanced, EXPCheck employs a novel "Aging-then-Greedy Expert Selection (AGES)" policy. AGES first enforces an age-based refresh for overdue "cold" experts to prevent indefinite staleness, and then greedily allocates the remaining persistence budget to frequently updated "hot" experts. Implemented on a production-scale training stack, EXPCheck significantly reduces persistence traffic and increases checkpoint frequency by at most 5× compared to full checkpointing, while maintaining downstream model accuracy comparable to standard methods.

People

Defense Innovation Institute

Chenchen Fu

Expertflow: Efficient Mixture-of-Experts Inference via Predictive Expert Caching and Token Scheduling

Research Manuscript

4:23pm - 4:36pm PDT Wednesday, July 29 Mtg Room 201B

AI5-II. AI/ML System and Platform Design

DescriptionSparse Mixture-of-Experts (MoE) models can outperform dense LLMs at similar computation, but their large expert parameters create high memory demand, making single-GPU deployment difficult. Offloading addresses this by storing inactive experts on CPU, yet static caches ignore dynamic routing and existing predictors for expert usage are often inaccurate or costly. We present ExpertFlow, a lightweight MoE inference system with a routing path predictor, a routing-aware token scheduler, and a predictive expert cache. Together, these components enable efficient expert loading and execution, reducing GPU memory by 93.72% and improving throughput by up to 10× on a single GPU.

People

Xin He

Shunkang Zhang

Harbin Institute of Technology, Shenzhen

Kaijie Tang

Shaohuai Shi

Harbin Institute of Technology, Shenzhen

Yuxin Wang

Hong Kong Baptist University

Zihao Zeng

Nanyang Technological University

Zhenheng Tang

Hong Kong University of Science and Technology (HKUST)

Xiaowen Chu

Haiyan Yin

Ivor Tsang

Yew Soon Ong

Exploiting Dependency and Parallelism: Real-Time Scheduling and Analysis for GPU Tasks

Research Manuscript

11:45am - 12:00pm PDT Wednesday, July 29 Mtg Room 202C

Systems

SYS3. Embedded Software

DescriptionWith the rapid advancement of Artificial Intelligence, the Graphics Processing Unit (GPU) has become increasingly essential across a growing number of safety-critical application domains.
Applying a GPU is indispensable for parallel computing; however, the complex data dependencies and resource contention across kernels within a GPU task may unpredictably delay its execution time.
To address these problems, this paper presents a scheduling and analysis method for Directed Acyclic Graph (DAG)-structured GPU tasks.
Given a DAG representation, the proposed scheduling scales the kernel-level parallelism and establishes inter-kernel dependencies to provide a reduced and predictable DAG response time.
The corresponding timing analysis yields a safe yet non-pessimistic makespan bound without any assumption on kernel priorities.
The proposed method is implemented using the standard CUDA API, requiring no additional software or hardware support. Experimental results under synthetic and real-world benchmarks
demonstrate that the proposed approach effectively reduces the worst-case makespan and measured task execution time compared to the existing methods up to $32.8\%$ and $21.3\%$, respectively.

People

Yuanhai Zhang

Songyang He

Ruizhe Gou

Hunan Univiersity

Mingyue Cui

Boyang Li

Shuai Zhao

Exploiting Function-Family Structure in Analog Circuit Optimization

Kai Huang

Sun Yat-Sen University

Research Manuscript

5:06pm - 5:18pm PDT Wednesday, July 29 Mtg Room 101B

EDA

EDA6. Analog CAD, Simulation, Verification and Test

DescriptionAnalog circuit optimization is typically framed as black-box search over arbitrary smooth functions, yet device physics constrains performance mappings to structured families: exponential device laws, rational transfer functions, and regime-dependent dynamics. Offthe-shelf Gaussian-process surrogates impose globally smooth, stationary priors that are misaligned with these regime-switching primitives and can severely misfit highly nonlinear circuits at realistic sample sizes (50–100 evaluations). We demonstrate that pretrained tabular models encoding these primitives enable reliable optimization without per-circuit engineering. Circuit Prior Network (CPN) combines a tabular foundation model (TabPFN v2) with Direct Expected Improvement (DEI), computing expected improvement exactly under discrete posteriors rather than Gaussian approximations. Across 6 circuits and 25 baselines, structure-matched priors achieve R2 ≈ 0.99 in small-sample regimes where GP-Matérn attains only R2 = 0.16 on Bandgap, deliver 1.05–3.81× higher FoM with 3.34–11.89× fewer iterations, and suggest a shift from handcrafting models as priors toward systematic physics-informed structure identification. Our code will be made publicly available upon paper acceptance.

People

University of Sheffield

Research Manuscript

Exploiting Movable Logical Qubits for Lattice Surgery Compilation

2:08pm - 2:21pm PDT Tuesday, July 28 Mtg Room 203AB

Design

Quantum

DES6. Quantum Computing

DescriptionLattice surgery is among the leading schemes for fault tolerant quantum computing motivated by superconducting hardware. Conventional lattice surgery compilation schemes follow a place-and-route paradigm, where logical qubits remain statically fixed in space throughout the computation. In this work, we introduce a paradigm shift by exploiting movable logical qubits via teleportation during the lattice surgery CNOT gate. We propose a proof-of-concept compilation scheme leveraging these movements, which can substantially reduce the routed circuit depth. This demonstrates that movable logical qubits can be used even on hardware with static physical qubits. An open-source implementation will be made available on GitHub.

People

Laura Herzog

Technical University Munich

Technical University of Munich

Research Manuscript

Exploiting Per-Core Leakage: Electromagnetic Side-Channel Monitoring of Multicore Architectures

10:56am - 11:10am PDT Tuesday, July 28 Mtg Room 202AB

Security

SEC3-I. Hardware Security: Attack and Defense

DescriptionMulticore processors are increasingly adopted in embedded systems to meet growing performance demands. However, physical side-channel analysis of multicore architectures remains underexplored, as obtaining usable leakage is inherently challenging. Consequently, side-channel security research on such systems has lagged far behind, leaving a critical security gap. To address this gap, we reveal the electromagnetic leakage mechanisms in multicore architectures and, for the first time, demonstrate per-core leakage exploitation, thereby enabling physical side-channel analysis for these systems. As a practical extension, we present a non-intrusive side-channel monitoring method that achieves per-core granularity. To validate its feasibility and practicality, we implement a prototype on a heterogeneous SoC platform with an RF front-end, and evaluate on a commercial off-the-shelf quad-core embedded system, the Raspberry Pi 4B with ARM Cortex-A72 cores.

People

Agency for Defense Development

Heeseok Kim

Korea University

Seokhie Hong

Independent Researcher

Research Manuscript

Exquant: Global Expert Ranking–guided Mixed-Precision Quantization for Efficient MoE Inference

3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 101B

AI2-I. AI/ML Algorithms and Models

DescriptionMixture-of-Experts (MoE) large language models (LLMs) leverage dynamic routing and sparse activation to improve efficiency and scalability, achieving high performance with reduced computational cost. However, their complex architecture and large memory footprint pose significant challenges for deployment, particularly on resource-constrained hardware.
Post-training quantization (PTQ) is a widely used technique to reduce model size and memory usage. Existing PTQ approaches for MoE models are predominantly layer-wise and task-agnostic, optimizing reconstruction error independently within each layer. As a result, they ignore cross-layer differences in expert importance and fail to leverage task-specific signals, causing pivotal experts to be over-compressed, rarely activated experts to be over-provisioned, and overall accuracy to degrade.
To overcome these limitations, we propose ExQuant, a PTQ framework for MoE LLMs that enables global, expert-level mixed-precision quantization. ExQuant first constructs a Globally Comparable Expert Importance Metric by integrating expert routing frequency and post-ablation performance. Based on this metric, it assigns tiered bit-widths to experts and employs a precision-aware load balancing strategy to dynamically schedule computation across processing elements, fully exploiting slack between low- and high-precision workloads. Experiments demonstrate that ExQuant significantly reduces memory footprint, improves inference efficiency, and achieves $2.87-5.93\%$ accuracy improvement over existing MoE quantization methods. These results validate the effectiveness of global, expert-level mixed-precision quantization for efficient and accurate deployment of MoE LLMs.

People

Chenyang Guan

Fangxin Liu

Junjie Wang

Ning Yang

Haibing Guan

EXRA: Efficient Execution of Data-Dominated Applications via ISA Extensions for Expandable Register Files

Research Manuscript

2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 203C

Systems

SYS4. Embedded System Design Tools and Methodologies

DescriptionModern processor architectures typically employ a fixed, small register file, which is well-suited for most computations due to its simplicity, energy efficiency, and ease of implementation. However, data-intensive applications often suffer from limited register availability; simply enlarging the register file increases code size, pressures the instruction cache, complicates decoding, and raises power consumption. To address these challenges, we propose an extension to the legacy RISC-V Instruction Set Architecture (ISA) that supports an expandable register file. Our design partitions the register file into multiple logical banks, each mirroring the standard 32-register configuration, allowing operands and destination registers to reside in different banks concurrently. We introduce instruction extensions, overhead reduction mechanisms, and exception-handling infrastructure to fully exploit the expanded register space on a scalar processor. The approach is implemented on the CVA6 CPU, a 6-stage RISC-V processor, and deployed on an FPGA with only 27% hardware overhead. Experimental results demonstrate substantial performance improvements: matrix multiplication achieves 60% speed-up with 17% energy reduction, convolutions improve by 48% with 22% energy reduction, and convolutional neural networks such as ResNet-50 achieve 83.5% speed-up with 45% energy reduction.

People

The University of Sydney

Research Manuscript

E³-CODE: Embedded and Efficient Error-Correcting Code for Error-Resilient Neural Networks

10:30am - 10:43am PDT Tuesday, July 28 Mtg Room 202C

Systems

SYS2. Design of Cyber-Physical Systems and IoT

DescriptionNeural networks are widely deployed at the edge to process high-
dimensional sensor data, but they are susceptible to burst errors that
can corrupt weights and degrade inference accuracy. Conventional
error-correcting codes (ECC) mitigate errors but incur significant
memory overhead. Recent ECC methods for neural networks over-
write the least significant bits of the model weights with parity bits,
providing zero-overhead resilience at the expense of slightly re-
duced inference accuracy. In this paper, we propose a framework for
Embedded and Efficient Error-Correcting Code for Error-Resilient
Neural Networks called (E3-CODE). The proposed method embeds
multi-bit parity within the entire weight representation, which is
different from only modifying the LSBs of the weights. To mini-
mize the negative impact from the parity embedded ECC, weight
and parity assignments are jointly optimized via a mixed-integer
linear programming (MILP) formulation. We also propose a hybrid
ECC scheme that combines the embedded ECC with conventional
ECC to trade-off minor memory overhead for significantly im-
proved reliance. The experimental evaluation on the ImageNet and
CIFAR-10 datasets using ResNet, MobileNetV2, and EfficientNet-B0
demonstrates that E3-CODE maintains software-level accuracy in
the presence of burst errors. Compared with prior methods, the
lifetime of the edge system is extended by 4.8𝑋 with no memory
overhead and 10𝑋 with less than 2% memory overhead.

People

Venkata Nithin Kamineni

Habibur Rahaman

Ovishake Sen

Baibhab Chatterjee

SWARUP BHUNIA

Rickard Ewetz

Factored Floating-Point MAC: Eliminating Redundant Normalization for Energy-Efficient Systolic Arrays

Research Manuscript

3:54pm - 4:06pm PDT Monday, July 27 Mtg Room 203AB

Design

DES4. Digital and Analog Circuits

DescriptionFloating-point multiply-accumulate (FPMAC) is crucial in scientific computing, machine learning, and graphics but remains a major performance and energy bottleneck. Conventional IEEE-754 FP-FMA schemes optimize single multiply-add fusion but overlook long-chain MAC patterns in GEMM, leading to redundant rounding and normalization, accumulated numerical error, and high delay and power overhead from wide carry-propagate adders (CPAs). We propose Factored-FPMAC (F-FPMAC), which employs 4:2 carry-save adders (CSAs) and CSA-based redundant representation inside systolic arrays to eliminate CPAs from processing elements and defer normalization to a unified post-processing stage. To prevent accumulated intermediate value overflow (AIVO) under deferred normalization, we introduce a lightweight hierarchical risk-aware boundary protection mechanism. To further reduce register overhead from redundant representation, we replace per-PE dual buffers with an array-shared buffer pool. Experimental results indicate that F-FPMAC reduces critical-path delay by 61.9%, lowers power consumption by 22.6%, improves energy efficiency by 3×, achieves nearly two orders of magnitude lower numerical error, and decreases overflow events by up to 44.5%.

People

Hao Xiong

Zhichao Rui

Zhijie Yang

Rui Gong

Lei Wang

Fair Play in the Multiplex: Formal Verification of Complex Arbmux Designs

Engineering Poster

3:00pm - 4:00pm PDT Wednesday, July 29 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionModern digital systems rely heavily on interconnects capable of servicing multiple requesters efficiently and fairly. Traditional arbitration logic often fails in handling complex, multi-flit, and overlapping transactions typical of today's system-on-chip (SoC) designs. To address these limitations, arbiter-multiplexer (arbmux) architectures have emerged as a promising solution, combining arbiters with multiplexers to handle variable-length, multi-port transfers. However, the increased complexity of arbmux structures poses substantial challenges for formal verification, particularly when conventional fairness properties yield spurious failures or miss critical bugs. This work presents a comprehensive comparative study and methodological advancement in the formal verification of arbmux fairness.

We introduce a novel formal verification approach, unlike traditional methods, this technique enables assertion of liveness and fairness properties only during meaningful protocol intervals, sharply reducing assertion noise and increasing the precision of bug detection. Parameterized assertion code, supported by symbolic indices, further boosts the scalability and generality of the method, facilitating application to arbitrarily complex, multi-port arbmuxes. Through practical case studies, we demonstrate that our approach detects subtle protocol violations, including premature grant switching and potential requester starvation—issues that elude prior techniques due to inadequate property focus or over-constrained assumptions.

Quantitative and qualitative results establish the superiority of our enhanced methodology: bug counterexamples are more interpretable, assertion code is more maintainable, and formal runs achieve greater coverage within manageable computational resources. Critically, we show that tracking active transactions is essential to distinguish between acceptable protocol behavior and real fairness failures, enabling designers to close the gap between specification and implementation. Ultimately, this work lays the foundation for a reusable plug-in framework for arbmux verification, providing the industry with scalable, robust, and insightful mechanisms to ensure fairness and liveness in next-generation communication fabrics.

People

Work in Progress

Fast and Accurate RRAM Write-and-Verify via Hadamard-Encoded Read and ADC-Energy-Reduced HARP

6:56pm - 6:57pm PDT Monday, July 27 Exhibit Hall

DescriptionWe propose two circuit-aware write–verify (WV) schemes for resistive-RAM (RRAM)–based analog compute-in-memory (ACiM) that reduce the dominant cost of analog-to-digital converters (ADCs). Hadamard-Encoded Parallel-Verify (HD-PV) improves readout signal-to-noise ratio through Hadamard-driven vector sensing and inverse decoding, enhancing robustness without added analog hardware. Hadamard-based ADC-Energy-Reduced Parallel-Verify (HARP) preserves this SNR benefit while replacing full successive-approximation-register (SAR) conversions with one-shot decisions, lowering energy. On CIFAR-10, conventional WV suffers large accuracy loss, whereas HD-PV and HARP keep degradation under 3% and offer up to 3× speedup, with HARP achieving the lowest overall energy.

People

Ilhuan Choi

Jiwon Yoo

Yonsei University

Yoona Lee

Yewon Jeong

Jason Lee

Woo-Seok Choi

Fast Template Matching for Quantum Circuits Using Hypergraph

Research Manuscript

1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 201B

Design

Quantum

DES6. Quantum Computing

DescriptionQuantum circuit optimization is a key step toward the efficient execution of quantum algorithms. Template matching has emerged as one of the dominant approaches for simplifying quantum circuits, yet it confronts the intrinsic challenge of accommodating gate commutativity. The state-of-the-art template-matching algorithm relies on a directed acyclic graph (DAG) representation. While this DAG-based technique handles gate commutativity satisfactorily, it fails to preserve the local connectivity inherent to quantum circuits, thereby leading to relatively high matching complexity.

In this paper, we introduce a hypergraph representation (HG), a commutativity-aware representation that collapses commuting gates into a single super-node while retaining all local connectivity. This enables matches to be extended locally without revisiting the rest of the circuit, with incremental updates limited to the immediate neighborhood.
Experimental results demonstrate that our HG matcher achieves 11--606x speed-up over the DAG-based implementation in Qiskit (Iten et al., 2022) on both random and arithmetic benchmarks, while maintaining the same optimization quality. The acceleration increases with circuit size, confirming that preserving locality and connectivity is the key to scalable quantum circuit optimisation.

People

Xin Hong

Arclight Quantum Computing Inc.

Jintao Yu

Runhong He

Shenggang Ying

Faster-MoA: Low-Latency Tree-Structured MoA Serving with Early Exit and Agent-Aware Prefill-Decode Overlap

Research Manuscript

2:34pm - 2:47pm PDT Monday, July 27 Mtg Room 101B

AI3-I. AI/ML Application and Infrastructure

DescriptionMixture-of-Agents (MoA) is a widely adopted multi-agent paradigm, but existing MoA systems face two major challenges: excessive agent-to-agent connectivity and poor hardware efficiency. To address these two issues, we propose Faster-MoA, a unified algorithm-system co-design for efficient MoA serving. Faster-MoA has three innovations. First, we replace the conventional all-to-all topology with a hierarchical tree structure that introduces structured sparsity in agent connections. Second, we develop a run-time dynamic agent early-exit mechanism that prunes unnecessary agent connections basing on output semantic similarity and answer confidence. Third, we propose an agent-dependency-aware incremental prefilling mechanism that overlaps prefilling and decoding among agents with data dependencies to reduce inference latency. Together, these three innovations enable Faster-MoA to reduce end-to-end serving latency by up to 90% while achieving similar (only ±1% variation) or even higher task accuracy compared with MoA baselines using all-to-all agent connection.

People

Zijun Wang

Yijiahao Qi

Hanqiu Chen

Zishen Wan

FBS: Accelerating CNN Inference over RNS-CKKS with Fewer Bootstrapping Sparsity

Research Manuscript

10:56am - 11:10am PDT Monday, July 27 Mtg Room 203C

Security

SEC1. AI/ML Security/Privacy

DescriptionRNS-CKKS is a fully homomorphic encryption scheme supporting fixed-point arithmetic, widely used in privacy-preserving convolutional neural network (CNN) inference.
However, its significant computational overhead, especially from bootstrapping—the most costly operation—raises deployment costs for CNN inference over RNS-CKKS.
While sparsity has proven effective in reducing computational overhead for unencrypted CNN inference, its application to large datasets (e.g., ImageNet) with RNS-CKKS-based CNN inference remains under-explored, particularly in optimizing bootstrapping operations that dominate computation time.
In this work, we observe that sparsity in CNN can be exploited to reduce the bootstrapping overhead in RNS-CKKS-based CNN inference.
Based on this observation, we propose FBS, a framework that accelerates CNN inference over RNS-CKKS by leveraging Fewer Bootstrapping Sparsity to reduce bootstrapping costs.
We propose two sparsity patterns: eliminate missing input sparsity pattern and channel sparsity pattern, to reduce the number of bootstrapping calls during CNN inference.
An iterative latency optimization framework is then presented to identify the key layers for pruning and determine the sparsity patterns to achieve effective performance.
Results show that FBS can accelerate CNN inference over RNS-CKKS by up to 1.91 times with negligible accuracy loss.
FBS will be open-sourced.

People

Xi'an JiaoTong University

Research Manuscript

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration

3:54pm - 4:06pm PDT Tuesday, July 28 Mtg Room 202C

Design

DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures

DescriptionWith the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms.
Prior works discuss dedicated architectures to achieve maximal resource efficiency. However, a mismatch between hardware and workloads always exists in various diverse workloads.
Other works discuss overlay architecture that can dynamically switch dataflow for different workloads.
However, these works are still limited by flexibility granularity and induce much resource inefficiency.

To solve this problem, we propose a flexible composing architecture, FILCO, that can efficiently match diverse workloads to achieve the optimal storage and computation resource efficiency. FILCO can be reconfigured in real-time and flexibly composed into a unified or multiple independent accelerators. We also propose the FILCO framework, including an analytical model with a two-stage DSE that can achieve the optimal design point. We also evaluate the FILCO framework on the 7nm AMD Versal VCK190 board. Compared with prior works, our design can achieve 1.3x - 5x throughput and hardware efficiency on various diverse workloads.

People

Wayne State University

Weisong Shi

University of Delaware

Peipei Zhou

Brown University

Research Manuscript

Finding Behavior Bugs in IoT Messaging Protocols with Automated Oracle Generation and Monitoring

12:00pm - 12:15pm PDT Wednesday, July 29 Mtg Room 202C

Systems

SYS3. Embedded Software

DescriptionIoT messaging protocols face critical security risks from behavior bugs - specification violations that enable unauthorized data access and device compromise. Detecting such bugs requires comprehensive understanding of protocol specifications and communication semantics. This paper introduces ARES, a fully automated framework that extracts executable behavior oracles from protocol specifications for real-time compliance monitoring using LLM-driven behavior filtering. ARES evaluates six widely-used IoT protocol implementations, identifying 25 new bugs with 87.5% precision, including 21 behavior bugs. Of these, 18 have been confirmed or fixed and 10 CVEs assigned due to their severity.

People

Qingpeng Du

Zhengxiong Luo

First-Time-Right Power Analysis: Data-Driven Test Selection Through Real-Time Validation of Clocks, Gating and Traffic-Dependent Metrics

Engineering Poster

5:00pm - 6:00pm PDT Monday, July 27 DAC Pavilion, Exhibit Floor

Chiplet

Design

EDA

Quantum

Security

Systems

DescriptionPower signoff demands high-quality test selection, yet teams submit comprehensive suites to power estimation tools like Synopsys PrimePower without quantitative pre-validation. We present a real-time power validation framework with parallel analysis engines extracting multi-dimensional metrics—clock behavior, gating patterns, switching activity, bandwidth profiles—from design verification artifacts during active DV cycles.

Core technical innovation: multi-factor validation under live traffic reveals issues invisible to traditional approaches. Frequency correctness measured under realistic workloads detects violations missed by static checks. Dynamic gating analysis discovers transient efficiency degradation during burst-to-idle transitions—overlooked by idle-only validation. Rolling window bandwidth analysis surgically identifies peak power windows, while activity profiling quantifies switching intensity with documented confidence scores. Packet trace integration enables perf/watt correlation and traffic quality validation.

The framework enables Week 1-2 issue detection versus Week 5-6+ post-formal-tool feedback—fixing when design is fluid versus frozen. Test selection algorithms reduce submissions from dozens to 5-8 representative vectors with quantified coverage. Rapid test swapping completes in minutes versus multi-day formal tool queuing, enabling same-day hypothesis testing via pre-computed scores. Self-service architecture eliminates cross-team overhead, scaling from small IP blocks (minutes) to complex SoCs (hours).

Production deployment demonstrates 4× reduction in formal tool compute, Week 1 detection of dynamic gating issues, and surgical peak-window submission enabling first-time-right results.

People

Vinoth Selvan

FLASH3D: A Fast Layered Analytical Solver for High-Accuracy Steady-State Thermal Simulation of 3D ICs

Research Manuscript

5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 202AB

EDA

EDA4. Power Analysis and Optimization

DescriptionHigh-accuracy thermal simulation is essential for modern 3D integrated circuits (ICs), but its high computational cost often hinders early-stage, thermal-aware design. To address this, we propose
FLASH3D, a fast and versatile analytical simulator for 3D steady-state thermal analysis. FLASH3D integrates spectral modal decomposition, the transfer matrix method, and an accelerated power decomposition algorithm to compute 3D temperature distributions efficiently and accurately. Compared with COMSOL, FLASH3D achieves over four orders of magnitude speedup, reducing computation time from minutes to milliseconds while maintaining a maximum absolute error below 0.5 K. Compared to the state-of-the-art machine learning (ML) method DeepOHeat, within a single inference time, FLASH3D can compute the temperature distribution of roughly 2000 slices and attains approximately 10× lower error. Furthermore, FLASH3D supports complex boundary conditions and fine-grained power maps, including curved-edge and standard-cell-level distributions, overcoming the limitations of conventional analytical methods. These features make FLASH3D an efficient, reliable, and scalable tool for early-stage thermal-aware design, providing a solid foundation for thermal optimization of large-scale 3D ICs.

People

Research Manuscript

Flashfps: Efficient Farthest Point Sampling for Large-Scale Point Clouds via Pruning and Caching

5:18pm - 5:30pm PDT Wednesday, July 29 Mtg Room 101A

AI2-II. AI/ML Algorithms and Models

DescriptionPoint-based Neural Networks (PNNs) have become a key approach for point cloud processing.
However, a core operation in these models, Farthest Point Sampling (FPS), often introduces significant inference latency, especially for large-scale processing.

Despite existing CUDA- and hardware-level optimizations, FPS remains a major bottleneck due to exhaustive computations across multiple network layers in PNNs, which hinders scalability.
Through systematic analysis, we identify three substantial redundancy in FPS, including unnecessary full-cloud computations, redundant late-stage iterations, and predictable inter-layer outputs that make later FPS computations avoidable.

To address these, we propose FlashFPS, a hardware-agnostic, plug-and-play framework for FPS acceleration, composed of FPS-Prune and FPS-Cache. FPS-Prune introduces candidate pruning and iteration pruning to reduce redundant computations in FPS while preserving sampling quality, and FPS-Cache eliminates layer-wise redundancy via cache-and-reuse. Integrated into existing CUDA libraries and state-of-the-art PNN accelerators, FlashFPS achieves 5.16× speedup over the standard CUDA baseline on GPU and 2.69× on PNN accelerators, with negligible accuracy loss, enabling efficient and scalable PNN inference.

People

Research Manuscript

Flashhd: A Flash-Based In-Storage Hyperdimensional Computing Framework for Hierarchical Sequence Matching

4:18pm - 4:30pm PDT Wednesday, July 29 Mtg Room 203C

Systems

SYS5. Embedded Memory and Storage Systems

DescriptionThe rapid growth of DNA data makes exact sequence matching a central task in bioinformatics. These applications are both compute- and memory-intensive due to exhaustive database scans. However, conventional systems suffer from high I/O overhead caused by frequent page faults when memory capacity is limited. We propose FlashHD, an in-storage sequence matching framework that executes exact matching directly inside 3D NAND flash. FlashHD employs a hierarchical hyperdimensional computing architecture that filters dissimilar sequences across multiple stages while preserving full recall. FlashHD introduces a hierarchy-aware hyperdimensional architecture search that automatically tunes HDC hyperparameters for low latency and energy to optimize the hierarchical searching. Our evaluation reveals that FlashHD significantly outperforms other state-of-the-art systems.

People

Wen-Hsin Liu

Chieh-Lin Tsai

National Taiwan University (NTU)

Wen Sheng Lim

Ray-Ting Huang

Macronix International Co., Ltd.

Han-Wen Hu

Tei-Wei Kuo

Yuan-Hao Chang