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Xi Li
University of Science and Technology of China
Presentations
Research Manuscript
Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
11:23am - 11:36am PDT Wednesday, July 29 Mtg Room 203C
Systems
SYS6. Time-Critical and Fault-Tolerant System Design
Research Manuscript
Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
11:50am - 12:03pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Late Breaking Results
Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
6:21pm - 6:24pm PDT Monday, July 27 Exhibit Hall