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Lei Gong
University of Science and Technology of China
Presentations
Research Manuscript
Actionflow: A Pipelined Action Acceleration for Vision Language Models on Edge
1:55pm - 2:08pm PDT Wednesday, July 29 Mtg Room 203C
Systems
SYS1. Autonomous Systems (Automotive, Robotics, Drones)
Research Manuscript
SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
3:30pm - 3:42pm PDT Monday, July 27 Mtg Room 202C
Design
DES1-I. SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Idealsim: Efficient Ideal Scenario Modeling for Processor Upper-Bound Performance Analysis
2:21pm - 2:34pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
Efficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks
11:50am - 12:03pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis
Research Manuscript
Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle
5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 101B
AI
AI2-I. AI/ML Algorithms and Models
Late Breaking Results
Late Breaking Results: Efficient MoE-ViT Gating on Edge Accelerator via Dynamic Expert Routing and Quantized Router
5:45pm - 5:48pm PDT Monday, July 27 Exhibit Hall
Research Manuscript
Scheduling Cause-Effect Chains Without Timing Anomalies in End to End Latency
11:23am - 11:36am PDT Wednesday, July 29 Mtg Room 203C
Systems
SYS6. Time-Critical and Fault-Tolerant System Design
Research Manuscript
CHiRM-DSE: CodeLLM-Based Hierarchical and Rule-Mining Guided DSE for FPGA Accelerators
10:30am - 10:43am PDT Monday, July 27 Mtg Room 201B
EDA
EDA5. RTL/Logic Level and High-level Synthesis