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Leilei Jin
The Chinese University of Hong Kong
Presentations
Research Manuscript
RTL-3D: Timing-Aware Tier Partitioning for 3D ICs Using Pre-Synthesis Timing Analysis
10:56am - 11:10am PDT Monday, July 27 Mtg Room 202AB
EDA
EDA3. Timing Analysis and Optimization
Research Manuscript
BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/ground Plane Synthesis
3:42pm - 3:54pm PDT Monday, July 27 Mtg Room 202AB
EDA
EDA4. Power Analysis and Optimization
Research Manuscript
DiffDEG: Diffusion-Enhanced Design Evolution Graph Representation Learning for Post-Layout Optimization
1:42pm - 1:55pm PDT Tuesday, July 28 Mtg Room 101A
AI
AI3-II. AI/ML Application and Infrastructure
Research Manuscript
Mixed-Structure Double-Sided Redistribution Layer Routing for Glass Interposer-Based 5.5D ICs
4:30pm - 4:42pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
Flexicts: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs
1:30pm - 1:42pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package
Research Manuscript
BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs
2:08pm - 2:21pm PDT Monday, July 27 Mtg Room 201B
Chiplet
EDA
EDA1. Design Methodologies for System-on-Chip and 3D/2.5D System-in-Package