Presenter <Full Program · Contributors · Organizations · Search Program · Flagged · My Recommendations · Happening NowMore…Search ProgramFlaggedMy RecommendationsHappening NowHaoran XueUniversity of Science and Technology of ChinaPresentationsResearch ManuscriptEfficient HLS Accelerator Floorplan on Multi-Die FPGA Aided by Graph Neural Networks11:50am - 12:03pm PDT Monday, July 27 Mtg Room 201BEDAEDA5. RTL/Logic Level and High-level Synthesis
