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Haodong Lu
Fudan University
Presentations
Research Manuscript
Drcagent: A Design Rule Aware LLM Agent for DRC Auto-Fix with Adversarial Reinforcement Learning
5:06pm - 5:18pm PDT Monday, July 27 Mtg Room 101A
AI
AI1. AI/ML Frontiers for Hardware Design
Research Manuscript
AccDRC: FPGA Acceleration for VLSI DRC with Cell-Aware Layout Partitioning
5:18pm - 5:30pm PDT Monday, July 27 Mtg Room 201B
EDA
EDA2. Design Verification and Validation
Research Manuscript
DRCGen: A Controllable DRC Violation Case Generator with Cross-PDK Transferability for Rule-Deck and Tool Validation
4:42pm - 4:54pm PDT Tuesday, July 28 Mtg Room 202AB
EDA
EDA7-I. Physical Design and Verification
Research Manuscript
Duet: Exploiting High-Order Lossless Sparsity for Bit-Serial Transformer Acceleration via Distribution-Aware Pruning
10:56am - 11:10am PDT Wednesday, July 29 Mtg Room 101B
AI
AI5-I. AI/ML System and Platform Design